Full catalogue

Generated by .claude/skills/review-gateware-project/gen_catalogue.py from data/catalogue.json. Do not edit by hand.

Toolchain: open = yosys + nextpnr-ecp5 + ecppack (incl. via apio/LiteX/ghdl plugin), diamond = Lattice Diamond, both = both build paths exist. License none found = no license file/header found (all rights reserved by default; ask the author before reusing). Fork column: which copy to prefer when several clones exist.

At a glance

• 523 repositories catalogued.
• Gateware toolchains: open 393, both 36, diamond 28, n/a 18, unknown 7.
• 222 repositories have no license found.
• 322 repositories have some detected testbench/simulation setup (heuristic scan; see “Testbenches and simulation” below).
• 125 repositories have a Makefile target that runs a testbench/simulation/formal check (make_tests).
• 122 repositories target a non-ECP5 FPGA (iCE40 UP5K etc., marked NOT ECP5 in the FPGA column): abhinavputhran__ttysky-raycast-test, agamez__whisperice, alangarf__apple-one, alberto-grl__1bitsdr, alhusseingamal__r2sdf-fft, apfaudio__eurorack-pmod, aravindrajeshkanna__vernier-rv32, asinghani__advent-of-hardcaml-2025, badgeteam__mch2022-firmware-ice40, bit-hack__icesid, bnossum__midgetv, bonfireprocessor__bonfire-core, cariboulabs__cariboulite, carlosedp__chisel-fpga-pinfinder, ckdur__riscvconsole, cliffordwolf__icotools, cube1us__ibm1410fpga, daglem__redip-sid, damdoy__ice40_ultraplus_examples, dangerousprototypes__buspirateultrahdl, danielh186__6502-tapeout, daveshah1__pmods, daveshah1__up5k-demos, dibyx__flux, dylansebastianheredia__e155_tuner_project, emard__fpga_snake_game, emard__ledstrip, emard__ulx2s, emeb__iceradio, emeb__rpi_rxadc, emeb__up5k_osc, emeb__up5k_vga, enjoy-digital__litedsp, evgenymuryshkin__quokkaevaluation, fm4dd__pmod-7seg9, fm4dd__pmod-charlcd, fulig__tinyfpga_fft, gage1999__fpga-sdr-receiver, gergoerdi__advent-of-clash-2025, glasgowembedded__glasgow, google__cfu-playground, greatscottgadgets__hackrf, gtjennings1__hyperbus, hariharan6307-coder__verilog-goertzel-audio-visualizer, heichips__heichips25-template, hoglet67__ice40atom, hoglet67__ice40beeb, htfab__asicle2, ibm2030__ibm2030, icebreaker-fpga__icebreaker-verilog-examples, icebreaker-fpga__icebreaker-workshop, icebreaker-fpga__icetwang, im-tomu__foboot, im-tomu__fomu-workshop, ipmgroup__fftd, jamchamb__cojiro, jamesbowman__swapforth, joaln27__cordic, kbob__icebreaker-candy, kelu124__lit3rick, kelu124__un0rick, lawrie__blackicemxbook, lawrie__hdmi_examples, lawrie__verilog_examples, lazardjurovic__edulent_rtl, litex-hub__litex-boards, mattvenn__fpga-sdft, maxzischka1__fastfouriertransformproject, meharbaan2__systemverilog-ofdm-phy-core, michaelbell__nanov, mikeakohn__apollo11_fpga, mikeakohn__riscv_fpga, mmicko__fpga101-workshop, mole99__tt05-one-sprite-pony, msiddalingaiah__centurion, msinger__iceboy, mysteriouswolf__vna_fpga_dsp, mystorm-org__blackice-ii, nesl__ice40_examples, nickmqb__fpga_craft, nkrackow__singularitysurfer-fpga-lock-in-amplifier, no2fpga__no2bootloader, obijuan__open-fpga-verilog-tutorial, openconcepts-ar__accel2d, orbcode__orbtrace, osmocom__osmo-e1-hardware, osresearch__up5k, ox-computing__real-time-analytics-fpga, pablogs9__rocketfpga, pat-pgt__multifrequenciesdetector, pmezydlo__beaglewire, ranzbak__fpga-workshop, rhobbie__library704, romavis__lwdo-sdr-fw, rschlaikjer__fpga-3-softcores, rxrbln__picorv32, schlae__graphics-gremlin, smunaut__ice40-playground, smunaut__ice40linux, smunaut__mch2022-ice40, srjilarious__fpga_start, sylefeb__tinygpus, tinyfpga__tinyfpga-bootloader, tinyvision-ai-inc__pico-ice-sdk, toasterllc__mdccode, toni3141__rastericer, tvelliott__dsp_ice, ulixxe__usb_cdc, ultraembedded__core_ddr3_controller, vmware-archive__cascade, vyges__fast-fourier-transform-ip, wifiboy__ok-ice40pro, wren6991__riscboy, wren6991__smoldvi, wuxx__icesugar, x653__xv6-riscv-fpga, yosyshq__picorv32, zeldin__icegdrom, zipcpu__dblclockfft, zipcpu__icozip, zipcpu__sdr, zipcpu__sdspi.

Board, tools and infrastructure

Repo	What	FPGA	Toolchain	HDL	License	Active (first → last, commits)	Fork / preferred copy
alpin3__ulx3s	KOST docker/static bundle: yosys, trellis, nextpnr, ghdl+plugin, vhd2vl, Silice	n/a	open	Dockerfile	none found	2019-11-23 → 2020-10-12, 69	none
andreaspirklbauer__oberon-extended	Extended Oberon OS + Oberon-2 compiler	n/a	n/a	Oberon-2	none found	2021-06-11 → 2026-09-25, 124	none
basman74__next186	Next186 FleaFPGA Ohm Diamond archive	n/a	diamond	Verilog (zip only)	custom permissive	2018-02-03 → 2018-02-20, 14	upstream of emard__next186
dfiantworks__interactive-sim	interactive-sim: DPI/VPI/VHPI framework for live, viewer-driven HDL simulation controls (buttons/LEDs) over one TCP socket	n/a (simulation-only demo, no real ULX3S synthesis target)	n/a; iverilog + VPI simulation only, no FPGA synthesis toolchain invoked	Verilog (4 .v), VHDL (4 .vhdl), SystemVerilog (3 .sv), C++ (4 .cpp)	MIT	? → 2026-07-23, ?	none
dok3r__ulx3s-build	Docker env: Diamond 3.7 + alpin3 open tools	n/a	both	Dockerfile	none found	2020-01-01 → 2020-02-11, 4	none (uses alpin3 release)
dok3r__ulx3s-saxonsoc	Docker build of SaxonSoc SMP VexRiscv + OpenSBI + u-boot + buildroot	12F/25F/45F/85F (64MB → 85F)	open	none (shell)	none found	2020-01-12 → 2020-10-21, 34	none (original)
emard__esp32ecp5	esp32ecp5: MicroPython JTAG programmer for ECP5 from onboard ESP32, FTP/SD/DFU	n/a	n/a	MicroPython	MIT (pypi/LICENSE.txt)	2019-11-06 → 2025-09-14, 745	none
emard__fleafpga-jtag	FleaFPGA-JTAG: host CLI programmer for FleaFPGA boards, playing .vme (compiled ispVM/SVF) files over FTDI JTAG; Linux and Win32 builds	n/a (host tool) - programs FleaFPGA boards (Lattice devices) via .vme files; no ULX3S/ECP5 mention found	n/a (host tool); Makefile.linux / Makefile.win32, links FTDI D2XX (ftd2xx.h)	none (C: ivm_core.c, ispvm_ui.c, hardware.c; ~3 source files per platform dir, duplicated in -linux and -win32)	none found (license.txt is Lattice’s proprietary ispVM(TM) End User License Agreement, not a redistribution/OSI license)	? → 2019-05-21, ?	derived from Lattice’s ispVM(TM) ispVM_ui/ivm_core sources (license.txt header, ivm_core.c/ispvm_ui.c)
emard__libxsvf-esp	LibXSVF-ESP: ESP32/ESP8266 Arduino (X)SVF JTAG player, small fork of Clifford Wolf’s Lib(X)SVF for standalone or web-uploaded SVF programming of FPGAs	n/a (host/companion-MCU tool) - JTAG target is whatever Lib(X)SVF supports; README states tested on Lattice ECP5 and XP2 (README.md)	n/a; builds as an Arduino library (library.properties) for ESP32/ESP8266, not an FPGA toolchain	none (C: src/trunk/*.c ~7 files; C++/Arduino: src/LibXSVF.cpp + .ino examples, ~21 files total)	ISC (src/trunk/COPYING, Clifford Wolf/RIEGL header); no license file for the Arduino wrapper itself	? → 2018-11-28, ?	fork of Clifford Wolf’s Lib(X)SVF (src/trunk/, README.md); Arduino library wrapper added by emard
emard__st7789py_mpy	MicroPython ST7789 240x240 driver	n/a	n/a	MicroPython	MIT	2019-02-15 → 2020-02-14, 10	fork of devbis/st7789py_mpy
emard__ulx2s	ULX2S: KiCad hardware/PCB project documenting and reworking the predecessor ULX2S board (Lattice XP2); gerbers/footprints/schematic only, no gateware	Lattice XP2 (NOT ECP5) - doc/LatticeXP2-8Pinout.CSV; no HDL/gateware in this repo, only the board carrying the chip	n/a (PCB/KiCad project, no FPGA build); doc references the LatticeXP2-8Pin part only for footprint/pinout	none (0 .v/.vhd/.sv files found)	none found	? → 2017-11-21, ?	none; documents+reworks the original ULX2S board (original_gerbers/, doc/)
emard__ulx3s	ULX3S board hardware (KiCad), manual, reference LPFs	12F/25F/45F/85F	n/a	none (KiCad)	MIT-style with logo clause (LICENSE.md)	2016-01-28 → 2025-04-27, 2732	none
emard__ulx3s-bin	Prebuilt bitstreams + quickstart/self-test kit	12F/25F/45F/85F	n/a (diamond-era .vme + open .bit.gz)	none (binaries)	none found	2018-03-11 → 2022-04-19, 327	none
emard__wifijtag	WiFiJTAG: ESP8266 web SVF JTAG player	n/a	n/a	C++/Arduino	BSD-2-Clause-Views	2016-08-13 → 2017-08-06, 69	fork of gmag11/FSBrowserNG
enjoy-digital__litedsp	litedsp: Migen/LiteX portable RF/DSP block library incl. radix-2 SDF FFT/IFFT, Goertzel, Welch PSD, PFB channelizer	ECP5 LFE5UM5G-85F CABGA381 (impl/ecp5.py, out-of-context synth_ecp5 + nextpnr-ecp5 –um5g-85k, resource/Fmax characterization only, no full P&R/bitstream/board); also has impl/xilinx.py for Xilinx (NOT ECP5)	open; LiteX/Migen generates Verilog; impl/ecp5.py drives yosys synth_ecp5 + nextpnr-ecp5 –um5g-85k for out-of-context resource/Fmax characterization (no ecppack/bitstream)	Python/Migen (430 .py, litedsp/+test/+bench/+impl/); no hand-written Verilog/VHDL - RTL is generated at build/simulation time from Migen	BSD-2-Clause	? → 2026-09-24, ?	none
f32c__arduino	FPGArduino core source (Arduino for f32c), ULX3S board entry	12F/25F/45F/85F	n/a (f32c GCC + ujprog)	C/C++ (no HDL)	mixed LGPL-2.1+ (Arduino core), BSD-2 (Zec), BSD (Adafruit)	2015-02-28 → 2019-04-09, 767	none
f32c__fpgarduino	FPGArduino distribution: Boards Manager index + toolchains + prebuilt f32c ULX3S bitstreams	12F/25F/45F/85F	n/a (binaries from diamond)	none	none found	2019-03-05 → 2019-08-05, 13	companion of f32c__arduino
f32c__tools	ujprog (FT231X JTAG programmer, fujprog predecessor) + f32cup uploader	12F/25F/45F/85F	n/a	C, Python	BSD-2-Clause (ujprog)	2011-02-17 → 2026-05-11, 298	none
fm4dd__pmod-7seg9	7SEG9 PMOD: 9-digit 7-segment LED display PMOD board (TM1640 driver) with example driver code for ULX3S, IceBreaker, GateMate, Arduino and Raspberry Pi	ECP5 (ULX3S, examples/ulx3s/*/ulx3s.lpf); also NOT ECP5: iCE40 (IceBreaker, examples/icebreaker/) and Cologne Chip GateMate (NOT ECP5, examples/gatemate/, VHDL via GHDL+synth_gatemate); Arduino/Raspberry Pi examples are not FPGAs	open (yosys+nextpnr-ecp5 for ULX3S per examples/ulx3s Makefiles); GHDL+synth_gatemate for the GateMate VHDL examples (examples/gatemate/config.mk:38-41)	Verilog (26, PMOD driver + examples across boards), C/C++ (9, Raspberry Pi example)	CERN-OHL-S v1.2 (hardware, LICENSE header) - covers the PCB/hardware design	? → 2026-02-14, ?	none
ghaworth__ulx3s-bldc-foc	Planned open field-oriented-control BLDC/PMSM motor driver: FOC gateware track + companion open three-phase driver board (KiCad) for ULX3S — both tracks are currently empty skeletons	unspecified (Makefile default DEVICE=85k but comment says ‘confirm against your actual ULX3S variant, ships as 12F/25F/45F/85F’)	open; detail=yosys+nextpnr-ecp5+ecppack Makefile scaffold present and correctly written, but with zero rtl/*.v sources and no LPF file to build against	none (zero HDL files anywhere in the repo)	Apache-2.0 (gateware/LICENSE) + CERN-OHL-P-2.0 (hardware/LICENSE)	? → 2026-06-15, ?	none
gmejiamtz__ulx3s-components	Generic ‘ecp5-project-template’ (per its own README) — a Verilator/sv2v/Yosys/nextpnr-ecp5 project scaffold for ECP5/ULX3S with lint+sim+synth+GLS flow, containing only a trivial XOR-register demo module	12F (Makefile: nextpnr-ecp5 –12k –package CABGA381)	open; detail=sv2v (SystemVerilog->Verilog) + Yosys (tcl-driven) + nextpnr-ecp5 + ecppack, plus Verilator for lint/sim/gate-level-sim	SystemVerilog 2 files (rtl/top.sv trivial XOR-register + rtl/config_pkg.sv); depends on unfetched third_party/basejump_stl submodule for its dv/ testbench infrastructure	MIT	? → 2025-08-19, ?	none
goran-mahovlic__ulx3s-pmod	ULX3S extension/PMOD boards (KiCad): GPDI in/out, OV7670, LoRa, I2S, ENC28J60, SD, USB, PS/2, VGA, MIDI…	n/a	n/a (KiCad, KiKit)	none	MIT-style with RADIONA logo clause (LICENSE.md)	2018-11-25 → 2023-08-24, 194	none
intergalaktik__ulx4m-ls	ULX4M-LS PCB, ULX3S successor board hardware (KiCad); no gateware in this repo	ECP5 LFE5U-12F/25F/45F/85F-6BG381C (README “Main parts”); doc/Pinout.csv.license also ships ECP5UM5G-25/45/85 (SERDES-variant) pinout files for the optional PCIe/SerDes header (“Only available if ECP5 SerDes chip is used”)	n/a (KiCad hardware only, no gateware/build scripts)	none (0 .v/.sv/.vhd files; KiCad schematic/PCB + 6 .lpf constraint files under doc/constraints/)	CERN-OHL-S-2.0 (LICENSE.md; README SPDX headers)	? → 2025-08-06, ?	none (successor to ULX3S/ULX2S per README lineage)
kost__fujprog	fujprog: host CLI JTAG/UART programmer for ULX2S/ULX3S boards (bitstream upload to SRAM/flash, terminal mode, f32c binary loader)	n/a (host tool) - programs Lattice ECP5 ULX3S and XP2 ULX2S boards over JTAG/FTDI (README.md); no FPGA build itself	n/a (host tool); built with CMake (CMakeLists.txt), links libftdi/FTD2XX	none (C: fujprog.c, getopt.c; ~2 source files)	BSD-2-Clause (LICENSE)	? → 2020-11-12, ?	based on ujprog by Marko Zec, f32c project (README.md:261)
litex-hub__litex-boards	LiteX board-support collection: Python platform + target definitions (pinout, PHYs, SoC glue) for LiteX-built SoCs across many FPGA vendors	ECP5 (35 platforms incl. radiona_ulx3s [LFE5U-12F/25F/45F/85F-6BG381C, rev 2.0 default 45F], radiona_ulx4m_ld_v2 [LFE5UM5G-85F-8BG381C SERDES, rev 0.3], radiona_ulx4m_ls_v2 [LFE5U-85F-8BG381C, rev 0.1], lambdaconcept_ecpix5, gsd_butterstick, colorlight_, machdyne_, trellisboard) + iCE40 (14 platforms: icebreaker, fomu, tinyfpga_bx, alchitry_cu…) + (NOT ECP5) dozens of other families in the same repo (Xilinx Artix/Kintex/Zynq, Intel/Altera, Efinix, GateMate) — mixed multi-vendor BSP collection, not a single-FPGA project	mixed/open by target: ECP5 boards via LiteX->yosys+nextpnr-ecp5+ecppack (trellis); iCE40 via yosys+nextpnr-ice40+icepack; other families use vendor flows (Vivado, Quartus, Efinity) — all driven through the LiteX Python builder, not raw Makefiles	Python (526 .py files: 257 litex_boards/platforms + 247 litex_boards/targets + glue); HDL is generated by Migen/LiteX at build time, no static .v/.vhd sources in this repo	BSD-2-Clause (LICENSE)	? → 2026-09-28, ?	none
mit-plv__koika	Koika: Coq-verified rule-based HDL / compiler (BlueSpec-inspired); examples/rv ships a RISC-V core with a ULX3S top	unknown (no –XXk/DEVICE flag found in examples/rv/etc Makefiles for the ULX3S target)	open (implied); Koika compiles to Verilog, then yosys+nextpnr-ecp5 for ULX3S; formal semantics in Coq	Koika DSL (.lv, compiles to Verilog), Verilog (125, generated+support), OCaml (16, compiler), C/C++ (cuttlesim/verilator)	LGPL-2.1	? → 2025-12-10, ?	none
nicocavallu__fpga-lora-receiver	LoRa-Dechirper: project-status README/index only, no RTL here; links to sibling repos (rf-dds-lo, rf-sdr-frontend, rf-fft-engine) for the DSP blocks	ECP5 85F claimed only (README: ‘Radiona ULX3S (Lattice ECP5 LFE5U-85F)’), no build files of any kind present	unknown (README lists intended tools – iverilog, yosys, nextpnr-ecp5, fujprog – but no build files exist in this repo)	none (no source files at all)	unknown (LICENSE file present but not read in detail; repo has no code to which it would apply)	? → 2026-08-18, ?	none
noxharmonium__sirc	SIRC "Super Imaginary Retro Console": Rust VM/simulator + assembler/linker toolchain for a from-scratch retro CPU/PPU; no HDL yet	none - no gateware exists; claimed future target is ECP5 (ULX3S) per README, unverified	none (pure Rust simulator; no synthesis toolchain used)	none (Rust: 118 files across sirc-vm/*)	GPL-3.0 (LICENSE)	? → 2026-09-18, ?	none
pepijndevos__rust-litex-example	pepijndevos/rust-litex-example: Rust firmware demonstrating litex-hal (SSD1306 OLED) on a LiteX SoC running on ULX3S	unknown (targets a ULX3S LiteX build, size unspecified in this repo)	n/a	Rust (2 files), no HDL	Apache-2.0	? → 2022-04-27, ?	none
rhobbie__library704	Library704: C# netlist-to-Verilog compiler + cycle/logic-exact IBM 704 CPU simulation (from bitsavers schematics), Icarus-only, not a synthesizable FPGA design	none (NOT ECP5) - no FPGA target at all; README: “The generated verilog file runs only in Icarus Verilog” and “The simulation is very slow” - simulation-only, not meant for synthesis	none (no FPGA toolchain); Icarus Verilog for simulation, driven by a C# (.NET 10 SDK-style project) netlist-to-Verilog converter	C# (1 file, Program.cs), Verilog (2 generated testbenches: Testbench/system_tb_sort.v, Testbench/system_tb_LOAD_CR.v; the CPU itself, I704.v, is generated at run time from 337 custom-format .txt schematic files and is not stored in git)	MIT (LICENSE, repo root, Copyright (c) 2023 rhobbie)	? → 2026-09-06, ?	none
trabucayre__openfpgaloader	openFPGALoader universal programmer	12F/25F/45F/85F	n/a	C++	Apache-2.0	2019-09-26 → 2026-09-23, 2095	none
ulx3s__tt-support-tools	tt-support-tools (ULX3S/gojimmypi fork, branch experimental): Tiny Tapeout shuttle tooling (config/precheck/docs generation) extended with ULX3S and ULX4M FPGA board support	ECP5 (ULX3S, all revisions: v1.7 via ulx3s_v17patch.lpf, v2.0-3.07 via ulx3s_v20.lpf, v3.14 via ulx3s_v314.lpf, v3.16-3.18 via ulx3s_v316.lpf; also ULX4M-LD/ULX4M-LS ECP5 boards via fpga/ulx4m/*.lpf); fpga/tt_fpga_top.pcf (‘TT ASIC SIMULATOR’) and fpga/tt_fpga_fabricfox{,v2}.pcf target unidentified other boards	open (implied: the fpga GH Action synthesizes/loads the TT project top wrapped by tt_fpga_top_ulx3s.v onto ULX3S via yosys/nextpnr-ecp5, per fpga/ulx3s/README.md); this repo itself only ships the constraint files and wrapper, no build is run here	Python (33, config/precheck/docs tooling), Verilog (8 .v: fpga tops + logo), Typst (datasheet templates)	Apache-2.0 (LICENSE)	? → 2026-09-03, ?	TinyTapeout/tt-support-tools
ulx3s__ulx3s-saxonsoc	Docker build of SaxonSoc Linux for ULX3S (older)	12F/25F/45F/85F	open (docker alpin3 + sbt)	none (shell)	none found	2020-01-12 → 2020-02-23, 19	older copy of dok3r__ulx3s-saxonsoc
vmware-archive__cascade	Cascade: VMware’s live/interactive Verilog interpreter with hardware backends (archived); ULX3S backend maps compute onto FPGA fabric via Yosys/NextPNR/ujprog	ECP5 (ULX3S, README.md:37,410-419, share/cascade/ulx3s/ulx3s_v20.lpf); also Intel Cyclone V (NOT ECP5) - Terasic DE10 Nano backend via Quartus (share/cascade/de10/*.qsf); the sw backend is not a board	open (yosys+nextpnr+ujprog for ULX3S, README.md:412); Quartus (proprietary) for the DE10 Nano backend	Verilog (323, incl. DE10/ULX3S backend .v + stdlib), C/C++ (288, Cascade core interpreter)	BSD-2-Clause (LICENSE.txt)	? → 2021-07-01, ?	none
zipcpu__dblclockfft	dblclockfft: ZipCPU’s portable C++ generator for a configurable pipelined radix-2 FFT/IFFT core; rtl/ ships a 512-pt demo	vendor-neutral (NOT ECP5-specific): generic pipelined-FFT generator/demo, no vendor primitives in rtl/ or sw/; downstream cores in this collection build it for ECP5 85F (mb-sat__ulx3s-longwave-sdr, 512-pt) and ECP5 45F (C-Elegans__single_sdr, 256-pt)	none in this repo (generator-only, portable C++/Verilog); downstream users run yosys+nextpnr-ecp5 on the generated Verilog (see mb-sat__ulx3s-longwave-sdr, C-Elegans__single_sdr)	Verilog (15, rtl/ demo core), C++ (18 .cpp + 9 .h/.hxx, sw/ generator + bench/cpp/ testbenches)	none found (no LICENSE file); per-file headers: GPL-3.0 (sw/ generator, top Makefile), LGPL-3.0 (rtl/ demo Verilog, e.g. rtl/fftmain.v)	? → 2024-04-18, ?	none

Example collections and education

Repo	What	FPGA	Toolchain	HDL	License	Active (first → last, commits)	Fork / preferred copy
acairncross__clash-ulx3s-examples	Collection of Clash (Haskell-to-HDL) example designs for the ULX3S (stack machine, counter, RAM, DVI, snake game)	85F (Makefile nextpnr-ecp5 –85k)	open; yosys+nextpnr-ecp5+ecppack (Makefile), Clash compiles Haskell to Verilog first	Haskell/Clash (16 .hs, generates Verilog per target)	MIT (LICENSE, unmarked MIT-style text, Aiken Cairncross 2021)	? → 2023-04-26, ?	none
ahamidi87__simpleblinky	Minimal LED-blink example for ULX3S (yosys/nextpnr/verilator tutorial project)	85F (“Default size in Makefile is 85F”; nextpnr-ecp5 –85k)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (1 file, blinky.v)	none found	? → 2024-10-30, ?	none
andrewcapon__spinaltemplatesbtulx3s	SpinalHDL + SBT + VS Code template project for ULX3S	85F (nextpnr-ecp5 –85k)	open (yosys+nextpnr-ecp5+ecppack; SpinalHDL/SBT generates hardware.v)	Scala/SpinalHDL (3 .scala), Verilog (1 generated, hardware.v)	none found	? → 2020-12-22, ?	none
angelojacobo__ulx3s_fpga_camera_streaming	OV7670 camera streaming to VGA on ULX3S, built from Icestudio visual blocks	85F (PART_NEXTPNR ?= –85k)	open; Icestudio -> yosys+nextpnr-ecp5+ecppack via Makefile	Icestudio .ice (15, block diagrams generating Verilog), Verilog (13, generated+glue)	MIT	? → 2021-11-17, ?	none
angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670	Sobel edge detection on an OV7670 camera feed on ULX3S, built from Icestudio visual blocks	85F (PART_NEXTPNR ?= –85k)	open; Icestudio -> yosys+nextpnr-ecp5+ecppack	Icestudio .ice (24), Verilog (15)	MIT	? → 2021-11-17, ?	companion project to angelojacobo/ulx3s_fpga_camera_streaming (same author/pattern); note GitHub survey lists MSRRaju07/IOP with an identical ULX3S_SOBEL.ice, possibly a copy
antoinevg__cynthion-tutorials	cynthion-tutorials: Amaranth tutorials for Cynthion/ECPIX-5 (I2S, RGMII, VexRiscv SoC+Wishbone, UAC, WS2812) with step-by-step example files	12F (LFE5U-12F, BG256, Cynthion) - src/gateware/platform/cynthion.py (WIP, has a live NameError bug: I2SResource references undefined clk_dir instead of its own clkdir); also ECPIX-5 45F/85F via src/gateware/platform/ecpix5.py + ecpix5_luna.py (Amaranth platform, ULPI via luna)	open (Amaranth build backend, apollo / openFPGALoader per survey); examples/soc firmware built with Rust/cargo	Python/Amaranth (54 .py), Verilog (5 .v: bundled VexRiscv variants), Scala (5 .scala: VexRiscv generators), Rust (88 .rs: examples/soc firmware+HAL+PAC)	BSD-3-Clause (LICENSE)	? → 2025-01-13, ?	none
asinghani__advent-of-hardcaml-2024	Advent of Hardcaml 2024: Advent-of-Code solutions implemented as synthesizable Hardcaml (OCaml HDL) FPGA designs on the ULX3S ECP5-85K	ECP5 85F/85K (README: ‘ULX3S FPGA platform with the ECP5-85K’; fpga/src/constraints.lpf) - ULX3S-only, no other board found in this repo despite the group-C listing	open (implied: Hardcaml -> generated Verilog -> yosys+nextpnr-ecp5, consistent with the 2025 sibling repo; not spelled out in this README)	OCaml .ml/.mli (~58 files); no raw Verilog/SystemVerilog/VHDL found	MIT (LICENSE)	? → 2025-02-25, ?	none
asinghani__advent-of-hardcaml-2025	Advent of Hardcaml 2025: Advent-of-Code 2025 solutions as synthesizable Hardcaml designs, primarily targeting the ULX3S ECP5-85F, with a Zynq path also present	ECP5 85F (README: ‘primarily targeting the ULX3S FPGA board, with the Lattice ECP5-85F’; infra/src/constraints.lpf); also Xilinx Zynq (NOT ECP5) - infra/src/zynq_top.ml (no constraints file for it found in this clone)	open (yosys+nextpnr-ecp5 implied by ‘compatibility with the open-source yosys+nextpnr toolchain’, README); Hardcaml -> generated Verilog	OCaml .ml/.mli (~67 files); no raw Verilog/SystemVerilog found	none found (no LICENSE file in this clone)	? → 2026-01-01, ?	none
asinghani__ulx3s-vga-example	Minimal VGA-over-PMOD example for ULX3S (course example project)	12F (nextpnr-ecp5 –12k)	open (yosys+nextpnr-ecp5+ecppack via build.sh)	SystemVerilog (1 file)	MIT (LICENSE.txt)	? → 2024-03-25, ?	none
brunolevy__learn-fpga	Learn FPGA: yosys/nextpnr tutorials, FemtoRV RISC-V core, LiteX SoC, targeting ULX3S HDMI/SDRAM	85F (nextpnr –85k throughout Basic and FemtoRV ULX3S flows)	open; yosys synth_ecp5 + nextpnr-ecp5 + ecppack (+ LiteX path for SoC variant)	Verilog (137 .v, mostly FemtoRV RTL), C (208, firmware/tutorials), Python (LiteX)	BSD-3-Clause (root LICENSE); FemtoRV/LICENSE.md separate	? → 2025-11-18, ?	none
cgarryza__advent-of-camel-2025	Advent of Hardcaml 2025: Advent-of-Code puzzle solutions (12 days) implemented as cycle-accurate FPGA designs in OCaml/Hardcaml with UART I/O, targeting ULX3S	ECP5 85F (fpga/src/build.ml:100 nextpnr-ecp5 –85k)	open (Hardcaml generates Verilog; fpga/src/build.ml shells out to yosys synth_ecp5 + nextpnr-ecp5 + ecppack)	OCaml/Hardcaml (98 .ml/.mli files, generates Verilog at build time)	MIT (LICENSE.md)	? → 2026-01-19, ?	none
cheyao__icepi-zero	Icepi Zero: Raspberry-Pi-Zero-form-factor ECP5-25F board explicitly inspired by ULX3S; gateware/ holds example cores (blinky, UART, SPI, PS/2, DVI, SDRAM memtest, USB, flash) plus emulator ports (Oberon, Apple I, Acorn Atom)	25F (LFE5U-25F, –25k –package CABGA256, FPGA_SIZE variable in Makefile)	open (yosys synth_ecp5 + nextpnr-ecp5 + ecppack –compress); openFPGALoader -b icepi-zero for program/flash; gateware/DIAMOND.md documents an alternate Diamond flow	Verilog (37 .v), SystemVerilog (40 .sv), VHDL (9 .vhd, in third-party/)	zlib (gateware/LICENSE, “software provided as-is” text, covers gateware); Solderpad Hardware License v2.1 (top-level LICENSE, covers hardware/PCB)	? → 2026-09-18, ?	none (board design credits emard/ulx3s as inspiration, not a code fork)
chipflow__example-socs	ChipFlow example-socs: Amaranth-based example SoC buildable via the ChipFlow toolchain, with a real ULX3S board target using amaranth_boards’ ULX3S_85F_Platform	ECP5 85F (ULX3S; my_design/steps/board.py:3 from amaranth_boards.ulx3s import ULX3S_85F_Platform) - ULX3S is the only board target in this repo; pin constraints live in the external amaranth_boards Python package, not present in this clone	open (Amaranth -> yosys+nextpnr-ecp5+ecppack via the amaranth_boards platform; loaded with openFPGALoader -b ulx3s, Makefile:23)	Python (11, Amaranth HDL design + ChipFlow steps)	BSD-2-Clause (LICENSE.md)	? → 2024-07-26, ?	none
daveshah1__up5k-demos	UPduino: UP5K demos - a buildable port of the MiST NES core to iCE40 UltraPlus (VGA+sigma-delta audio), plus a source-only MiST Gameboy Color core port with no working ice40 build	iCE40 UP5K (NOT ECP5) - nes/Makefile uses arachne-pnr -d 5k	open (yosys+arachne-pnr+icepack) for nes/; gameboy/ has no ice40 build path (stale Quartus II project only)	Verilog (37 .v), VHDL (13 .vhd, gameboy/gbc_snd.vhd)	none found (nes/nes.v header says “GPL Licensed. See COPYING for the full license” but no COPYING/LICENSE file in repo)	? → 2017-11-23, ?	MiST NES core / MiST Gameboy core (source ports credited in READMEs, not GitHub forks)
dicethrow__amtest	amtest: Amaranth-HDL learning exercises (SPI, SDRAM+FIFO, on-FPGA logic analyser, formal-verified timers) on ULX3S with ESP32 wifi GUI bridge	ECP5 85F (generated top.lpf: nextpnr-ecp5 –85k –package CABGA381 –speed 6, e.g. tests2_feb2022/test1_amlib_timers_build/build_top.sh); LPF pin names (esp32_spi_0) confirm real ULX3S board	open (Amaranth HDL -> yosys+nextpnr-ecp5+ecppack+openFPGALoader, auto-generated build_top.sh per test)	Python/Amaranth (64 .py)	none found	? → 2022-03-11, ?	none
diegob94__ulx3s_blink	ulx3s_blink: minimal LED-blink example project for ULX3S	85F (nextpnr-ecp5 –85k in Makefile)	open; yosys (blinky.ys script) + nextpnr-ecp5 –85k + ecppack	Verilog (1 .v)	Apache-2.0	? → 2022-09-28, ?	none
dman2021__blink	dman2021/blink: clock-divider LED blink test (‘Test the ulx3s functions’)	85F (Makefile DEVICE = LFE5U-85F, nextpnr –85k)	open; yosys synth_ecp5 + nextpnr-ecp5 –85k + ecppack; make prog uses openFPGALoader -b ulx3s	Verilog (1 .v)	none found (no LICENSE/COPYING file)	? → 2025-07-31, ?	none
dman2021__fpga_count	dman2021/fpga_count: simple binary counter on LEDs for ULX3S	85F (README: nextpnr-ecp5 –85k –package CABGA381)	open; yosys synth_ecp5 + nextpnr-ecp5 –85k + ecppack; openFPGALoader -b ulx3s to flash	Verilog (1 .v)	none found (no LICENSE/COPYING file)	? → 2025-07-16, ?	none
dman2021__uart_echo	dman2021/uart_echo: UART loopback/echo example (separate tx/rx modules) for ULX3S	85F (Makefile/README: nextpnr-ecp5 –85k –package CABGA381)	open; yosys synth_ecp5 + nextpnr-ecp5 –85k + ecppack; openFPGALoader -b ulx3s	Verilog (3 .v)	none found (no LICENSE/COPYING file)	? → 2025-07-17, ?	none
doctorwkt__ulx3s-blinky	ULX3S-Blinky (Warren Toomey): blinky, UART echo, HDMI test pattern with Verilator sim	45F	open (+Verilator)	Verilog	GPL-3.0	2018-12-01 → 2026-01-17, 21	none (upstream)
dpks2003__my_ulx3s_repo	Personal ULX3S-12F project collection; currently just a BCD-to-7-segment decoder	12F (README: ‘ulx3s-12f FPGA board’)	open; detail=implied yosys+nextpnr-ecp5+ecppack via standard ulx3s_v20.lpf flow (no Makefile/script committed)	Verilog 1 file	none found	? → 2024-01-15, ?	none
dschaefer__fpga-template	fpga-template: CMake/Ninja-based FPGA project template (blinky) with verilator+googletest unit testing, open ECP5 flow	85F (cmake/hdl.cmake: nextpnr-ecp5 –85k –timing-allow-fail)	open; yosys synth_ecp5 + nextpnr-ecp5 –85k + ecppack, driven by CMake/Ninja (build.sh)	SystemVerilog (3 .sv), C++ (2 .cpp, verilator/gtest testbench)	none found (no LICENSE/COPYING file)	? → 2022-11-05, ?	none
dschaefer__ulx3s-ghdl-adder	ulx3s-ghdl-adder: VHDL adder example built via CMake+GHDL-yosys plugin, with ghdl testbench	85F (CMakeLists.txt: FPGA_SIZE 85, FPGA_PACKAGE CABGA381)	open; yosys ghdl plugin (VHDL synthesis) + synth_ecp5 + nextpnr-ecp5 –85k + ecppack, via cmake/ghdl.cmake	VHDL (3 .vhdl)	none found (no LICENSE/COPYING file)	? → 2021-09-19, ?	none
dylansebastianheredia__e155_tuner_project	E155 Tuner Project: 512-pt 16-bit FFT (UP5K/Radiant) + STM32 pitch detection, I2S mic in, SPI to MCU (HMC course project)	iCE40 UP5K (NOT ECP5) - SG48 (Upduino v3.1, per README only; no .pcf/.lpf/Radiant project file in this clone to verify)	Lattice Radiant (README states “Lattice Radiant on the Upduino v3.1”); no Radiant project file, Makefile, or open-flow script in this clone to confirm	SystemVerilog (34, fpga/fft_src_v2 + fpga/src + fpga/sim), C (16, mcu/ STM32L432KC firmware)	none found	? → 2025-12-08, ?	none
emard__ulx3s-misc	ULX3S misc/advanced examples: EMARD’s building-block library	12F mostly (also 25F, 85F, um-85k)	both (63 trellis / 60 diamond makefiles; default trellis 42 vs diamond 5)	Verilog ≈ VHDL (156 .v / 102 .vhd), nmigen (dvi), MicroPython	mixed, no LICENSE file: EMARD files BSD; dvi vga2dvid/tmds_encoder MIT (Mike Field); usb/usbhost + usb/usbcdc GPL; sdram variants mixed (mistery GPL-3.0, 16bit LGPL-2.1, pnru public domain)	2019-03-14 → 2026-02-07, 1284	none (upstream of many cores)
embeddeddojo__ulx3s_examples	ULX3S basic examples: button+LED, switch-to-binary decoder, PLL-driven counter (with per-example Makefiles and testbenches)	85F (all 3 Makefiles: nextpnr-ecp5 –85k –package CABGA381)	open; detail=yosys+nextpnr-ecp5+ecppack, PLL generated via ecpppll (Project Trellis tool)	Verilog 8 files	Apache-2.0	? → 2022-01-18, ?	none
fdarling__orangecrab-usb-cdc-demo	OrangeCrab: minimal USB CDC (virtual COM port) echo demo built on the tinyfpga_bx_usbserial core	25F (OrangeCrab r0.2, CSFBGA285 package, per Makefile –25k)	open (yosys+nextpnr-ecp5+ecppack+dfu-util, per Makefile)	Verilog (3 .v own) + submodule tinyfpga_bx_usbserial: Verilog (19 .v)	Apache-2.0 (LICENSE, root); submodule tinyfpga_bx_usbserial: Apache-2.0 (LICENSE) - same license, no conflict	? → 2022-10-02, ?	davidthings/tinyfpga_bx_usbserial (ported/wrapped for OrangeCrab via submodule + custom top.v/reset_timer.v)
flyingoverclouds__flocs-ulx3s-samples	Six small ULX3S Verilog samples (blinky, pushbutton counter, debounced pushbutton counter, slowclock counter, LED PWM, LED glow) with Windows .cmd build scripts	85F by default (BOARDVARIANT=85k in each .cmd, comment notes 12k/25k/45k also selectable for smaller boards)	open; detail=yosys+nextpnr-ecp5+ecppack, driven via Windows batch (.cmd) scripts rather than Make	Verilog 11 files	MIT	? → 2020-12-31, ?	fork/derivation; each README says ‘based on the ulx3s quickstart’ template (upstream ulx3s quickstart project, not a cloned slug here)
fulig__tinyfpga_fft	TinyFPGA_FFT: bachelor-thesis 8-pt FFT, TinyFPGA BX - full-unrolled 8FFT/ plus a single-butterfly-stage FFT_stage/ variant, SPI to Arduino+TFT	iCE40 LP8K (NOT ECP5) - TinyFPGA BX (apio.ini: board = TinyFPGA-BX, in both 8FFT/apio.ini and FFT_stage/apio.ini)	apio (wraps yosys+nextpnr-ice40+icepack; apio build/apio upload per README.md)	Verilog (36 .v across 8FFT/ and FFT_stage/)	none found (no LICENSE/COPYING at any depth)	? → 2022-08-29, ?	none
fusesoc__blinky	FuseSoC example LED-blinker core targeting many dev boards, incl. ULX3S (both 45F and 85F targets)	45F and 85F (two FuseSoC targets: –45k / –85k)	open; yosys+nextpnr-ecp5+ecppack via FuseSoC trellis backend	Verilog (35 .v, mostly per-board tops), Tcl (39, vendor/fusesoc scripts)	MIT	? → 2026-02-28, ?	none
gergoerdi__advent-of-clash-2025	Advent of Clash 2025: Advent-of-Code puzzle solutions (days 3 and 7) implemented as Clash (Haskell HDL) FPGA circuits with serial I/O, targeting ULX3S and Nexys A7	ECP5 45F/85F (Shakefile.hs: ECP5.ecp5 "45k"/"85k"); also Xilinx Artix-7 (NOT ECP5) nexys-a7-50t via Vivado or F4PGA (Shakefile.hs:19-20)	open for ULX3S (clash-shake’s Clash.Shake.ECP5 wraps yosys+nextpnr-ecp5+ecppack, external Hackage package, not vendored); Xilinx target uses Vivado or F4PGA	Clash/Haskell (16 files), generated Verilog (2 files, Top.v per target)	GPL-3.0 (LICENSE)	? → 2026-01-13, ?	none
gojimmypi__nextpnr-issue235	nextpnr-issue235: minimal ULX3S blinky demonstrating a nextpnr LPF line-ending (LF vs CRLF) parsing bug (upstream issue #235)	25F (nextpnr-ecp5 –25k in Makefile)	open; yosys (blinky.ys) + nextpnr-ecp5 –25k + ecppack –idcode 0x21111043; demo.sh uses dos2unix/unix2dos to toggle LPF line endings	Verilog (1 .v), C++ (1 .cpp testbench)	GPL-3.0	? → 2019-02-25, ?	derived from DoctorWkt/ULX3S-Blinky (not cloned), with a modified ulx3s_v20.lpf
gojimmypi__ulx3s-examples	gojimmypi/ulx3s-examples: getting-started tutorial collection for ULX3S (blinky, JTAG passthru, ESP32 VisualMicro, MicroPython)	45F default in blinky/OpenSource (nextpnr –45k); Makefile.12F variant also present; board rev v2.0	both (OpenSource dirs = yosys+nextpnr-ecp5+ecppack; Diamond dirs = Lattice Diamond)	Verilog (4 core examples) + ESP32 C/.ino sketches + MicroPython + doc assets	GPL-3.0 (blinky/OpenSource/LICENSE only; no repo-wide license file)	? → 2019-06-16, ?	none
goran-mahovlic__prjtrellis-led64x64	HUB75 64x64 LED panel, sprite animation	12F	both (vhd2vl for trellis)	Verilog, VHDL	none found	2019-01-05 → 2019-01-13, 51	variant of ulx3s-misc led64x64 (more complete image demo)
greatscottgadgets__cynthion-uac	cynthion-uac: official USB Audio Class 2.0 example gateware for Cynthion (NCO synth, DSP, DAC, VU meter, USB feedback clock recovery)	12F (LFE5U-12F, BG256, Cynthion) - depends on cynthion~=0.2.2 package for the platform (pyproject.toml); uac/top.py requests platform.request(‘target_phy’) (Cynthion ULPI target PHY); no board files bundled in this repo	open (Amaranth build backend via python -m uac.top, inherits the Cynthion platform’s yosys/nextpnr-ecp5/ecppack + apollo programmer)	Python/Amaranth (10 .py in uac/)	BSD-3-Clause (LICENSE.txt); uac/dac.py under a separate ISC-style permission notice (adapted from the Glasgow Interface Explorer audio applet, no SPDX id)	? → 2025-07-15, ?	none
guztech__ulx3s-nmigen-examples	GuzTech/ulx3s-nmigen-examples: nMigen/Amaranth example designs (DVI/VGA, OLED+VGA) for ULX3S	12F/25F/45F/85F selectable via CLI arg to top_*.py	open (yosys+nextpnr-ecp5 via nMigen/Amaranth build backend)	Python/Amaranth (11 files)	none found	? → 2020-11-26, ?	none; lawrie/ulx3s-nmigen-examples (survey sec D) is a fork pushed 563d later, may be a maintained copy
hassan2203__system-on-chip-soc-design-and-verification	RV32I single-cycle CPU + Wishbone bus SoC teaching project, built for Colorlight i5 (primary target per README) and ULX3S onboard variant	45F (build_wishbone_ulx3s.sh: nextpnr-ecp5 –45k –package CABGA381)	open; yosys synth_ecp5 + nextpnr-ecp5 –45k + ecppack, via build_wishbone_ulx3s.sh; openFPGALoader -b ulx3s to program	Verilog (23 .v: ALU, control_unit, wb_interconnect, wb_ram/rom/led, top.v)	none found (no LICENSE/COPYING file)	? → 2026-06-19, ?	none
heichips__heichips25-template	HeiChips 2025 Hackathon submission template: ASIC macro template (eFPGA-integrated tapeout) with six FPGA emulation targets including ULX3S	ECP5 (ULX3S, fpga/ulx3s/ulx3s_v20.lpf); also NOT ECP5: Xilinx Artix-7 (basys3, fpga/basys3/Basys-3-Master.xdc), Xilinx Spartan-7 (boolean, fpga/boolean/boolean.xdc, README.md:81), iCE40 HX8K (fpga/ice40hx8k/ice40hx8k-evb.pcf), iCE40 UP5K (fpga/icebreaker/icebreaker.pcf), Gowin (fpga/nano9k/nano9k.cst)	open for ULX3S/icebreaker/ice40hx8k (nextpnr icestorm+trellis+openFPGALoader, README ‘tools included’); nextpnr-xilinx via openXC7 for basys3/boolean (README.md:119); Gowin toolchain (implied by .cst) for nano9k; LibreLane for the ASIC macro itself	SystemVerilog (9), Python (1)	Apache-2.0 (LICENSE)	? → 2026-03-01, ?	none
hexagon5un__hackaday_supercon_2019_logic_noise_fpga_workshop	Hackaday Supercon 2019 “Logic Noise” FPGA workshop: cumulative Verilog exercises building audio oscillators and an organ on the badge	45F (LFE5U-45F-6BG381, –45k –package CABGA381, includes/global_makefile) - Hackaday Supercon 2019 badge	open (yosys+nextpnr-ecp5+ecppack, dfu-util flash) - includes/global_makefile	Verilog (22 .v)	none found	? → 2019-11-20, ?	none
icebreaker-fpga__icebreaker-verilog-examples	iCEBreaker: collection of small Verilog examples (blink/counter, 7-seg, DVI/VGA 4/12/24-bit, PDM/PWM LED fade, gamepad audio tone, WS2812, charlieplexing) for iCEBreaker and iCEBreaker-bitsy boards	iCE40 UP5K (NOT ECP5) - SG48 package (icebreaker/icebitsy .pcf + Makefile PACKAGE=sg48)	open (yosys+nextpnr-ice40+icepack, via main.mk)	Verilog (51 .v)	no repo-wide LICENSE; per-example COPYING files are ISC-style (e.g. icebreaker/pdm_fade_gamma/COPYING), sb_rgba_blink/LICENSE is CC0 1.0; most examples have none found	? → 2021-09-25, ?	none
icebreaker-fpga__icebreaker-workshop	iCEBreaker: self-directed educational workshop building a BCD stopwatch/counter driven onto a 7-segment Pmod display, with asciidoc/PDF guide and reference solutions (single and dual-display variants)	iCE40 UP5K (NOT ECP5) - SG48 package (Makefile: nextpnr-ice40 –up5k –package sg48)	open (yosys+nextpnr-ice40+icepack)	Verilog (4 .v: stopwatch/stopwatch.v + solution, stopwatch-dual/stopwatch.v + solution)	none found (no LICENSE/COPYING file anywhere in repo)	? → 2021-10-27, ?	none
im-tomu__fomu-workshop	Fomu: a multi-language FPGA workshop (Verilog, VHDL, mixed HDL, Migen, a LiteX SoC with ValentyUSB, plus MicroPython/Rust/Zig blink examples) teaching FPGA basics on the iCE40 UP5K Fomu board	iCE40 UP5K (NOT ECP5) - SG48 (evt1/evt2/evt3), UWG30 (hacker, pvt)	open (yosys+nextpnr-ice40+icepack) for HDL blink examples; LiteX -> yosys/nextpnr for litex/workshop.py SoC	Verilog (6 .v), VHDL (4 .vhd), Python (7 .py, Migen/LiteX)	Apache-2.0 (LICENSE)	? → 2024-03-17, ?	none
jadephilipoom__ulx3s-experiments	ulx3s-experiments: small “learning stuff about hardware” RISC-V toy (top.v drives an LED test-double loop) for ULX3S	85F (Makefile: nextpnr-ecp5 –85k)	open; yosys (top.ys script) + nextpnr-ecp5 –85k –lpf ulx3s_v20.lpf + ecppack	Verilog (1 .v), RISC-V asm (1 .s)	none found (no LICENSE/COPYING file)	? → 2026-06-06, ?	none
jamon__jspcpu	Verilog implementation of James Sharman’s 8-bit pipelined educational CPU design, built module-by-module	85F (Makefile nextpnr-ecp5 –85k)	open; yosys+nextpnr-ecp5+ecppack (Makefile); also uses Verilator for simulation and apio-style toolchain paths in per-module flash.sh	Verilog (21 .v), shell (18 .sh, mostly per-module flash/test scripts), C++ (4, Verilator testbenches)	none found	? → 2021-07-16, ?	none
jderobot__fpga-robotics	FPGA-robotics: JdeRobot teaching library for camera/robotics on FPGA; many apio OV7670 camera demos for ULX3S	85F (apio.ini: board = ulx3s-85f)	open; apio wraps yosys+nextpnr-ecp5+ecppack	Verilog (636, many generated/sim+demo variants), VHDL (180), Icestudio .ice (147, block diagrams)	mixed: GPL-3.0-or-later (software, LICENSE.md) + CERN-OHL-S-2.0 (hardware, doc/cern_ohl_s_v2.txt)	? → 2024-07-14, ?	none
jlopezr__mini-gpu	“mini-gpu”: staged educational build-up of a MiniISA CPU and MiniGPU on ULX3S 85F (28+ numbered stages)	85F (apio.ini board=ulx3s-85f across stages)	open (apio wrapping yosys+nextpnr-ecp5+ecppack)	Verilog (391 .v), SystemVerilog (27 .sv), custom MiniISA asm (288 .asm)	none found	? → 2026-09-25, ?	none
johngannon4__riscv-cpu-portfolio	RV32IM 6-stage AXI4-Lite pipelined processor built for a university course (Penn CIS 4710/5710); documentation-only, RTL deliberately withheld	ECP5 (ULX3S board) claimed only, per README "Target: Lattice ECP5 (ULX3S board)"; unverifiable, no gateware in the clone	Yosys + nextpnr open-source flow (claimed in README; no scripts present)	none (repo is Markdown documentation only)	none found	? → 2026-09-24, ?	none
joshajohnson__ecp5-mini-projects	ECP5 Mini: Verilog examples (blink, fade, nightrider, clock, 74595, WTFPGA, USB serial) + a LiteX SoC with HyperRAM + nMigen blink	12F default (DEVICE:=12k, CABGA256); 25F via make DEVICE=25k / –device=25F	open (yosys+nextpnr-ecp5+ecppack, verilog/common.mk; LiteX for soc-hr; ecpprog/DFU to load)	Verilog (40 .v), Migen/LiteX + nMigen (5 .py)	BSD-2-Clause (LICENCE.md, “unless otherwise stated”); verilog/common/usb: Apache-2.0 (LICENSE, tinyfpga_bx_usbserial subset)	? → 2021-08-29, ?	none (based on kbeckmann/pergola_projects; soc-hr credited to Greg Davill)
kbeckmann__pergola_projects	Pergola: Verilog HDMI pass-through experiments (plain, registered, DDR1x/DDR2x) + an nMigen applet collection (DVI in/out, DVI->VGA, TMDS, UART, PLL, gearbox, ChaCha20, matmul, SoC demo, radio TX)	12F board (platform LFE5U-12F, BG256); Verilog flow builds with ECP5_VARIANT?=25k + IDCODE override	open (yosys+nextpnr-ecp5+ecppack for verilog/; nMigen -> yosys/nextpnr for pergola/)	nMigen/Amaranth (43 .py), Verilog (5 .v)	BSD-2-Clause (LICENCE.md, “unless otherwise stated in individual files”)	? → 2021-06-23, ?	none (upstream of joshajohnson__ecp5-mini-projects layout)
kbob__icebreaker-candy	iCEBreaker: eye-candy demos driving a 64x64 HUB75 RGB LED panel (munching squares, circles, tunnels, PWM/PDM gamma-corrected LED drivers)	iCE40 UP5K (NOT ECP5) - package unspecified in main.mk (DEVICE:=up5k per-example Makefile, e.g. first-demo/Makefile)	open (yosys+nextpnr-ice40+icepack; main.mk also supports arachne-pnr via USE_ARACHNEPNR)	Verilog (32 .v across ~25 example dirs), SystemVerilog (1 .sv testbench: gray/top_tb.sv), C (2 table generators), Rust (sim/ Vulkano visualizer, not part of FPGA build)	GPL-3.0 (LICENSE, root; no per-file SPDX headers seen)	? → 2019-06-13, ?	none
kholia__colorlight-5a-75b	Colorlight 5A-75B: notes + example projects (blink, DDS/SSB radio via UART/Docker) for the Colorlight 5A-75B ECP5 board	25F (LFE5U-25F-6CABGA256, –25k –package CABGA256, blink/Makefile; confirmed via openFPGALoader log in README: “Part: LFE5U-25F-6CABGA256”; DP16KD 54/56 in dds_ssb_docker/FPGA_USAGE_REPORT.md matches 25F’s 56 DP16KD blocks)	open (yosys+nextpnr-ecp5+ecppack), native Makefile or Docker (davidsiaw/yosys-docker, blink_docker/build.sh); programmed via openFPGALoader/OpenOCD/UrJTAG (Bus Pirate, CMSIS-DAP, Pico dirtyJtag, STM32 Blue Pill DirtyJTAG)	Verilog (18 .v across 6 example dirs, incl. per-dir copies of nco.v/fifo.v/uart_rx.v/uart_tx.v), Python (5 .py: gen_phase_mem.py, mem_to_wav.py, gen_sine.py, stream_wav_uart.py x2)	none found (no LICENSE/COPYING at any depth; README carries no SPDX id)	? → 2026-02-26, ?	none
kost__ulx3s-ghdl-examples	VHDL versions of odysseus basics/audio via ghdl-yosys-plugin	85F	open (ghdl plugin)	VHDL	none found (passthru BSD)	2019-12-29 → 2020-10-07, 5	none
lawrie__blackicemxbook	BlackIce Mx open-source-FPGA book (Lawrie Griffiths): jekyll chapters + 33 worked Verilog examples (audio, video, sensors, camera, retro “baby” computer, PicoSoC/SpinalHDL chapters text-only)	iCE40 HX8K (NOT ECP5) - TQ144:4k package (nextpnr-ice40 --freq 64 --hx8k --package tq144:4k, examples/blackicemx.mk)	both: open (yosys+nextpnr-ice40+icepack, examples/blackicemx.mk) and open (yosys+arachne-pnr+icepack, examples/arachne.mk); examples/verilator/ adds a verilator+g++ sim target	Verilog (60 .v, all under examples/)	none found (no LICENSE/COPYING at any depth)	? → 2019-11-15, ?	none
lawrie__hdmi_examples	iCE40 open-source HDMI/DVI examples for BlackIce II: hdmi_test/_ibr/_mx (test pattern variants), hdmi_pong and ball_paddle (VGA-timed games over HDMI), hdmi_pmod_mx	iCE40 HX8K (NOT ECP5) - TQ144:4k package (nextpnr-ice40 --freq 70 --hx8k --package tq144:4k, root/hdmi_pong/hdmi_test*/Makefile); hdmi_test_ibr/ also targets iCE40 UP5K (NOT ECP5) - SG48 (--up5k --package sg48, iCEBreaker board)	open (yosys+nextpnr-ice40+icepack); commented-out arachne-pnr fallback line left in each Makefile	Verilog (10 .v)	none found (no LICENSE/COPYING); per-file header cites “Copyright 2016 myStorm … Solderpad Hardware License v0.51” in each Makefile (build-script license only, not the HDL)	? → 2022-05-12, ?	none
lawrie__ulx3s-nmigen-examples	Large collection of nMigen/Amaranth examples for ULX3S: blinky, camera, DVI, SDRAM, PS/2, retro CPUs, OLED	12F/25F/45F/85F (CLI arg, e.g. python top_x.py 85F)	open: yosys+nextpnr-ecp5+prjtrellis+openFPGALoader via nMigen/Amaranth	Python (nMigen/Amaranth), 326 files	none found	? → 2022-05-05, ?	GuzTech/ulx3s-nmigen-examples (survey: fork with substantial own commits)
lawrie__ulx3s_examples	Lawrie Griffiths Verilog examples: HDMI, displays, PS/2, SDRAM, USB host, CPUs (8080, 68000, RISC-V)	25F mostly (85F default in ulx3s.mk)	open (yosys -abc9)	Verilog (194 .v)	none found at repo level; sdram16/sdram.v and sdram8/sdram.v GPL-3.0-or-later (MiST), st7789/oled_video.v BSD, hdmi/menu PicoRV32 ISC	2020-01-02 → 2022-05-05, 25	merges fpga-odysseus + ulx3s-misc usbhost + led64x64
lawrie__ulx3s_vhdl_examples	VHDL ports of the ulx3s_examples Verilog tutorial examples (LED, counter, button, debounce, audio/piano/sound)	85F (Makefile DEVICE?=85k)	open; yosys (ghdl plugin for VHDL)+nextpnr-ecp5+ecppack via ulx3s.mk	VHDL (8 .vhd)	none found	? → 2022-05-07, ?	VHDL translation of lawrie’s ulx3s_examples (Verilog)
lawrie__ulx4m_amaranth_examples	Amaranth HDL examples for the ULX4M board: blinky, DVI, SDRAM16, Conway life, mitecpu, PS/2, OLED, audio	ULX4M 12F/45F/85F (ULX4M_12F_Platform / 45F / 85F classes in ulx4m.py)	open: yosys+nextpnr-ecp5+ecppack via Amaranth (amaranth.vendor.lattice_ecp5)	Python (Amaranth), ~40+ files	none found	? → 2022-05-11, ?	none (sibling to lawrie__ulx3s-nmigen-examples, same author/pattern)
lawrie__ulx4m_examples	Verilog examples for the ULX4M board: blinky, HDMI/DVI, SDRAM, softcore CPUs, GPI2 game demos	ULX4M 85F (DEVICE ?= 85k in ulx4m.mk)	open: yosys+nextpnr-ecp5+ecppack (+dfu-util for DFU bootloader path)	Verilog, ~30+ files	none found	? → 2022-04-22, ?	none (some examples ported from RadionaOrg/fpga-odysseus per README)
lawrie__verilog_examples	Lawrie Griffiths Verilog examples for BlackIce II: ~157 files across ebook (audio/input/output/builtin), fpga (baby computer, PS/2, VGA, motors, WS2812, oscilloscope), fpga4fun ports (pong/HDMI), fpgafun, other	iCE40 HX8K (NOT ECP5) - TQ144:4k package (arachne-pnr -d 8k -P tq144:4k, fpga/blackice.mk; fpga4fun/main.mk also supports –up5k/–hx1k/–lp via DEVICE var, not exercised here)	both: open (yosys+arachne-pnr+icepack, blackice.mk) and open (yosys+nextpnr-ice40+icepack, fpga4fun/main.mk, USE_ARACHNEPNR switches to arachne-pnr)	Verilog (157 .v)	none found at repo root; ebook/output/hex7seg/LICENSE is a vendored MIT file (Copyright Simon Monk) for that one example only	? → 2019-09-08, ?	none (fpga4fun/ and fpgafun/ dirs port well-known fpga4fun.com Verilog demos; ebook/output/hex7seg/ vendors Simon Monk’s “Programming FPGAs” book code)
lcausevic__ulx3s_fpga_logic_structures	Coursework collection of small ULX3S/ECP5 logic exercises (ADC, counters, mux, PID, PWM, UART, combinational logic) built with Lattice Diamond	85F (zip named ULX3S-85F; per-project .ldf device)	diamond: Lattice Diamond project dirs per exercise (.ldf/impl1), no Trellis/open flow seen	VHDL (per exercise), plus prebuilt .bit files committed	none found	? → 2026-09-22, ?	none
mangelajo__orangecrab-usb	OrangeCrab: two USB device examples (UVC camera, I2S mic audio) built on WangXuan95’s FPGA-USB-Device IP core	25F or 85F (OrangeCrab r0.1/r0.2/r0.2.1 via VERSION/DENSITY vars, default 85F)	open (yosys+nextpnr-ecp5+ecppack, run locally or via podman/docker container from container.mk)	Verilog (4 .v own: clkdiv.v, i2s.v, fpga_top_usb_camera.v, fpga_top_usb_audio.v), Python (2 cocotb test files) + submodule FPGA-USB-Device: Verilog (19 .v)	none found (no LICENSE/COPYING file in own repo; README states no license); submodule ip/FPGA-USB-Device: GPL-3.0 (LICENSE) - licensing concern: the wrapping demo code is unlicensed while the USB core it bundles is GPLv3	? → 2024-02-25, ?	none (wraps WangXuan95/FPGA-USB-Device via git submodule, not a fork itself)
marinsiric__ulx3s	ULX3S FPGA coursework: Diamond JTAG passthru copy + custom serial_tx lab (FER Zagreb)	12F/25F/45F/85F (passthru has all four size project dirs)	diamond	VHDL, 3 files (serial_tx.vhd etc.) + Diamond project artifacts	none found (serial_tx.vhd itself carries a Marko Zec BSD-2-like header, but no repo LICENSE)	? → 2020-01-23, ?	none (Diamond/passthru looks copied from a stock ULX3S Diamond example)
mkvenkit__learn_fpga	Personal collection of FPGA learning exercises (ULX3S, iCE40HX1k/UP5k, Migen)	85F (nextpnr-ecp5 –85k –package CABGA381 in each Makefile)	open: yosys+nextpnr-ecp5+ecppack per-project Makefiles	Verilog (37 .v), Python (4, Migen)	MIT	? → 2026-07-19, ?	none (own tutorials)
mkvenkit__ulx3s_examples	mkvenkit/ulx3s_examples: repo migrated, README-only redirect to mkvenkit/learn_fpga	unknown	n/a	none (README + .gitignore only)	none found	? → 2022-04-25, ?	none (superseded by mkvenkit/learn_fpga)
mmicko__fpga101-workshop	FPGA 101 workshop (Hackaday Belgrade 2018): 20 progressive Verilog exercises for the FPGA101 badge (LED, audio, LCD video, Pong, grom CPU, i8080 Altair, PicoSoC + MicroPython) plus a Galaksija project	iCE40 UP5K (NOT ECP5) - SG48 (README apio log: arachne-pnr -d 5k -P sg48; apio.ini board = fpga101); 12 MHz clock (pinout.pcf)	open via apio (yosys + arachne-pnr + icepack, per README test log); IceStudio for 00-IceStudio; riscv64-unknown-elf-gcc for 12-RiscV firmware	Verilog (82 .v), C (160 .c, mostly the MicroPython port), IceStudio .ice (2)	MIT (LICENSE, Copyright 2018 Miodrag Milanović); i8080.v modified BSD (Dmitry Tselikov, Bashkiria-2M header); z_picorv32.v ISC (PicoRV32); MicroPython MIT	? → 2019-03-17, ?	none (original; its ULX3S follow-up by the same author is ulx3s__fpga-odysseus, which shares 10 identical files)
mmicko__ulx3s-examples	Single ULX3S blinky example (apio project) by nextpnr/yosys maintainer mmicko	12F (apio.ini board=ulx3s-12f)	open; detail=apio (yosys+nextpnr-ecp5+ecppack via apio)	Verilog 1 file	none found	? → 2019-02-21, ?	none
mpardalos__clash-blinky	Clash (Haskell-to-Verilog) starter/template project blinking the ULX3S LED, with Cabal/Stack/Shake build scaffolding	unknown (Shakefile references synth stage but no explicit nextpnr device flag seen in Shakefile.hs/mk)	open: Clash compiler generates Verilog, then presumably yosys+nextpnr-ecp5 (Shakefile ‘synth’ target uses lpf, exact nextpnr invocation not inlined)	Haskell (7 .hs, Clash HDL)	none found	? → 2025-04-13, ?	none (generic Clash ‘Simple Starter Project’ template, adapted for ULX3S)
mystorm-org__blackice-ii	BlackIce II: myStorm board repo - Verilog example designs (blink/uart/pll/sram/rotate/…) for the iCE40 HX4K FPGA, plus an STM32L4 bootloader/DFU firmware and board hardware files	iCE40 HX4K (NOT ECP5) - TQ144 (arachne-pnr -d 8k -P tq144:4k, e.g. examples/hello_world/Makefile; icetime -tmd hx8k in examples/sram/Makefile confirms HX4K built on the HX8K die)	open (yosys+arachne-pnr+icepack); dfu-util for STM32 flash; verilator –lint-only target present in examples/sram/Makefile (lint only, not simulation)	Verilog (52 .v: 51 in examples/, 1 in firmware/Src/blackice.v); C (STM32 HAL/USB firmware, non-gateware: 108 .c/.h files under firmware/{Src,icedfu,iceboot,Drivers,Middlewares})	none found at repo root; per-file headers (e.g. every examples/*/Makefile) cite Solderpad Hardware License, Version 0.51 (SHL-0.51)	? → 2020-12-29, ?	none
nesl__ice40_examples	NESL iCE40 HX8K breakout-board example projects: blank, blinky, buttons_bounce/debounce/nopullup, fsm_simple, uart_transmission — beginner IceStorm-toolchain tutorials	iCE40 HX8K (NOT ECP5) - CT256 package intended (FOOTPRINT=ct256 var in each Makefile for the iCE40-HX8K Breakout board; nextpnr-ice40 call itself passes only --hx8k with no –package flag, so footprint is not actually enforced by the build); uart_transmission/ also ships a TQ144 pinmap variant (pinmap_tq144.pcf, alternate board)	open (yosys+nextpnr-ice40+icepack; commented-out arachne-pnr line left in each Makefile)	Verilog (9 .v)	GPL-3.0 (LICENSE file, GNU GPLv3 text)	? → 2023-04-24, ?	none
nullobject__counter-ulx3s	Minimal LED counter example on ULX3S (single top.v incrementing LEDs from a clock divider)	85F (Makefile DEVICE?=85k)	open: yosys+nextpnr-ecp5+ecppack via Makefile, fujprog/ftp to program	Verilog (1 .v)	none found	? → 2025-02-01, ?	none
obijuan__open-fpga-verilog-tutorial	Digital Design for FPGAs (Spanish): ~90 numbered Verilog lessons, combinational logic through UART/ROM/RAM/FSM/tiny-CPU, built with open toolchains	iCE40 HX8K (NOT ECP5) - tutorial/ICE40-HX8K_Breakout_Board/* (arachne-pnr -d 8k, per-lesson Makefile) and tutorial/Alhambra_II/* (nextpnr-ice40 –hx8k –package tq144:4k, e.g. T01-setbit/Makefile); also iCE40 HX1K (tutorial/ICESTICK/*, arachne-pnr -d 1k) and iCE40 LP8K CM81 (tutorial/TinyFpgaBx/Makefile, nextpnr-ice40 –lp8k –package cm81, reuses ICESTICK sources)	open, mixed: arachne-pnr (yosys synth_ice40 -blif + arachne-pnr -d {1k,8k} + icepack) for HX8K_Breakout_Board & ICESTICK; nextpnr-ice40 (yosys synth_ice40 -json + nextpnr-ice40 + icepack) for Alhambra_II & TinyFpgaBx	Verilog: 277 .v, 99 .pcf across ~90+ lesson dirs (ICE40-HX8K_Breakout_Board:5, ICESTICK:31, Alhambra_II:30, TinyFpgaBx:1); comments/docs in Spanish	GPL-2.0 (LICENSE)	? → 2020-04-15, ?	none (original BQ/Obijuan course; some lesson Makefiles credit D. Cuartielles/Arduino Dec 2015)
orangecrab-fpga__orangecrab-examples	OrangeCrab: example projects - RISC-V/VexRiscv firmware, plain Verilog (blink/PWM/USB-ACM), LiteX SoC, and Amaranth blink, for the official OrangeCrab bootloader/DFU flow	25F (OrangeCrab r0.1/r0.2/r0.2.1, CSFBGA285; Makefile DENSITY var also supports 85F)	open (yosys+nextpnr-ecp5+ecppack+dfu-util for verilog; LiteX/migen+yosys/nextpnr for SoC; Amaranth+yosys for amaranth example)	Verilog (10 .v own), Python (8 .py own), C (2 .c own RISC-V firmware) + submodule valentyusb: Python (75 .py, 2 .v) + submodule usbserial: Verilog (19 .v)	MIT (LICENCE.md, root); submodule litex/deps/valentyusb: BSD-3-Clause (LICENSE); submodule verilog/usb_acm_device/blocks/usbserial: Apache-2.0 (LICENSE) - three different licenses in this one repo	? → 2024-05-08, ?	none
osresearch__up5k	UPduino v2: standalone iCE40 UltraPlus5K Verilog demos - blink, RGB pulse, UART serial/echo, SPRAM buffered echo, CORDIC, DAC, OLED SSD1331, HTC-Vive lighthouse sensor decode, USB-serial	iCE40 UP5K (NOT ECP5) - SG48 (default BOARD=upduino & icebreaker); tomu UP5K UWG30; tinyfpga-bx targets iCE40 LP8K CM81 (not UP5K)	open (yosys+nextpnr-ice40+icepack, Makefile.icestorm)	Verilog (18 .v top-level demos + 15 .v in usb/ = 33 total)	none found (no LICENSE/COPYING file; README states none)	? → 2021-05-24, ?	none
p-kraszewski__cs-ulx3s-03	CS-ULX3S-03 resources: toolchain setup notes + Knight Rider Verilog example for ULX3S v3.1.8	85F (FPGA ?= 85k default in .make/ulx3s.mk)	open: yosys+nextpnr-ecp5+ecppack (+verilator sim)	Verilog, 1 file + C++ verilator testbench	GPL-3.0	? → 2023-08-22, ?	none
pcotret__ulx3s-examples	VHDL ULX3S basics examples (button/counter/debounce/init/led-blink/trigger) via GHDL-Yosys plugin	85F (README: ‘the ULX3S, 85F variant’; nextpnr –85k)	open; detail=yosys+ghdl-yosys-plugin+nextpnr-ecp5+ecppack, VHDL via ghdl plugin	VHDL 5 vhdl + 1 vhd	none found	? → 2020-11-13, ?	fork; explicit README credit to kost/ulx3s-ghdl-examples (‘Taken from’)
pfontvilanova__pfforthmachine	PFForth Machine: planned pure-hardware async Forth stack machine for ULX3S (README-only)	unknown	n/a	none present	MIT (from a .license text file, not a real LICENSE)	? → 2026-01-17, ?	none
pmezydlo__beaglewire	BeagleWire: GSoC-2017 open Verilog example/peripheral collection for the iCE40HX4K BeagleBone cape (GPMC host bus)	iCE40 HX4K (NOT ECP5) - TQ144 (examples/Makefile.beaglewire: DEVICE=8k FOOTPRNT=tq144:4k; beaglewire_pinmap.pcf header “ice40hx4k tq144”)	open (yosys+arachne-pnr+icepack, examples/Makefile.beaglewire); SPI load via load_fw/bw-prog.sh from BeagleBone	Verilog (23 .v: 10 components/ + 13 examples/*/top.v), C (9: drivers/ Linux kernel modules + bridge_lib/ + load_fw/, not gateware)	GPL-2.0 (LICENSE, README badge); beaglewire_pinmap.pcf file header states “license: gplv3” (inconsistent with root LICENSE)	? → 2018-10-10, ?	none
q3k__ulx3s-foss-blinky	FOSS-only ULX3S blinky template (yosys/nextpnr/openocd)	85F default (PART_NEXTPNR ?= –85k, overridable via PART_* vars)	open: yosys+nextpnr-ecp5+ecppack, OpenOCD flashing (patched fork required)	Verilog (1 .v)	mixed (blinky.v: ISC from nextpnr; Makefile/LPF/OpenOCD script/README: CC0)	? → 2018-11-11, ?	blinky core comes from nextpnr’s own example
racerxdl__colorlight-picorv32	Colorlight I5 PicoRV32 example: minimal RV32I SoC (picorv32 CPU + simpleuart) booting firmware.hex from block RAM	25F (LFE5UM5G-25F, –25k –package CABGA381 –freq 25, Makefile; openocd/LFE5UM5G-25F.cfg)	open (yosys+nextpnr-ecp5+ecppack, all run via Docker images hdlc/yosys, hdlc/nextpnr:ecp5, hdlc/prjtrellis in Makefile); openocd (ghdl/synth:prog image) for JTAG programming via openocd/ft232.cfg	Verilog (3 .v: top.v, simpleuart.v, vendored picorv32.v), Python (1 .py: firmware/makehex.py), C (firmware/firmware.c) + asm (firmware/start.s)	none found (no LICENSE/COPYING in this repo’s own files; vendored src/picorv32.v carries its own ISC-style header, Copyright (C) 2015 Clifford Wolf)	? → 2021-02-27, ?	none (vendors CPU core src/picorv32.v + src/simpleuart.v from YosysHQ/picorv32, unmodified, ISC header retained)
ranzbak__fpga-workshop	UPDuino v2.0: 14-lesson Verilog workshop curriculum (hello/module/blink/parameters/registers/dimming/tasks/functions/case/IO/sim/DS18B20 1-wire sensor) for iCE40 UP5K beginners.	iCE40 UP5K (NOT ECP5) - SG48	open (yosys+arachne-pnr+icepack+icetime; NOT nextpnr)	Verilog (48 .v)	none found (no LICENSE/COPYING file)	? → 2020-03-10, ?	none
richardegeorge__ulx3s-chase	Simple LED chase/sequencer pattern on ULX3S-85F, derived from DoctorWkt’s ULX3S-Blinky example	85F (README states ULX3S-85F requirement; device not explicit in yosys/nextpnr flags shown but matches sibling repos)	open: yosys(+blinky.ys)+nextpnr-ecp5+ecppack via Makefile	Verilog (1 .v)	GPL-3.0	? → 2021-02-11, ?	derived from DoctorWkt/ULX3S-Blinky (not one of our cloned slugs)
richardegeorge__ulx3s-flipflop	D-type flip-flop driven by two ULX3S buttons (clock+reset), demo based on DoctorWkt’s blinky example	85F (per README/sibling repos; ULX3S-85F board assumed)	open: yosys(+flipflop.ys)+nextpnr-ecp5+ecppack via Makefile	Verilog (1 .v)	none found (no LICENSE file, unlike sibling ulx3s-chase)	? → 2021-02-13, ?	derived from DoctorWkt blinky example (not one of our cloned slugs)
richardegeorge__ulx3s-passthru	Simplest-possible ULX3S example: copies 6 button inputs directly to 6 LEDs	85F (per README/sibling repos; ULX3S-85F board assumed)	open: yosys(+passthru.ys)+nextpnr-ecp5+ecppack via Makefile	Verilog (1 .v)	none found (no LICENSE file)	? → 2021-02-13, ?	derived from DoctorWkt/blinky example (not one of our cloned slugs)
robinsonb5__eightthirtytwodemos	Demo projects (SoC, Dhrystone, VGA, SDRAM test) for the EightThirtyTwo soft CPU, multi-board	85F (Board/ulx3s_85f/board.mk: DEVICE=–85k)	open; yosys+nextpnr-ecp5+ecppack (Board/ulx3s_85f/board.mk, Scripts/yosys.mk); also has sim_ghdl board for GHDL simulation	C (173, EightThirtyTwo asm-C toolchain), VHDL (126), Verilog (48), Tcl (92, mostly Xilinx/Altera flows), Quartus/Vivado project files + submodule EightThirtyTwo: C (57), H (50), VHDL (44), Verilog (1), assembly (16 .s) - CPU core, assembler/linker/emulator, vbcc C backend	GPL-3.0; submodule EightThirtyTwo: GPL-3.0 (COPYING, Alastair M. Robinson) for the CPU/toolchain, plus LGPL (lib832/COPYING.LESSER) for the C runtime library - same author, consistent with main repo	? → 2026-06-15, ?	none
srjilarious__fpga_start	fpga_start: Verilog/C++-sim tutorial series (blinky, state machine, seven-seg) for TinyFPGA-BX and ULX3S, built via CMake+Conan+Verilator+Yosys	ECP5 12F (–12k, cmake/yosys_ecp5.cmake: synth_ecp5 –12k –package CABGA381); also iCE40 (NOT ECP5) via tiny_fpga_bx_pins.pcf (primary target per README)	open (yosys synth_ecp5/synth_ice40 + nextpnr-ecp5/nextpnr-ice40 + ecppack/icepack), driven by custom CMake macros (cmake/yosys_ecp5.cmake, yosys_ice40.cmake)	Verilog (12 files)	none found	? → 2026-02-28, ?	none
stefanhaslhofer__hardwaredesign	Personal learning log/coursework: blinky (Verilog+VHDL), button passthru, and a small RISC-V-ish RAM/CPU exercise plus ESP32 companion sketch, on ULX3S	unknown (no explicit nextpnr device flag found; prebuilt ulx3s.bit / ulx3s_85f_passthru.bit filenames imply 85F)	open: presumably yosys+nextpnr-ecp5+ecppack via deploy.sh/deploy_blinky.sh/deploy_passthru.sh (scripts not fully inspected)	VHDL (3 .vhd), Verilog (1 .v), C (1, LedCounter/main.c), Assembly (riscvtest.s, LedCounter/main.s)	none found	? → 2024-12-26, ?	none
stnolting__neorv32-setups	NEORV32 exemplary setups: open-source-toolchain (osflow) BoardTop for the ULX3S	85F (PNRFLAGS –85k for BOARD=ULX3S)	open; GHDL/yosys synth_ecp5 + nextpnr-ecp5 + ecppack via osflow makefiles	VHDL (41, boardtop + osflow glue; NEORV32 core itself is an external dependency)	BSD-3-Clause	? → 2026-09-02, ?	none
sylefeb__a5k	a5k: Another World / Out of This World game engine in hardware (Silice); ULX3S support is a prebuilt HDMI bitstream only	unknown (prebuilt .bit; no ULX3S constraint/build files present; primary target is iCE40 UP5K)	n/a for ULX3S (prebuilt bitstream); main design uses open Silice+yosys+nextpnr for the UP5K target	Silice (4 .si: VM/blitter/rasterizer), Python (game-data prep)	mixed: MIT (Silice design) + CC-BY-NC-SA-4.0 (write-up) + GPL/copyrighted (ported game data, not included)	? → 2023-10-06, ?	none
td0034__fpga	Multi-board (iCESugar + ULX3S) FPGA examples collection, bundling the official ULX3S KiCad hardware design	85F (DEVICE ?= –85k in Makefile.inc)	open (yosys+nextpnr-ecp5+ecppack via Makefile.inc)	Verilog (17 .v across examples); large KiCad/mechanical asset counts (kicad_mod, lib, dcm, wrl, scad, stl) are PCB, not HDL	MIT-style (“Copyright 2016-2018 EMARD”) in ulx3s/LICENSE.md and synth-fpga-module/LICENSE.md - looks like the stock ULX3S board license, not td0034’s own	? → 2026-03-05, ?	ulx3s/ dir’s KiCad schematics (wifi/usb/gpio/ram/power/analog/gpdi/blinkey) appear copied from the official emard/ulx3s board hardware repo, not authored here
thata__td4-ulx3s	TD4 4-bit toy CPU (from the Japanese book “CPUの創りかた”) ported to ULX3S	85F (nextpnr-ecp5 –85k)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (1), SystemVerilog (1 top)	none found	? → 2024-12-06, ?	none (book-based educational CPU design, no upstream repo cited)
thata__ulx3s-uart-loopback	Minimal UART loopback test on ULX3S (SystemVerilog top wrapping a Verilog UART module)	85F (Makefile nextpnr-ecp5 –85k)	open: yosys+nextpnr-ecp5+ecppack+fujprog via Makefile	SystemVerilog (1 .sv), Verilog (1 .v)	none found	? → 2024-11-19, ?	none
theperfectcomputer__learn-clash	Personal Clash (Haskell HDL) learning exercises, several targeting ULX3S	85F (–85k in ulx3s/makefile; IDCODE 0x41113043 = 85F)	open (yosys+nextpnr-ecp5+ecppack)	Haskell/Clash (19 .hs)	none found	? → 2024-04-17, ?	none
thewbi__ulx3s	ULX3S Lattice Diamond tutorial: blinky walkthrough + SDRAM controller testbench notes	85F (LFE5U-85F per README board-feature notes)	diamond	Verilog, 4 files (blinky.v, MT48LC16M16A2.v model, tb_sdram_controller.v)	none found	? → 2025-09-15, ?	none
thorkn__vexriscv-ulx3s-helloworld	VexRiscv (SpinalHDL, Murax SoC) “hello world” on ULX3S	85F (CHIP := 85k)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (8 top-level .v; vexriscv/ subdir is mostly Scala (81) generating Verilog), C (hello_world firmware)	MIT, but only inside vexriscv/LICENSE (vendored VexRiscv); no license for thorkn’s own wrapper files	? → 2020-09-28, ?	bundles a full copy of SpinalHDL/VexRiscv (vexriscv/ subdir, MIT-licensed upstream)
thorkn__vexriscv-ulx3s-simple-plugin	Tutorial: custom VexRiscv (SpinalHDL) instruction plugin built as a Murax SoC, deployed and debugged on the ULX3S	85F (ulx3s/Makefile CHIP=85k)	open; yosys+nextpnr-ecp5+ecppack (ulx3s/Makefile); Scala/SpinalHDL generates the Verilog	Scala/SpinalHDL (45 .scala, generates Murax.v), C (2, firmware test), some assembly (1 .S)	MIT (only found inside vendored vexriscv/ submodule copy; no top-level LICENSE)	? → 2020-10-02, ?	built on SpinalHDL/VexRiscv Murax SoC example
titouanc__fpga-scratchpad	fpga-scratchpad: small Migen/LiteX Verilog examples (hello-world LEDs/buttons, binary clock, CSR) plus a LiteX RISC-V SoC demo, built for the ULX3S board	ECP5 12F (fpga_platform.py: device="LFE5U-12F"); README also runs litex_boards.targets.ulx3s --device LFE5U-12F --build for a RISC-V demo	open (Migen/LiteX Platform.build() -> trellis toolchain: yosys+nextpnr-ecp5+ecppack, via litex_boards’ external Platform class; no local LPF file, pin constraints come from litex_boards)	Python/Migen (4 files); no Verilog checked in (LiteX generates it at build time)	none found	? → 2021-03-25, ?	none
tommythorn__bluespec_blink	LED blink ‘hello world’ on ULX3S written in Bluespec (BSV), with generated Verilog checked in for reference	85F (Makefile nextpnr-ecp5 –85k)	open: bsc (Bluespec compiler) -> yosys+nextpnr-ecp5+ecppack+fujprog via Makefile	Bluespec (1 .bsv), Verilog (1 .v, bsc-generated mkBlink.v, committed for reference)	none found	? → 2025-03-09, ?	none
tomverbeure__ecp5_jtag	Colorlight i5: reverse-engineering notes plus a SpinalHDL/Verilog example demonstrating the Lattice ECP5 JTAGG user-JTAG primitive (blink an LED via JTAG)	25F (–25k, CABGA381; Colorlight i5 board)	open (yosys+nextpnr-ecp5 –25k+ecppack; SpinalHDL/Scala generates the Verilog top via sbt)	Verilog (5 .v: 2 in verilog/, 3 testbench in tb/src/), Scala/SpinalHDL (1 file, Ecp5JtagDemo.scala)	none found (no LICENSE/COPYING file, no SPDX headers found in source)	? → 2021-07-23, ?	none
tristanitschner__ulx3s-examples	Three small ULX3S Verilog examples: UART hello-world, DDS sound synth, delta-sigma wave playback	85F (nextpnr-ecp5 –85k in Makefiles)	open: yosys+nextpnr-ecp5+ecppack	Verilog, ~8 files	GPL-2.0	? → 2022-10-01, ?	none
ultraembedded__orangecrab	OrangeCrab: DDR3 128MB read/write memory test gateware (ddr_test) for the OrangeCrab r0.2 ECP5 board	unknown (no nextpnr device flag in source; only prebuilt .dfu bitstream present)	unknown (no build script in source; plain synthesizable Verilog/SV suggests a yosys+nextpnr-ecp5 flow, unconfirmed)	Verilog (11 .v), SystemVerilog (1 .sv: ecp5pll)	Apache-2.0 (LICENSE, root; matches per-file headers in ddr3_axi*.v)	? → 2020-08-21, ?	none
ulx3s__anotherworld_fpga	Another World VM mirror (iCE40 only)	n/a	open (iCE40)	Verilog	none found	2020-02-23 → 2020-02-28, 23	stale mirror of felipesanches (pre-ECP5)
ulx3s__blink	Official ULX3S blink-LED reference example (GPL-3.0)	85F (nextpnr-ecp5 –85k in Makefile; prebuilt .bit for 12f/45f/85f included)	open: yosys+nextpnr-ecp5+ecppack via plain Makefile	Verilog (1 .v)	GPL-3.0	? → 2022-05-16, ?	none (canonical ulx3s org example)
ulx3s__fpga-odysseus	FPGA Odysseus workshop (Radiona 2019): progressive tutorials	25F (apio ulx3s-25f)	open (apio)	Verilog (173 .v)	none found (picorv32 ISC etc.)	2019-03-03 → 2023-11-01, 35	ULX3S follow-up of mmicko__fpga101-workshop by the same author (Miodrag Milanović): 10 identical files (grom CPU, i8080/Altair, UARTs); upstream of lawrie examples
ulx3s__ulx3s-examples	ULX3S Examples: official getting-started (blinky, ESP32 passthru, docs, binaries)	12F (diamond), 25k/45k/85k (open)	both	Verilog, VHDL	mixed: GPL-3.0 (blinky), BSD (passthru); none at top	2019-03-02 → 2020-10-11, 86	blinky/OpenSource from doctorwkt
wuxx__colorlight-fpga-projects	Colorlight i5/i9/i9plus/5a-75b: vendor example collection (blink, uart, VGA/HDMI test pattern, OLED, PicoRV32 picosoc, LiteX-with-DRAM Linux) for Colorlight ECP5/XC7A breakout boards	25F (i5, 5a-75b-v7.0: LFE5U-25F-6BG381/256, –25k) and 45F (i9: LFE5U-45F-6BG381, –45k); i9plus is Xilinx XC7A50T (not ECP5)	open (yosys+prjtrellis+nextpnr-ecp5, ecppack->svf via openocd/dapprog); also an amaranth_boards Python board def	Verilog (34 .v)	Apache-2.0 (LICENSE, top-level, applies to the whole repo)	? → 2026-09-15, ?	none
wuxx__icesugar	iCESugar: MuseLab’s vendor example/demo collection for the iCESugar v1.5 board (iCE40 UP5K) - basic Verilog/SpinalHDL peripheral tests plus advanced SoC and retro-computing cores	iCE40 UP5K (NOT ECP5) - SG48/QFN48 package (–up5k –package sg48, e.g. src/basic/verilog/leds/Makefile)	open (yosys+nextpnr-ice40+icepack); src/advanced/picorv32 and icicle also build RISC-V firmware via riscv-gnu-toolchain	Verilog (189 .v total incl. submodules), SystemVerilog (31 .sv, mostly icicle/ RV32 core), VHDL (13 .vhd, in up5k-demos), Python (21, pmodoled2 tools)	none found at repo root; per-subtree: icicle/LICENSE (ISC-style, Graham Edgecombe), picorv32 README states ISC, iceZ0mb1e submodule LICENSE (MIT), up5k_6502 submodule LICENSE (MIT), up5k-demos submodule has no LICENSE file	? → 2026-07-31, ?	none (collection; several src/advanced/ subdirs are wuxx’s forks of upstream projects, see notes)
wuxx__icesugar-pro	iCESugar-pro: vendor example collection (blink, UART TX, HDMI test pattern, LiteX+VexRiscv Linux-on-DRAM demo) for the iCESugar-pro DDR2-SODIMM-form-factor ECP5 dev board	25F (LFE5U-25F-6BG256C, –25k –package CABGA256)	open (yosys+nextpnr-ecp5+ecppack, timing-allow-fail on litex build); iCELink DAPLink for drag-and-drop programming	Verilog (13 .v)	none found (no LICENSE file; README “Copyright Statement” section states free for hobby/personal use, contact vendor for commercial use)	? → 2025-09-16, ?	none
yowasp__toolchain-demo	Minimal demo of the YoWASP (WASM-packaged) FPGA toolchain + VS Code extension, targets ULX3S by default	not specified (generic top.lpf; works via YoWASP yosys+nextpnr-ecp5, size not pinned in repo)	open: YoWASP-packaged yosys+nextpnr-ecp5+ecppack, invoked from VS Code via WebUSB bitstream upload	Amaranth (1 top.py)	ISC	? → 2024-01-01, ?	none (YoWASP project’s own demo)

SoCs, CPUs and Linux

Repo	What	FPGA	Toolchain	HDL	License	Active (first → last, commits)	Fork / preferred copy
acairncross__euphrates	Maximum-flow (push-relabel) graph accelerator written in Clash (Haskell->Verilog)	unknown (no nextpnr invocation found in repo; device size not pinned)	open (Clash-generated Verilog, presumably yosys/nextpnr-ecp5 downstream but not scripted in-repo)	Haskell/Clash (10 .hs)	BSD-3-Clause	? → 2020-12-31, ?	none
adrmcintyre__vixen	Vixen: 16-bit RISC-style CPU + VGA/DVI video controller + custom language toolchain for ULX3S	12F (nextpnr –12k)	open (yosys+nextpnr-ecp5+ecppack via Makefile)	Verilog (17 .v: vixen.v, videoctl.v, memory.v, sprites.v, irq_controller.v, video/*), custom asm (26 .asm)	none found	? → 2026-09-09, ?	none
anmho__ulx3_bsv	Bluespec (BSV) environment for ULX3S/ECP5: UART/PLL/SDRAM/Mult18x18D wrappers, plus rv32i, nn_fc (FC NN accelerator) and image_proc example projects	ECP5 85F (apio board ulx3s-85f, e.g. projects/rv32i/Makefile)	open: bsc (Bluespec compiler) emits Verilog -> apio (yosys+nextpnr-ecp5+ecppack) -> apio upload	Bluespec SystemVerilog (26 .bsv), Verilog (13 .v, vendored BSV runtime primitives + Lattice IP wrappers)	none found	? → 2024-03-25, ?	none
antonblanchard__chiselwatt	chiselwatt: tiny POWER ISA soft core in Chisel, with ECP5-EVN and ULX3S build targets	85F (NEXTPNR_FLAGS=–85k –freq 25 for ulx3s; evn board separately uses um5g-85k)	open; Chisel->Verilog, then yosys+nextpnr-ecp5+ecppack via Makefile, dockerized	Chisel/Scala (29), Verilog (6, glue)	CC-BY-4.0 per LICENSE file text (IBM Corp. 2019 header) though GitHub shows NOASSERTION	? → 2023-02-13, ?	none
aravindrajeshkanna__vernier-rv32	Vernier-RV32: RV32IMA 5-stage pipelined SoC (Wishbone, Sv32 MMU, CLINT/PLIC, UART, SPI/SD, boot ROM+loader) that boots Linux to userspace on ULX3S LFE5U-85F	ECP5 85F/45F (fpga/README.md: "17,435 TRELLIS_COMB… on an 85F"; fpga/synth/synth_ecp5.sh); also ECPIX5 (fpga/ecpix5_top.v, fpga/constraints/ecpix5.lpf/ecpix5_ddr3.lpf - also ECP5 family, not NOT-ECP5); also Xilinx Artix-7 (NOT ECP5) via fpga/constraints/generic.xdc + fpga/synth/vivado.tcl, explicitly marked "NEVER EXECUTED"	open (yosys + nextpnr-ecp5 + ecppack, fpga/synth/synth_ecp5.sh, run end-to-end per the script’s own header comment); Xilinx path (Vivado) is an unrun placeholder	Verilog (141 files), Python (21, tooling), C (23, software/riscv-tests firmware)	Apache-2.0 WITH SHL-2.1 (Solderpad HW License 2.1; SPDX header in LICENSE)	? → 2026-09-28, ?	none
asinghani__pifive-cpu	3-stage RV32I(+M) RISC-V CPU core in SystemVerilog + automated Migen-based SoC generator	85F (NEXTPNR_FLAGS=–85k in fpga/ulx3s/Makefile)	open: yosys+nextpnr-ecp5+ecppack (fpga/ulx3s/Makefile); soc/ SoC generation via Migen (Python)	SystemVerilog (27 .sv), Python (42, Migen SoC gen + sv2v flow), Scala (24, unclear/legacy) + submodule hyperram: Verilog (2 .v) + submodule verilog-i2c: Verilog (17 .v)	Apache-2.0 (own repo); submodule soc/third_party/hyperram: no LICENSE file, in-file header claims CERN-OHL-1.2 (hyper_xface.v) - terms not formalized at repo level; submodule soc/third_party/verilog-i2c: MIT (COPYING) - three different license postures in one repo	? → 2021-12-28, ?	none (own core)
assured__ct-key	CT-key: LiteX/VexRiscv SoC with a Wishbone/CSR-mapped secworks AES core, real target for ULX3S (default ECP5-45F) and OrangeCrab	ECP5 45F default (ctkey_ulx3s.py: device=”LFE5U-45F” default, –device overrides)	open: LiteX -> yosys + nextpnr-ecp5 + ecppack via the Trellis toolchain (per README’s oss-cad-suite instructions)	Python/Migen (LiteX SoC + core wrappers), Verilog (14 .v, incl. vendored secworks AES rtl)	BSD-2-Clause (root LICENSE, Assured AB 2024); vendored ctkey_package/src/ctkey/cores/aes submodule carries its own BSD-2-Clause (Joachim Strombergson, 2014)	? → 2025-05-17, ?	none (own SoC target; vendors secworks/aes as a fetched submodule)
bhouvana__aegis-x86-processor	AEGIS-X86: research speculative OoO x86-64 subset CPU (~21k SV lines), reference emulator, lockstep verification, experimental ECP5 bring-up	ECP5 85F (LFE5U-85F CABGA381, FPGA/README.md target table; nextpnr-ecp5 –85k –package CABGA381 –freq 40 in FPGA/flow/Makefile)	open (OSS CAD Suite: yosys+slang frontend+nextpnr-ecp5+prjtrellis+ecppack, FPGA/flow/Makefile); Verilator+cocotb for functional verification	SystemVerilog (108 modules per README badge, RTL/{apic,bpu,cache,core,fp,fpga,lsq,mem,mmu,pmu,prefetch,rename,rob,sched,spec,tb,uopc,vec}), Python (326: emulator/decoder/differential-testing)	none found (README status badge is not a license grant; no LICENSE file)	? → 2026-09-10, ?	none
bnossum__midgetv	iCEBreaker/UPduino2: midgetv - compact Wishbone-B4 RV32I RISC-V core (optional C, M, always Zicsr/Zifencei) hand-tuned for minimal iCE40 LUT/EBR usage, plus extensive test/compliance suite	iCE40 UP5K (NOT ECP5) - SG48 (icebreaker, max_upduino2); also targets iCE40 HX1K (work/hwtst/iceblink40-hx1k/, not UP5K)	open (yosys+nextpnr-ice40+icepack, apio.ini) for icebreaker/upduino2; work/hwtst/max_upduino2/for_iCEcube2/ holds an alternate proprietary Lattice iCEcube2 project	Verilog (77 .v under work/), C (48 .c, incl. midgetv_bin2ebr/genucode utilities), C++ (14 .cpp Verilator testbenches)	Apache-2.0 (top-level LICENSE; file headers e.g. work/code/m_midgetv_core.v reference “LICENCE”)	? → 2020-10-26, ?	none
bonfireprocessor__bonfire-basic-soc	Bonfire RV32IM basic SoC (BRAM + SDRAM), multi-board	85F	diamond (FuseSoC)	VHDL-2008	MIT	2018-04-28 → 2024-10-13, 35	none
bonfireprocessor__bonfire-core	Bonfire Core: modular configurable RISC-V (RV32I) core in MyHDL with real ULX3S/ECP5-85 FuseSoC targets incl. an ECP5 JTAGG debug bridge	ECP5 85F (LFE5U-85F/CABGA381 speed grade 6, docs/timing/TIMING_ULX3S_JTAGG_PIPELINE_COMPARISON.md); also Digilent Arty A7 (NOT ECP5, Xilinx) and Trion T8 FireAnt (NOT ECP5, Efinix) per README	open; FuseSoC 2.4.6 + Edalize 0.6.8 drive MyHDL->VHDL generators then a project-local OSS CAD Suite (yosys+nextpnr-ecp5+ecppack); GHDL/Icarus for sim targets	VHDL (19 .vhd/.vhdl), Python/MyHDL (149: generators, testbenches, SoC glue)	MIT (LICENSE, Bonfire Processor/Thomas Hornschuh 2017; includes LXP32 MIT-style notice)	? → 2026-09-16, ?	none
bonfireprocessor__bonfire-ecp5-jtagg-led-demo	Standalone MyHDL/FuseSoC demo wrapping the ECP5 JTAGG primitive to shift an LED pattern via the JTAG USER1/2 data registers (from bonfire-core)	ECP5 85F ULX3S (LFE5U-85F-6BG381C, README) and ECP5 25F Ice Pi Zero (LFE5U-25F-6MG256C, fusesoc/fpga/icepizero/)	open; FuseSoC generator converts MyHDL to VHDL, then GHDL->Yosys->nextpnr-ecp5->ecppack (“trellis” FuseSoC tool)	VHDL (3: 1 static JTAGG bridge + 2 generated top wrappers), Python/MyHDL (8: generator + src package + pytest)	MIT (LICENSE, Bonfire Processor/Thomas Hornschuh 2017)	? → 2026-07-20, ?	none (extracted from bonfireprocessor/bonfire-core per README)
bqqbarbhg__blipv1	nMigen/Amaranth DVI (TMDS) video output + SDRAM controller library targeting ULX3S 85F, with a check/build task runner	85F (blip/rtl/ecp5/pll.py imports ULX3S_85F_Platform)	open; detail=nMigen/Amaranth -> yosys+nextpnr-ecp5+ecppack via nmigen-boards ULX3S platform	Python 12 (nMigen/Amaranth HDL, no Verilog checked in)	none found	? → 2020-12-25, ?	none
brunolevy__tordboyau	TordBoyau: pipelined RISC-V processor demo (tinyraytracer), with a ULX3S open-toolchain build script	85F (run_ulx3s.sh FPGA_VARIANT=85k)	open; yosys+nextpnr-ecp5+ecppack via run_ulx3s.sh	Verilog (15 .v)	BSD-3-Clause	? → 2023-12-01, ?	none (same author/lineage as brunolevy/learn-fpga’s FemtoRV)
businessmanraduc__doggo-v6	PHANTOM-32: 32-bit RV32IMC six-stage in-order RISC-V soft core (SystemVerilog) with Gshare branch prediction, real ULX3S-85K synthesis Makefile	ECP5 85F (LFE5U-85F-6BG381C, synth/Makefile header)	open; Yosys+nextpnr-ecp5+prjtrellis+openFPGALoader (synth/Makefile); Verilator for sim; Nix shell (shell.nix) pins the toolchain	SystemVerilog (23 .sv) + 2 .vh headers	Proprietary - All Rights Reserved (LICENSE, Copyright 2026 Radu Arseni)	? → 2026-07-12, ?	none (microarchitecture ‘takes after RVCoreP-32IC’ per README, inspiration not code fork)
callummcduff-droid__cpu	CPU: custom 16-bit 5-stage pipelined ISA in SystemVerilog with a C reference model and assembler; has an ULX3S top/lpf but no wired synthesis step	ECP5 (fpga/ulx3s.lpf targets ULX3S; no –XXk chip-size argument anywhere since no PnR step is wired up)	open implied (fpga/ulx3s.lpf is a Trellis/nextpnr-style constraint file) but no synthesis/PnR Makefile target exists: Verilator is the only tool actually invoked (simulation only)	SystemVerilog (14 .sv), C (11 files: assembler + reference_model)	none found	? → 2026-09-19, ?	none
carlosedp__chiselv	ChiselV: RV32I RISC-V core in Chisel, with a FuseSoC ULX3S 85k target	85F (README FuseSoC target: nextpnr_options –85k, part LFE5U-85F-6BG381C)	open; Chisel->Verilog, then yosys+nextpnr-ecp5+ecppack via FuseSoC	Chisel/Scala (31), Verilog (4, PLL glue)	MIT	? → 2026-09-14, ?	none
cbalint13__e-verest	e-VEREST: ECP5 USB-stick board (85F, 1GB DDR3, USB3 FIFO, JTAG/UART) + picorv32 SoC test-firmware	ECP5 LFE5U-85F - CSFBGA285 (nextpnr-ecp5 –85k –package CSFBGA285, utils/test-firmware/Makefile)	open (yosys synth_ecp5 + nextpnr-ecp5 + ecppack; upload via openFPGALoader/ecpprog)	Verilog (9 files: rtl/{firmsoc,picorv32,pll,simpleuart,top}.v, sim/{firmsoc_tb,clkdiv,spiflash,spiflash_tb}.v)	Apache-2.0 (LICENSE, repo root); rtl/top.v file header is ISC (Wolf/gatecat)	? → 2023-04-12, ?	none (test-firmware rtl/top.v adapted from Claire Wolf/gatecat icestorm examples per file header; own PCB design, credits OrangeCrab layout as inspiration)
chipdesign-bv__cdriscv-32s-20	cdriscv-32s-20: 32-bit RISC-V safety-subsystem core (dual-core lockstep), variant 2, with ASIC chip-top and FPGA bring-up docs	45F (LFE5U-45F per doc/fpga_ulx3s.md)	open; yosys synth_ecp5 used only to measure LUT/FF/EBR fit (25986 LUT4 etc.); nextpnr-ecp5/ecppack never run, no bitstream	SystemVerilog (92 .sv), Python (31 .py), RISC-V asm (18 .S)	Apache-2.0	? → 2026-09-18, ?	variant of ChipDesign-BV/cdriscv-32s-10 (not cloned)
chiplet__acorechip-ulx3s	RISC-V ‘ACoreChip’ SoC (from external Chisel a-core project) wrapped with ULX3S top-level, JTAG debug and blinky/fault LEDs	85F (Makefile: PART_BASECONFIG=lfe5u-85f, –85k)	open; detail=yosys+nextpnr-ecp5+ecppack (Makefile), Chisel used upstream to generate ACoreChip.v (not present, submodule unfetched)	Verilog: rtl/top.v (ULX3S wrapper) only; + submodule ACoreChip: Chisel/Scala (1 .scala, generates ACoreChip.v via sbt/make) - its own nested submodules ACoreBase/ProgMem/JTAG/amba (actual CPU core etc.) are still unfetched/empty, so no core RTL is inspectable yet	Apache-2.0; submodule ACoreChip: Apache-2.0 (LICENSE) - same license	? → 2022-05-29, ?	fork/derivation of gitlab a-core/a-core_chisel/ACoreChip (git submodule) + a-core_software/riscv-c-tests
chrismoos__m6502	m6502: compact microcoded cycle-accurate 6502 in SystemVerilog + MCU wrapper	85F default	open (-abc9)	SystemVerilog, Python (cocotb)	MIT	2026-02-17 → 2026-03-01, 5	none
ckdur__riscvconsole	RISCVConsole: Chipyard-based RISC-V SoC aiming to run Linux and drive HDMI graphics, framed as an attempted game console; FPGA targets include ULX3S among several others	ECP5 (ULX3S, fpga/ULX3S/scripts/ulx3s_v20.lpf); all other targets are NOT ECP5: Xilinx Artix-7 (NOT ECP5) - ArtyA7100T, NexysVideo; Altera/Intel (NOT ECP5) - Arrow, DE2, TR4 (Quartus .qsys/.sdc files present)	open for ULX3S (scripts/yosys.tcl implies yosys+nextpnr-ecp5); Quartus for Arrow/DE2/TR4; Vivado likely for ArtyA7100T/NexysVideo (not verified, vendor project files not inspected)	Scala (29, chipyard config only - the SoC Chisel source itself lives in the unfetched hardware/chipyard submodule), Verilog (4), VHDL (7), C/C++ (45, software)	MIT (LICENSE)	? → 2026-09-25, ?	none (uses the chipyard framework as an unfetched submodule, not vendored)
damdoy__ice40_ultraplus_examples	iCE40 UltraPlus Breakout Board: collection of Verilog examples (LEDs, PWM, SPRAM read/write, BRAM, N25Q032A flash read via hard/soft SPI, SB_MAC16 DSP calc, internal PLL) plus a full RISC-V (rv32i) SoC driven over SPI from a Linux host	iCE40 UP5K (NOT ECP5) - package not set in any Makefile (no –package flag passed to nextpnr-ice40; board is the Lattice iCE40UP5K breakout board)	open (yosys+nextpnr-ice40+icepack)	Verilog (26 .v, including riscv/simple_riscv_cpu submodule’s alu/register_file/memory cores)	MPL-2.0 (LICENSE, repo root); riscv/simple_riscv_cpu submodule is GNU LGPL-3.0 (its own LICENSE file)	? → 2022-04-11, ?	none (riscv example bundles the simple_riscv_cpu core as a submodule)
danodus__onramp-fpga	Onramp-FPGA: 32-bit "Onramp" processor SoC (running the Onramp C toolchain) with serial + HDMI/PS2 I/O, targeting ULX3S and iCEPi Zero	ECP5 85F (nextpnr-ecp5 –85k –package CABGA381, boards/ulx3s/Makefile); also ECP5 25F CABGA256 (boards/icepi-zero, same family, not NOT-ECP5)	open (yosys + nextpnr-ecp5 + ecppack, boards/*/Makefile)	Verilog (31 files)	MIT (LICENSE)	? → 2026-05-17, ?	none (implements the Onramp toolchain project on FPGA)
danodus__xgsoc	XGSoC: RISC-V (RV32IMFC) SoC with SDRAM, HDMI video (Graphite 2D/3D accelerator), PS/2, USB host, SD card	85F (rtl/ulx3s/Makefile: DEVICE := 85k); also ships an icepi-zero/ target at 25k	open: yosys+nextpnr-ecp5+ecppack via rtl/ulx3s/Makefile	C (72 .c), Verilog/SystemVerilog (20 .v + 9 .sv), Lua (7) + submodule graphite: SystemVerilog (5 .sv), C (11 .c), Python (7 .py)	MIT (own repo); submodule external/graphite: MIT (LICENSE, Daniel Cliche) - same license, no conflict	? → 2026-02-17, ?	none (danodus own SoC, doc site at danodus.github.io/xgsoc)
darklife__darkriscv	darkriscv: minimal RV32 core, boards/ulx3s SoC demo wrapper	85F (Makefile nextpnr-ecp5 –85k)	open; yosys synth_ecp5 + nextpnr-ecp5 + ecppack; openFPGALoader upload	Verilog (50 .v: darksocv/darkriscv/darkuart/darkram/darkbridge/darkpll)	BSD-3-Clause (root LICENSE, BSD header in boards/ulx3s/Makefile)	? → 2026-09-04, ?	none
datanoisetv__colorlight-i9-aes67	AES67/RAVENNA audio-over-IP bridge for Colorlight i9 v7.2: hardware PTP (IEEE1588) + RTP engine + VexRiscv/LiteX soft CPU running lwIP for management	45F (LFE5U-45F-6BG381C, –45k –package CABGA381, Makefile DEVICE/PACKAGE vars) - Colorlight i9 v7.2	open (yosys+nextpnr-ecp5+ecppack, openFPGALoader program/flash) for standalone RTL; LiteX (litex/soc.py) builds the VexRiscv SoC variant; Docker image bundles OSS CAD Suite+LiteX+lwIP+RV32 GCC	Verilog (37 .v, rtl/), C (firmware/, lwIP-based management firmware)	MIT (LICENSE, root)	? → 2026-04-06, ?	none
daveshah1__ulx3s	Early (2018) FuseSoC-packaged mor1kx OpenRISC SoC ported to ULX3S (orpsoc_top.v), with SDRAM boot + Linux-boot scripts	45F (ulx3s.core nextpnr_options: –45k, –basecfg empty_lfe5u-45f.config)	open: yosys+nextpnr-ecp5 (via prjtrellis/FuseSoC ‘trellis’ tool) + ecppack; sim via Icarus Verilog	Verilog (8 .v + 5 .vh), Assembly (2 .S), Python (1, wb_rom_gen.py)	none found	? → 2018-10-19, ?	none (Dave Shah’s own early ULX3S/prjtrellis bring-up project); ulx3s.core (FuseSoC) depends on external mor1kx-4.1, wb_sdram_ctrl, uart16550, jtag_tap, adv_debug_sys cores
dlobato__cps1-musicbox	RISC-V (VexRiscv) + CPS1 arcade sound-chip (YM2151, MSM6295) emulation SoC built with LiteX/Migen, plays VGM music files	not explicitly pinned in inspected files (LiteX radiona_ulx3s.py board target typically used with ULX3S 85F; no –Nk flag found in this shallow clone’s build files)	open: LiteX/Migen (Python) -> yosys+nextpnr-ecp5+ecppack (LiteX-managed build, no vendored nextpnr flags visible)	Python (15, LiteX/Migen SoC), C (6, VGM player firmware) + submodule jt51: Verilog (60 .v, jotego YM2151 FM core); submodule jt6295: Verilog (12 .v, jotego OKI MSM6295 ADPCM core)	none found (top-level repo has no LICENSE file); submodule gateware/rtl/jt51: GPL-3.0 (LICENSE); submodule gateware/rtl/jt6295: GPL-3.0 (LICENSE) - two GPL-3.0 cores bundled into a project that itself carries no license	? → 2022-04-07, ?	none (own LiteX-based SoC); uses standard LiteX/Migen framework and VexRiscv core as dependencies
dlobato__tfmicro-on-litex-vexriscv	tfmicro-on-litex-vexriscv: PoC running TensorFlow Lite Micro (tfmicro) on a LiteX/VexRiscv SoC, tested on ULX3S with an IS42S16160 SDRAM module	ECP5 85F (README.md:5,8: ‘Tested on ULX3S … –device LFE5U-85F’); ULX3S-only claim, real via an external LiteX target (not vendored in this clone)	open (LiteX -> yosys+nextpnr-ecp5+ecppack, via the external litex-boards package; loaded with openFPGALoader, README.md:11-13)	C/C++ (207, firmware/tfmicro TFLM port + rt), Python (4, sim.py + scripts)	BSD-2-Clause (LICENSE)	? → 2021-04-26, ?	none
dstrbad__fpga-soc-ml-accelerator	dstrbad/fpga-soc-ml-accelerator: Linux-capable VexRiscv LiteX SoC on ULX3S 85F with CSR/DMA matmul ML accelerators	LFE5U-85F	open (LiteX/Migen -> yosys+nextpnr-ecp5+ecppack via litex_boards)	Python/Migen (~10 files), C (10, host-tests/buildroot)	none found	? → 2026-08-04, ?	none
dulatello08__litex-cpu-testing	LiteX testing project: LiteScope logic-analyzer SystemVerilog design plus a separate LiteX-generated VexRiscv RISC-V SoC, both for ULX3S	unknown (Makefile: DEVICE=85k default for rtl/top.sv flow; LiteX gen_soc.py SoC device not confirmed without reading script body)	both; open direct flow for LiteScope (yosys synth_ecp5+nextpnr-ecp5 –85k+ecppack) and open via LiteX (gen_soc.py/Migen-generated build for the SoC)	SystemVerilog (2 .sv: top.sv, unified_memory.sv), C (1 .c firmware), Python (3, LiteX/LiteScope scripts)	none found (no LICENSE/COPYING file)	? → 2025-12-18, ?	none
dulatello08__neocore-fx	NeoCoreFX: custom 16x32 pipelined CPU core (SystemVerilog) targeting ULX3S 85F	85F (ECP5_SIZE ?= 85k; lpf name)	open (yosys+nextpnr-ecp5+ecppack, explicit Makefile vars)	SystemVerilog (41 .sv), plus 17 .f filelists, 9 .hex init files	Apache-2.0 for RTL/testbench (LICENSE); README states the separate NeoCoreFX/NeoCore16x32 toolchain (not in this repo) is GPL-3.0	? → 2026-06-08, ?	none
egorxe__openglory	OpenGlory: open-source fixed-pipeline GPU in VHDL capable of running Quake; LiteX target for the Radiona ULX3S	45F default (device=”LFE5U-45F” in radiona_ulx3s.py, overridable via –device)	open; LiteX + GHDL-yosys-plugin + nextpnr-ecp5 + ecppack (toolchain=”trellis”)	VHDL (37, GPU core), Python (24, LiteX SoC integration), C/C++ (10+10, firmware/sim)	Apache-2.0	? → 2025-02-25, ?	none
emard__had2019-playground	HAD2019 badge playground (emard fork): the ULX3S/ULX4M US2 USB DFU bootloader (PicoRV32 + no2usb-style USB core) with ESP32 passthru multiboot image	12F default (Makefile DEVICE = 12k); comment lists 12k/25k/45k/85k/um-85k/um5g-85k; ULX4M um-85k via ecpmulti idcode fix	open (yosys+nextpnr-ecp5+ecppack, ecpbram to inject fw hex, ecpmulti for multiboot.img); RISC-V gcc for fw/	Verilog (46 .v), C (fw/ DFU firmware on PicoRV32)	per file: bootloader RTL BSD-3-Clause, USB core + DFU firmware LGPL-3.0-or-later, picorv32.v ISC (LICENSE says per-file; see docs/DFUs.md)	? → 2021-12-24, ?	smunaut/had2019-playground (Hackaday Supercon 2019 badge playground)
emard__prjtrellis-picorv32	prjtrellis-picorv32: minimal PicoRV32 SoC (attosoc) with FPGArduino-compatible HEX bootloader, built with the open prjtrellis/nextpnr-ecp5 flow	ECP5 (prjtrellis/nextpnr-ecp5 flow targeting ULX3S; README: “Compiles with latest prjtrellis and fits to ECP5”; ulx3s_v20_segpdi.lpf); README also claims iCE40 via arachne-pnr but no such Makefile target/pcf is present in this clone	both: open (yosys+prjtrellis/nextpnr-ecp5, scripts/ulx3s_trellis.mk) and Lattice Diamond (scripts/ulx3s_diamond.mk); firmware built with RISC-V GCC (firmware.c/start.s/sections.lds)	Verilog (5 files: top.v, attosoc.v, pll.v, simpleuart.v, picorv32.v), C (2 files: firmware.c, helloworld.c)	picorv32.v and attosoc.v carry ISC-style headers (Copyright Clifford Wolf 2015 / David Shah 2018, “permission notice appear in all copies”); no LICENSE file at repo root for the project’s own top.v/pll.v/simpleuart.v/firmware.c	? → 2019-01-18, ?	none (vendors yosyshq/picorv32’s picorv32.v + attosoc.v verbatim; firmware.c ported from the f32c project’s FPGArduino bootloader)
emard__usb_host	USB host core (HID: keyboard/mouse/hub hotplug) with small RISC-V softcore, for ECP5 ULX3S	12F (soc/build.sh: nextpnr-ecp5 –12k; README also says “Bitstream with demo for ULX3S 12F”)	open; yosys+nextpnr-ecp5+ecppack (soc/build.sh)	Verilog (12 .v), C (7, RISC-V firmware, kencc-compiled)	none found	? → 2024-03-31, ?	fork of PNRU’s usb_host (gitlab.com/pnru/usb_host); emard added soc/fw.sh firmware-patch script
emeb__ulx3s_6502	Simple 6502 system (Arlet core), ACIA UART, cc65 firmware	85F	open (+ecpbram)	Verilog, C (cc65) + submodule verilog-6502: Verilog (2 .v: ALU.v, cpu.v)	none found; submodule verilog-6502: no LICENSE file, permissive custom header in cpu.v (Arlet Ottens: ‘feel free to use this code in any project (commercial or not)…as is’)	2020-02-14 → 2020-02-25, 4	none
emeb__up5k_osc	iCE40 UP5K custom Eurorack module (up5k_osc board): digital oscillator generating audio-rate waveforms via NCO + differential PDM DAC, with SPI ADC for CV/pitch inputs and optional picorv32 RISC-V diagnostics core.	iCE40 UP5K (NOT ECP5) - SG48	open (yosys+nextpnr-ice40+icepack, icestorm)	Verilog (11 .v gateware, 8 .v RISC-V wrapper, excl. picorv32 submodule)	MIT (LICENSE, repo root)	? → 2024-11-24, ?	none
evgenymuryshkin__quokkaevaluation	QuokkaEvaluation: C# “Quokka” toolkit that transforms C# controller classes into VHDL/Verilog, plus demo HDL projects (SnakeGame, AES, Fourier, Keccak, etc.)	Cyclone IV E (NOT ECP5) - EP4CE6E22C8 (VHDL/Quokka.qsf: FAMILY “Cyclone IV E”, DEVICE EP4CE6E22C8); also Xilinx Zynq-7020 (NOT ECP5) - Arty Z7-20 (FPGAConf/arty/Arty-Z7-20-Master.xdc); Xilinx Artix-7 35T (NOT ECP5) - Arty A7-35 (FPGAConf/artyA35/artyA35.xpr)	both (Intel/Altera Quartus for fpga/Quokka.qsf; Xilinx Vivado for arty/artyA35 .xdc/.xpr); plus proprietary QuokkaCLI (.NET, C#->VHDL/Verilog code generator, not an HDL synthesis flow itself	C# (185 .cs: toolkit, drivers, per-demo controllers/tests), Verilog (31 .v, generated/hand-written demo RTL, excl. Test dirs), VHDL (19 .vhd, incl. VHDL/fpu100)	none found (no LICENSE file at any depth; README points to a “Quokka Whitepaper.pdf” but no SPDX/license text found)	? → 2026-03-04, ?	none
f32c__f32c	f32c: retargetable RISC-V/MIPS 32-bit soft CPU + SoC library	12F/25F/45F/85F	diamond (trellis attempts marked not working)	VHDL (432 .vhd), Verilog, C	BSD-2-Clause (most files) with MIT parts: rtl/soc/sdram*.vhd, ps2.vhd, vga2dvid.vhd are MIT; usb11 PHY has its own OpenCores-style license (see docs/projects/f32c__f32c.md)	2010-02-27 → 2026-09-22, 5912	none (upstream)
fedy0__neo	NEORV32 RISC-V SoC running on the ULX3S	85F (Makefile DEVICE?=85k)	open; yosys+ghdl-yosys-plugin (VHDL via ghdl -m ghdl)+nextpnr-ecp5+ecppack (Makefile)	VHDL (3 top-level .vhd; core CPU VHDL lives in the unfetched neorv32/ submodule)	MIT	? → 2024-06-07, ?	wraps stnolting/neorv32 (git submodule, not fetched in this shallow clone)
fedy0__zta	fedy0/zta: Ztachip (RISC-V + vector/tensor accelerator) ported to ULX3S — WIP, blocked on 64-bit memory controller	85k default (Makefile DEVICE ?= 85k)	open (yosys + ghdl-plugin for VHDL + nextpnr-ecp5 + ecppack)	Verilog (1), SystemVerilog (1) at top level; bulk of ztachip HDL lives in the unfetched submodule	MIT	? → 2024-07-12, ?	fedy0/ztachip (git submodule, NOT fetched in this shallow clone)
fpgawars__flix-v	FLIX-V: KianV RISC-V SoC running Linux (no-MMU), ULX3S 12F via apio	12F (apio.ini: board = ulx3s-12f)	open; apio wraps yosys+nextpnr-ecp5+ecppack	Verilog (114 .v) + Verilog headers (26 .vh)	LGPL-2.1	? → 2023-11-06, ?	derived from the KianV RISC-V SoC (kianv_harris_mc_edition.v)
fusetim__rusty-soc	Rusty SoC: from-scratch RISC-V RV32I SoC in Silice+Verilog with Rust PAC/HAL, real ULX3S default board target, SD-card audio player app	ECP5 (Silice board profile ‘ulx3s’, hardware/Makefile default BOARD=ulx3s; openFPGALoader -b ulx3s per README)	open; Silice -> Yosys+nextpnr-ecp5, silice-make.sh wrapper, openFPGALoader	Silice (6 .si), Verilog (3, incl. vendored SPI/PLL helpers), Rust (59, PAC/HAL/app crates)	MIT (LICENSE, Copyright 2025 FuseTim and contributors)	? → 2026-02-08, ?	none (CPU is the vendored Silice ‘Ice-V’ core, hardware/lib/silice/projects/ice-v/)
fywc__ulx3s_rv32i_processor	4-stage pipelined RV32I processor written in Bluespec (BSV), targeting ULX3S 85F via apio	85F (Makefile: apio init -b ulx3s-85f)	open; detail=Bluespec (bsc compiler) generates Verilog, then apio (yosys+nextpnr-ecp5+ecppack)	Bluespec/BSV 7 files (Top.bsv + processor/{Execute,Decode,RFile,Processor,Scoreboard,Defines}.bsv); C/asm test programs in sw/	none found	? → 2023-03-15, ?	none
gildobjanschi__riscv_processor	32-bit RISC-V (RV32IMAC+Zicsr/Zicond/Zb*) SystemVerilog microcontroller with SPI flash/SDRAM/PSRAM, targeting ULX3S and Blue Whale ECP5 boards	ECP5 85F (hdl/fpga.sh: nextpnr-ecp5 –85k –package CABGA381 –speed 6); Blue Whale board also ECP5 85F CABGA381 (hdl/fpga.sh -w, hdl/blue_whale.lpf) - same family, not NOT-ECP5	open (yosys synth_ecp5 -noabc9 + nextpnr-ecp5 + ecppack –db, hdl/fpga.sh; installed via apio)	SystemVerilog (26 files), C (7, apps/)	MIT (LICENSE)	? → 2024-09-06, ?	none
glasgowembedded__glasgow	Glasgow Interface Explorer: multi-protocol USB debug/reverse-engineering tool - Amaranth-generated gateware “applets” (SPI/I2C/JTAG/UART/…) driven by a Python host CLI	iCE40 HX8K (NOT ECP5) - BG121 (device=”iCE40HX8K”, package=”BG121”, software/glasgow/hardware/platform/rev_c.py; revC is the reviewed board). Also targets: iCE40 UP5K SG48 (rev A/B, rev_ab.py) and ECP5 LFE5U-25F BG256 (rev D, rev_d.py, software/glasgow/hardware/platform/ecp5.py) - a newer revision is already ECP5	open (yosys+nextpnr-ice40+icepack for iCE40, +nextpnr-ecp5+ecppack for ECP5) via YoWASP (WebAssembly toolchain, software/pyproject.toml: yowasp-yosys, yowasp-nextpnr-ice40, yowasp-nextpnr-ecp5); driven by Amaranth’s build system from the glasgow CLI, not a Makefile	Python/Amaranth HDL: 173 gateware files (26 in software/glasgow/gateware/ + 147 in software/glasgow/applet/*/), 300 Python files under software/ total; C (FX2 8051 firmware, NOT gateware): 19 files in firmware/fx2/ (needs vendor/libfx2 submodule, NOT fetched - empty dir); no Verilog	dual: 0BSD OR Apache-2.0 (LICENSE-0BSD.txt, LICENSE-Apache-2.0.txt at root)	? → 2026-09-25, ?	none
gonsolo__borg	Borg: open-source GPU project - Hutt RISC-V SoC + FP16 shader processor as an MMIO peripheral, targeting ECP5 (ULX3S) as FPGA prototype and GF180MCU (wafer.space) as the ASIC	ECP5 (ULX3S; fpga/ulx3s/*.lpf, README.md:145 ‘FPGA (ULX3S - ECP5)’); also GF180MCU (NOT an FPGA) - ASIC target via wafer.space/LibreLane, not a second board	open (yosys+nextpnr-ecp5+ecppack via make load/make flash in fpga/ulx3s, README.md:150-153); Chisel/Mill generates the Verilog	Scala (206, Chisel RTL), Verilog (21, generated/wrapper), SystemVerilog (5), Python (40, cocotb tests/tools), C/C++ (49)	multiple per-component (LICENSES/: Apache-2.0, BSD-3-Clause, CERN-OHL-S-2.0, GPL-3.0-or-later, MIT); Hutt CPU itself is CERN-OHL-S-2.0 per README Bill of Materials	? → 2026-09-28, ?	none
google__cfu-playground	CFU-Playground: framework for building/benchmarking custom CFU (Custom Function Unit) accelerators on VexRiscv/LiteX SoCs for embedded ML inference	Multi-board via LiteX, mostly NOT ECP5: Xilinx Artix-7 (NOT ECP5) - Arty A7-35T/100T (README.md:30); iCE40 (NOT ECP5) - iCEBreaker, Fomu; ECP5 - OrangeCrab, ULX3S (README.md:30, docs/source/setup-guide.rst:23); Xilinx (NOT ECP5) - Nexys Video. litex_boards submodule not fetched so ULX3S device size/constraints unverifiable here.	open (LiteX/Migen generic build, backend picked by litex_boards target; likely yosys+nextpnr-ecp5 for ULX3S, unverifiable: litex_boards submodule not fetched)	Python (147, LiteX/Migen SoC + build scripts), C/C++ (665, firmware/TFLM), Verilog (26, CFU/accelerator RTL under proj/), SystemVerilog (4), Scala (1)	Apache-2.0 (LICENSE)	? → 2026-02-26, ?	none
greatscottgadgets__cynthion	Cynthion: official GSG gateware (USB analyzer, Moondancer/Facedancer SoC, selftest) for the Cynthion ECP5 USB tool	12F (LFE5U-12F, BG256, Cynthion r0.1-r1.4) - cynthion/python/src/gateware/platform/cynthion_r1_4.py: clk_60MHz on A8, 3x ULPI (control/aux/target), HyperRAM (Winbond W956A8MBYA6I), speed grade via ECP5_SPEED_GRADE env (default 8); no other board targets found	open (Amaranth build backend -> yosys+nextpnr-ecp5+ecppack, invoked via top_level_cli / python -m cynthion.gateware.<name>.top); programmed via Apollo (apollo_fpga.ECP5_JTAGProgrammer, an external MCU, not part of this repo’s gateware)	Python/Amaranth (34 .py in gateware/: analyzer 8, facedancer 4, selftest 1, platform 13, interfaces 2, vendor; 72 .py total incl. host commands), Rust (223 .rs: firmware/moondancer+smolusb+libgreat+ladybug MCU firmware, not FPGA)	BSD-3-Clause (LICENSE.txt)	? → 2026-05-22, ?	none
greatscottgadgets__luna-soc	LUNA-SoC: Amaranth Wishbone/CSR SoC framework (VexRiscv/Minerva CPU, UART/timer/USB2/SPI-flash cores) used by Cynthion’s Moondancer	12F (LFE5U-12F, BG256, Cynthion) - luna_soc/gateware/provider/cynthion.py + examples/hello-c/top.py (LUNA_PLATFORM=cynthion…; CLOCK_FREQUENCIES_MHZ sync=60); framework itself is platform-parametric (Amaranth build backend); examples/hello-c/Makefile also has a load-ulx3s target though no ULX3S platform file is bundled here	open (Amaranth build backend: yosys+nextpnr-ecp5+ecppack); VexRiscv Verilog generated via SpinalHDL/sbt (cpu/verilog/Makefile, requires Scala/sbt, outside the open FPGA flow)	Python/Amaranth (53 .py: core/cpu/interface/provider/vendor), Verilog (5 .v: SpinalHDL-generated VexRiscv variants in cpu/verilog/vexriscv/), Scala (5 .scala: VexRiscv generators)	BSD-3-Clause (LICENSE.txt)	? → 2025-05-19, ?	none
gregdavill__luna-usb-serial-acm	ButterStick/LUNA: Amaranth-generated USB ACM (virtual serial) IP core wrapped for LiteX SoC integration	n/a (pure IP-core generator; no LPF/device/package specified, no nextpnr/ecppack step)	open (Amaranth -> yosys write_verilog via build_verilog.py; requires pip-installed luna + amaranth-yosys)	Python (3 .py: Amaranth/migen), Verilog (1 .v, 13967 lines, machine-generated by Yosys)	BSD-2-Clause (LICENSE, root; matches “License: BSD” file headers)	? → 2026-01-31, ?	greatscottgadgets/luna (LUNA USB gateware stack; Amaranth-generated verilog via build_verilog.py)
gtjennings1__hyperbus	UPduino: HyperBus/HyperRAM controller plus a PicoRV32 RISC-V SoC demo for iCE40 UltraPlus (iCEStorm/APIO/Radiant flows), with a companion rev-C HyperRAM/HyperFlash PMOD PCB	iCE40 UP5K (NOT ECP5) - SG48 (arachne-pnr -d 5k -P sg48); same UP5K target also built via a Lattice Radiant project (radiant/)	both - open (yosys+arachne-pnr+icepack, or APIO) and Diamond/Radiant (radiant/riscv32_radiant.rdf)	Verilog (23 .v)	none found (standalone/hbc.v and sim/hbc_tb.v carry an embedded MIT-style header “Copyright 2017 Gnarly Grey LLC”; no LICENSE/COPYING file in repo)	? → 2019-01-08, ?	none (RISC-V SoC based on mmicko’s fpga101-workshop PicoSoC examples per README)
hanseo03__ulx3s-custom-riscv-cpu	Custom single-cycle/pipelined RV32I CPU (with simple in-house OS/multitask kernel) for ULX3S 12F, Windows .bat build flow	12F (build_custom_fpga.bat: nextpnr-ecp5 –12k)	open; yosys synth_ecp5 + nextpnr-ecp5 –12k –lpf-allow-unconstrained + ecppack, driven by Windows .bat scripts (no Makefile-based ULX3S build)	Verilog (14 .v), C (5 .c, incl. tiny os_kernel.c/os_pool.c), RISC-V asm (4 .s)	none found (no LICENSE/COPYING file)	? → 2026-07-07, ?	none
hanseo03__ulx3s-vexriscv-soc	VexRiscv (Scala/SpinalHDL-generated) SoC on ULX3S 12F, with C firmware and Windows .bat build flow	12F (build_vex_fpga.bat: nextpnr-ecp5 –12k, comment “LFE5U-12”)	open; yosys synth_ecp5 + nextpnr-ecp5 –12k –lpf-allow-unconstrained + ecppack, driven by Windows .bat scripts	Verilog (5 .v, incl. generated VexRiscv.v), RISC-V asm (3 .s), Python (2 .py), Scala (1 .scala generator)	none found (no LICENSE/COPYING file)	? → 2026-06-04, ?	none (uses upstream SpinalHDL/VexRiscv.v generated core, fetched via get_vexriscv.bat)
hsa-ees__piconut	PicoNut: minimal, extensible RISC-V (RV32IMA) system modeled in SystemC for teaching/research, targets ULX3S and OrangeCrab	85F (“ULX3S (Yosys, ECP5 85k)” and –85k –package CABGA381 in boards/ulx3s/piconut-board.mk)	open: yosys+nextpnr-ecp5+ecppack via piconut-board.mk build glue; also Docker/devcontainer build environment	C++ (282 .cpp SystemC), C (47), Python (17)	BSD-2-Clause (top-level LICENCE; note: hw/common/riscv_disasm/LICENSE is a separate bundled BSD-3-Clause Spike-derived file)	? → 2026-09-01, ?	none (HSA-EES academic project)
icebreaker-fpga__icetwang	iCEBreaker-bitsy: iCEtwang, a TWANG-inspired 1D LED-strip game console SoC (PicoRV32 + no2usb/no2ice40/no2misc Wishbone cores) driving an APA102 LED string from joystick input, with Rust firmware and a desktop game simulator	iCE40 UP5K (NOT ECP5) - SG48 package (soc/ice-twang/Makefile: DEVICE=up5k PACKAGE=sg48)	open (yosys+nextpnr-ice40+icepack, via no2build project-rules.mk)	Verilog (65 .v total: soc/ice-twang/rtl ~15, no2ice40 11, no2misc 18, no2usb 10, plus sim files)	mixed: rtl/top.v and no2ice40/no2misc are CERN-OHL-P-2.0 (LICENSE); no2usb core is LGPL-3.0-or-later, its tinyusb-derived driver and utils are MIT (per no2usb/LICENSE.md); hardware/ KiCad dirs have none found	? → 2021-12-07, ?	none (built on no2fpga no2usb/no2ice40/no2misc cores, listed as submodules not forks)
im-tomu__foboot	Foboot: the Fomu iCE40 UP5K failsafe USB DFU bootloader, LiteX/Migen SoC (VexRiscv + ValentyUSB eptri core), touch-pad-forced-DFU entry	iCE40 UP5K (NOT ECP5) - Fomu evt/pvt/hacker revisions (hw/foboot-bitstream.py:51-66, litex_boards.platforms.fomu_*)	open; LiteX/Migen-generated (yosys+nextpnr-ice40+icepack via LatticePlatform, hw/foboot-bitstream.py:20-24); RISC-V gcc for sw/ (VexRiscv core)	Python (83, Migen/LiteX SoC generator incl. valentyusb submodule), C (39 .c, 90 .h sw/), Verilog (4 .v, VexRiscv_Fomu*.v + generated dut)	foboot itself Apache-2.0 (LICENSE, 202 lines); hw/deps/valentyusb submodule BSD-3-Clause (hw/deps/valentyusb/LICENSE, Luke Valenty 2018)	? → 2022-12-31, ?	none (built around the ValentyUSB core, submodule)
jamesbowman__swapforth	swapforth: cross-platform ANS Forth; ships J1a/J4a minimal stack-CPU FPGA cores (mostly Forth software otherwise)	iCE40 HX8K (NOT ECP5) - package unspecified/default ct256 (arachne-pnr -d 8k, j1a/icestorm/Makefile); also iCE40 HX1K/iCEstick default device (j1a.pcf, no -d flag) and FT900 non-FPGA MCU host (ft900/)	open (yosys+arachne-pnr+icepack+icemulti), j1a/icestorm/Makefile; j1a/nandland-go/ is a near-duplicate build for the Nandland Go board	Verilog (24 .v), Python (20, host tools/sim), Forth (77 .fs, the actual product), C (esp8266/ft900 hosts)	BSD-3-Clause (LICENSE, James Bowman 2015)	? → 2023-09-29, ?	none
jeli180__shape-inference-soc	Shape Inference SoC: 5-stage RV32I pipeline + integer MLP systolic-array accelerator on ULX3S-85K, classifies hand-drawn shapes streamed over UART	ECP5 85F (Lattice ECP5-85K/CABGA381, README implementation table)	open; yosys+nextpnr-ecp5(router2)+ecppack (Makefile)	SystemVerilog (33 .sv: cpu/dcache/icache/mshr/systolic_array/tensor_controller/uart_tower/etc.)	none found	? → 2026-09-09, ?	none
jerry-d__sympl_ieee754-2019_isa	SYMPL IEEE 754-2019 ISA Compute Engine: 32/64/128/256-bit ISA + debugger, alpha-stage; only a demo/binary release with flashing instructions for the ULX3S -85F is published	ECP5 85F (Quick_Start.txt: ‘Lattice device must be a ECP5 85F size’; RADIONA ULX3S -85F) - ULX3S-only, single board; no HDL/constraint files to verify device size independently	unknown - no build scripts/HDL/LPF in this clone; only pre-built demo assets are present (folder holds .HEX/.LST/.asm/.INI, no .bit found by extension search)	none in this clone (no .v/.vhd/.sv files); README describes a hardware ISA engine but source is not published here	custom Non-Commercial Evaluation License (LICENSE.TXT) - not an OSI/SPDX license; explicitly non-commercial, evaluation-only	? → 2023-12-08, ?	none
joaln27__koti	Koti: RV32IMA Linux-capable SoC (CPU+MMU+SDRAM+SD+HDMI+USB+ESP32) for ULX3S 85F	85F (LFE5U-85F per README and nextpnr.log)	open (yosys+nextpnr-ecp5+ecppack, implied by LFE5U-85F nextpnr.log reference)	SystemVerilog (49 .sv), Verilog (22 .v, mostly vendor/), C (17, firmware)	Apache-2.0	? → 2026-08-20, ?	none (vendor/ dir bundles reused third-party IP: audio.sv, sd_spi.sv, tmds_encoder.sv, usb_hid_host.v, dvi_tx.sv)
john-k__spinose	SPINose: LiteX gateware to dump external SPI NOR flash via the BIOS mr command	25F (default; 12F via flash-12f.sh; 45F/85F via –device)	open: yosys+nextpnr-ecp5+ecppack via LiteX/Migen	Python (LiteX/Migen), 2 files	BSD-2-Clause	? → 2020-04-11, ?	none
kulp__tenyr	tenyr: 32-bit orthogonal computer architecture + full software toolchain, with a hw/yosys ULX3S 12F build	12F (NEXTPNR_FLAGS –12k)	open; yosys+nextpnr-ecp5+ecppack via hw/yosys/Makefile	Verilog (16, CPU core+top), C (38, assembler/simulator/tools), custom .tas/.to (161+20, tenyr assembly) + submodule wb_intercon: Verilog (5 rtl .v + 5 bench .v, olofk Wishbone mux/arbiter/cdc/resize/upsizer)	MIT-style (COPYING; Darren Kulp/Forest Belton copyright); submodule 3rdparty/wb_intercon: ISC License (LICENSE, Olof Kindgren) - permissive, no conflict	? → 2026-08-15, ?	none
lawrie__spinalulx3s	Grab-bag of SpinalHDL example designs for ULX3S: HDMI, VGA, PS/2, USB host, audio, OLED, plus prebuilt SaxonSoc Linux bitstreams	85F (Makefile: –85k)	open: SpinalHDL (Scala, sbt build) -> generates Verilog -> yosys+nextpnr-ecp5+ecppack via per-feature Makefiles	Scala (37, SpinalHDL), Verilog (2, hdmi.v/hdmi_pll.v glue)	none found	? → 2020-03-29, ?	includes prebuilt SaxonSoc (SpinalHDL/SaxonSoc) bitstreams in saxon-bin/
lazardjurovic__edulent_rtl	Edulent: educational CISC 8/16-bit CPU (39-instruction ISA) in SystemVerilog, built for ULX3S ECP5-12F via yosys, also targets Xilinx via Vivado	ECP5 12F (rtl/Makefile: nextpnr-ecp5 –12k –package CABGA381); also an unspecified Xilinx device via rtl/constraints/vivado.xdc – NOT ECP5 for that path (manual Vivado import only, no automated flow)	both: open (yosys synth_ecp5 + nextpnr-ecp5 + ecppack via rtl/Makefile yosys target) and Vivado (manual project import per README)	SystemVerilog (10 .sv)	none found	? → 2025-03-26, ?	none (own university coursework project)
litex-hub__linux-on-litex-vexriscv	Linux on LiteX-VexRiscv (OpenSBI, buildroot)	45F/85F in practice (device via –device)	open (LiteX → yosys/nextpnr/trellis)	Migen/LiteX (Python), VexRiscv (SpinalHDL→Verilog)	BSD-2-Clause	2019-04-25 → 2026-09-14, 812	none
lucasebskora__wav-player	Wav-player: SD-card music-player SoC (RISC-V Ice-V core + OLED art + push-button menu) for ULX3S, built on Silice’s soc_wave_player example	ECP5 (Silice board profile ‘ulx3s’, Makefile default BOARD=ulx3s)	open; Silice -> silice-make.py -> Yosys+nextpnr-ecp5 (root Makefile calls silice-make.py -b $(BOARD))	Silice (3 .si: ice-v.si, ice-v-oled.si, soc-wav.si), C (firmware, ~28 files)	MIT (LICENSE, Copyright 2024 Lucas Eduardo Bonancio Skora)	? → 2025-02-07, ?	Silice learn-silice/classroom/soc_wave_player example (README: ‘almost all files were copied with little to no alterations’)
machdyne__zeitlos	Zeitlos: WIP RISC-V SoC + graphical OS for FPGA computers, multi-board incl. ULX3S (12F/25F/45F/85F)	25F default (DEVICE ?= 25k for BOARD=ulx3s); 12F/45F/85F also supported via DEVICE= override	open; yosys+nextpnr-ecp5+ecppack; openFPGALoader program/flash	C (530, OS/apps), Verilog (183, SoC RTL), Python (130, tools/ask assembler)	custom BSD-2-Clause-style (Lone Dynamics Corp, LICENSE.md); bundled rtl/sw components carry their own MIT/BSD licenses	? → 2026-09-27, ?	none (successor to Machdyne’s own Zucker project)
markus-zzz__hyperram-test	ULX3S HyperRAM add-on board test: PicoRV32 SoC writes/reads a Fibonacci sequence to HyperRAM to verify board assembly	ECP5 25F (nextpnr-ecp5 –25k in syn/build-ulx3s.sh), packed with ecppack –idcode 0x21111043 (25k-image-on-12F trick)	open (yosys ulx3s-top.ys -> nextpnr-ecp5 –25k –lpf ulx3s.lpf -> ecppack), per syn/build-ulx3s.sh	Verilog (5 .v files: rtl/top.v, rtl/hyper_xface.v, rtl/picorv32.v, rtl/spram.v, rtl/sprom.v, plus syn/ulx3s-top.v)	mixed per file: GPL-3.0-or-later (rtl/top.v, syn/ulx3s-top.v, rtl/spram.v, rtl/sprom.v headers, Markus Lavin); CERN-OHL-v1.2 (rtl/hyper_xface.v header, Kevin M. Hubbard/blackmesalabs); ISC (rtl/picorv32.v header, Clifford Wolf)	? → 2021-12-30, ?	none (vendors hyper_xface.v from blackmesalabs/hyperram and picorv32.v from YosysHQ/picorv32, per README)
markus-zzz__max9850-test	Small picorv32-based testbench for a custom ULX3S MAX9850 audio-codec expansion board: blinks an LED via SW-driven I2C to verify the board assembly	ECP5 25F (syn/build-ulx3s.sh: nextpnr-ecp5 –25k –idcode 0x21111043, the documented 25k-build-on-12F trick)	open; Yosys+nextpnr-ecp5+ecppack (syn/build-ulx3s.sh); Verilator for sim (sim/build-verilator.sh)	Verilog (4: picorv32.v vendored, spram.v, sprom.v, top.v), C (1, sw/max9850-test.c)	none found at repo root; rtl/picorv32.v carries its own ISC license header (Clifford Wolf 2015)	? → 2022-01-30, ?	none (vendors Clifford Wolf’s picorv32 core directly)
markus-zzz__zzz-rv	ZZZ-RiscV32: 5-stage RV32IMA core (Amaranth), boots Linux NoMMU; real ULX3S synthesis files though README’s FPGA section is a placeholder	ECP5 (syn/ulx3s.lpf + syn/ulx3s-top.v; also used directly in sim/soc.vvp’s Icarus cosim against a Micron SDRAM model)	open; Amaranth HDL generates cpu.v (python3 rtl/cpu.py), then YoWASP/Yosys+nextpnr-ecp5+ecppack; Verilator and Icarus Verilog both used for simulation	Python/Amaranth (10 .py, generates Verilog), Verilog (generated + syn/sim wrappers)	CERN-OHL-P v2 (LICENSE, Permissive variant)	? → 2023-09-16, ?	none
mcejp__poly94	Poly94: custom 32-bit CPU/SoC computing platform with firmware SDK, sim and CI	85F (nextpnr-ecp5 –85k in Makefile; prebuilt .bit for 12F/45F/85F also in repo root)	open; yosys+nextpnr-ecp5+ecppack (Makefile)	Verilog (13 .v) + SystemVerilog (12 .sv), C/H firmware (14), Python tooling (7), Scala (GenPoly94Cpu.scala, CPU generator) + submodule verilog-uart: Verilog (30 .v, alexforencich UART/AXI-Stream core)	GPL-3.0; submodule lib/verilog-uart: MIT (COPYING, Alex Forencich) - permissive, compatible with GPL-3.0 main project	? → 2024-03-03, ?	none
michaelbell__nanov	NanoV: minimal-area bit-serial RISC-V (RV32E) core + SPI FRAM controller, taped out on Tiny Tapeout 4; also runs on iceFUN and pico-ice	iCE40 HX8K (NOT ECP5) - CB132 (root Makefile: nextpnr-ice40 –hx8k –package cb132, iceFUN.pcf); also iCE40 UP5K (NOT ECP5) - SG48 (pico_ice/Makefile: –up5k –package sg48, pico_ice.pcf); primary target was Tiny Tapeout 4 ASIC (not FPGA), per README	open (yosys synth_ice40 + nextpnr-ice40 + icepack, Makefile + pico_ice/Makefile)	Verilog (~15 design .v files: core.v/cpu.v/alu.v/register.v/shift.v/multiply.v/uart/uart_tx.v/uart_rx.v; ice40_cells_sim.v is a vendor sim model, excluded)	Apache-2.0 (LICENSE)	? → 2024-11-17, ?	none
micki0271__maeri	MAERI 0.1: WIP FOSS end-to-end ML CNN accelerator (TensorFlow -> compiler -> nMigen RTL) with a real ULX3S ECP5-85F platform incl. SDRAM controller	ECP5 85F (top.py: from maeri.gateware.platform.ulx3s.ulx3s85f import ULX3S_85F_Platform)	open: nMigen -> yosys+nextpnr-ecp5+ecppack via the custom ULX3S_85F_Platform; a separate sim platform exists for software-only cosimulation (not a second board)	Python/nMigen (77 .py)	none found	? → 2020-12-06, ?	BracketMaster/maeri (per README’s own git clone URL)
mikeakohn__riscv_fpga	RISC-V CPU (forked from Intel 8008 FPGA project) with SPI/UART/IO/speaker-tone peripherals and a Mandelbrot accelerator instruction	iCE40 HX8K (NOT ECP5) - CB132 (--hx8k --package cb132, Makefile default target, pcf=icefun.pcf); also Gowin GW2A-18C (NOT ECP5, NOT iCE40) via tang_nano target (nextpnr-himbaechel, tangnano20k.cst)	open (yosys synth_ice40+nextpnr-ice40+icepack) for iceFUN; open (yosys synth_gowin+nextpnr-himbaechel+gowin_pack) for Tang Nano 20K (Makefile)	Verilog: 12 .v + 1 .vinc (src/); test/ has 13 .asm files for naken_asm assembler (not RTL testbenches)	MIT (LICENSE)	? → 2026-06-26, ?	mikeakohn/intel_8008_fpga (README: forked, memory_bus.v widened to 32-bit + RISC-V decode)
nickmqb__fpga_craft	iCE40 UP5K (iCEBreaker board): FPGA Craft, a voxel/Minecraft-like game with custom 16-bit CPU, ray-tracing GPU (~1Mray/s), N64 gamepad input, VGA output and flash-backed terrain streaming, written in the author’s own Wyre HDL.	iCE40 UP5K (NOT ECP5) - SG48	open (yosys+nextpnr-ice40+icepack, icestorm) fed by author’s custom Wyre-to-Verilog compiler + kasm assembler + bram_swap tool	Wyre (10 .w custom HDL source files, compiled to Verilog); Verilog (1 .v top-level wrapper, hw/top.v); Muon (31 .mu host tooling)	Apache-2.0 (LICENSE + SPDX headers in .w/.v/.pcf files)	? → 2025-10-28, ?	none
nklabs__libnklabs-ulx3s	PicoRV32-based RISC-V SoC running libnklabs CLI firmware, on ULX3S LFE5U-85F	85F (LFE5U-85F-6BG381I per README)	diamond (Lattice Diamond project ulx3s.ldf; diamondc/ddtcmd build+package fw+bitstream; README documents Diamond 3.11 module setup)	Verilog (36 .v: picorv32.v, uart.v, spiflash.v, sdram.v, bus_*), C (101 .c/103 .h firmware)	MIT (fw/libnklabs/LICENSE only; no top-level LICENSE)	? → 2022-08-13, ?	none
no2fpga__no2bootloader	Nitro Bootloader: iCE40 UP5K DFU bootloader (SB_WARMBOOT image-select stub + no2usb/PicoRV32 DFU class core), multi-board (iCEBreaker/bitsy, reDIP-SID, icE1usb, iCEpick, E1 tracer, osmo-amr…)	iCE40 UP5K (NOT ECP5) - sg48, BOARD=icebreaker default (gateware/ice40/Makefile DEVICE/PACKAGE from data/top-.pcf)	open (yosys+nextpnr-ice40+icepack via gateware/build/project-rules.mk - NOT fetched here, see notes); RISC-V riscv-none-elf-gcc for firmware/ (gateware/ice40-stub/README.md)	Verilog (67 .v incl. fetched submodules), C (16 .c, 21 .h firmware/), Python (8, utils/no2bootloader.py, mkmultiboot.py)	repo’s own firmware GPL-3.0-or-later (SPDX header, firmware/usb_desc_dfu.c:5); repo’s own HDL CERN-OHL-P-2.0 / utils MIT (LICENSE.md); submodule gateware/cores/no2usb: HDL CERN-OHL-P-2.0, custom USB stack LGPL-3.0-or-later, tinyusb driver parts MIT (gateware/cores/no2usb/LICENSE.md)	? → 2026-01-29, ?	none
nullobject__riscv-ulx3s	RISC-V (PicoRV32) SoC on ULX3S with OLED display, tile GPU, UART, PRNG and MIDI firmware library	85F (Makefile DEVICE=85k)	open: yosys+nextpnr-ecp5+ecppack via Makefile; riscv32-unknown-elf-gcc toolchain for firmware; Verilator for sim	Verilog (13 .v incl. picorv32.v), C (7, firmware/HAL/MIDI), Assembly (start.S, custom_ops.S), C++ (1 verilator tb)	none found (no LICENSE file; picorv32.v itself is ISC-licensed upstream but not restated here)	? → 2025-07-13, ?	picorv32.v is the vendored PicoRV32 core (Clifford Wolf); board integration is original
nusgreyhats__greybadge25	Greybadge25 (GreyCTF 2025 Badge): RP2350 CircuitPython badge PCB with an onboard ECP5 FPGA running CTF hardware-reversing challenges (AES/DES/SHA256 cores, UART coprocessor) plus OLED/shooting-game bring-up tests.	ECP5 25F (CABGA256, –25k flag in Makefile)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (59 .v)	none found at repo root (no LICENSE/COPYING); firmware/ecp5/uart_coprocessor/src/aes/*.v carry individual OpenCores copyright headers (Rudolf Usselmann, 2000-2002, permissive redistribution clause)	? → 2026-02-05, ?	none
openconcepts-ar__accel2d	accel2d: C-to-Verilog (Silice/CflexHDL) 2D graphics accelerators (line/rect/ellipse fill) on a LiteX VexRiscv SoC’s DRAM bus, with GUI/demo software	ECP5-5G 85F (LFE5UM5G-85F, BG554, default; lambdaconcept_ecpix5.py device=”85F”, litex_boards lambdaconcept_ecpix5 platform, DDR3 MT41K256M16 via ECP5DDRPHY, RGMII via LiteEth). Also ECP5 12F (gsd_orangecrab.py, NOT ECPIX-5) and Xilinx Artix-7 (NOT ECP5: digilent_arty.py)	open (LiteX + yosys/nextpnr-ecp5/ecppack, --toolchain trellis; Lattice Diamond also supported --toolchain diamond, forces a non-5G LFE5U part name for license limits); accelerator RTL generated at build time via external CflexHDL+Silice transpilers (../CflexHDL, not vendored)	Verilog (29 own .v: hand-written tops + Silice-generated accel_*.v), Python (14 own .py: LiteX SoC/board scripts), C/C++ (~30 files: demos, drivers)	AGPL-3.0-only (own C/C++/Python/generated-Verilog, SPDX headers e.g. accel_cores.c, line32.cc, wpu.py, accel_ellipse_fill32.v); lambdaconcept_ecpix5.py itself BSD-2-Clause (litex-boards origin, modified); top-level LICENSE: “most are BSD or Affero 3.0 GPL”	? → 2026-06-09, ?	none (earlier version: openconceptslabs/gpu2d per boards3_survey.md; not a GitHub fork relationship)
osmocom__osmo-e1-hardware	icE1usb / osmo-e1-tracer: E1/T1 telecom interface product family gateware for iCE40 UP5K boards - icE1usb USB-E1 dongle (PicoRV32 SoC), osmo-e1-tracer passive E1 bitstream tracer, shared no2e1 line-interface core (G.702/703/704)	iCE40 UP5K (NOT ECP5) - SG48 package (DEVICE=up5k PACKAGE=sg48, gateware/icE1usb/Makefile and e1-tracer/Makefile)	open (yosys + nextpnr-ice40 + icepack via no2build project-rules.mk submodule)	Verilog (25 .v in gateware/ excl. no2e1; no2e1 core adds 22 .v)	Mixed CERN-OHL-2.0 variants (gateware/README.md: CERN-OHL-S/W/P-2.0 per file header, texts in gateware/doc/LICENSE-*.txt); no LICENSE file at repo root; no2e1 submodule itself is CERN-OHL-W-2.0 (own LICENSE)	? → 2024-11-22, ?	none
pepijndevos__litedhrystone	litedhrystone: runs the Dhrystone benchmark on a LiteX SoC (SERV/PicoRV32/VexRiscv CPU cores) on a ULX3S board, reporting measured DMIPS/MHz	ECP5 85F (make.sh: –device LFE5U-85F)	open (LiteX SoC generator -> trellis toolchain: yosys+nextpnr-ecp5+ecppack, via litex_boards’ external radiona_ulx3s target; no LPF checked into this repo)	none checked in (LiteX-generated gateware); C (6 files, Dhrystone benchmark + demo firmware)	none found	? → 2024-10-30, ?	none (Dhrystone C code adapted from SpinalHDL/NaxSoftware and LiteX’s own demo software, per README)
pietptr__ulx3s-dsp	Clash (Haskell-to-HDL) DSP experiments (FFT, DAC/ADC audio effects) targeting ULX3S	85F (Makefile: nextpnr-ecp5 –85k)	open; detail=Clash compiler -> generated Verilog -> yosys+nextpnr-ecp5+ecppack	Haskell 10 hs (Clash DSP + FFT/audio-effects source), Verilog 1 generated (hdl/Main.topEntity/main.v)	none found	? → 2022-06-17, ?	none
remyciterin__3driscv	3DRiscV: RV32IMA CPU + custom RISC-V GPGPU SoC (TileLink) for ULX3S, boots xv6	85F (–85k in Makefile)	open (yosys+nextpnr-ecp5+ecppack)	Haskell/Blarney (40 .hs), Rust (27), Zig (21), Verilog (14) + submodule UberDDR3: Verilog (84 .v)	MIT (LICENSE); submodule UberDDR3: GPL-3.0 (LICENSE) - license conflict (project MIT, DDR3 controller GPL-3.0)	? → 2026-01-11, ?	shares SDRAM/HDMI/simulation infra with remyciterin__dooom (same author); xv6-rv32/ is a fork of michaelengel/xv6-rv32
remyciterin__adventoffpga	Advent of Code puzzle solutions implemented as Bluespec RISC-V/GPU hardware designs running on ULX3S, plus a DOoOM CPU sim	85F (Makefile: –85k –package CABGA381, also –85k –freq 40 –gui variant)	open: Bluespec (bsc) -> yosys+nextpnr-ecp5+ecppack via root Makefile; nix-shell based dev environment	Bluespec (9 .bsv), Zig (8), C (6), Assembly (2)	Apache-2.0	? → 2026-01-14, ?	includes own other repos as submodules: 3DRiscV, DOoOM, elf_to_hex
rschlaikjer__fpga-3-softcores	fpga-3-softcores: VexRiscv Wishbone SoC demo (“FPGA Soft CPU SoC Demonstration” blog) for iCE40 HX8K - custom peripherals + bare-metal RISC-V firmware	iCE40 HX8K (NOT ECP5) - TQ144 (CMakeLists.txt: FPGA_DEVICE=hx8k FPGA_PACKAGE=tq144:4k, PLACEMENT_FILE=hx4k_pmod.pcf)	open (yosys+nextpnr-ice40+icepack via CMake synth_ice40(), cmake/synthesis_ice40.cmake); verilator for sim/tests; riscv-gnu-toolchain (rv32i) for firmware; faff for programming	Verilog (10 .v in rtl/ + 18 .v vendored: vendor/wb_intercon, vendor/verilog-arbiter submodules + vendor/vexriscv/VexRiscv.v), C++ (7: firmware/ + sim/ + test/ catch2 unit tests), Scala (1, vendor/vexriscv/GenVexRiscv.scala - VexRiscv generator source, not built here)	MIT (LICENSE.md); vendor/catch (Catch2) and vendored VexRiscv.v carry their own upstream licenses; vendor/wb_intercon and vendor/verilog-arbiter are git submodules (upstream licenses not vendored into this repo)	? → 2020-08-23, ?	none (rtl/vendor generated/vendored, see reuse)
rxrbln__picorv32	PicoRV32 fork (rxrbln) adding a PicoSoC ULX3S port: VGA+HDMI, SDRAM, PS/2 keyboard and 1-bit audio DAC on top of the upstream picosoc/hx8kdemo SoC	ECP5 85k (ULX3S v2.0/2.1; picosoc/Makefile: nextpnr-ecp5 --85k --freq 50 --placer heap --lpf ulx3s.lpf) - NEW vs upstream; also iCE40 HX8K (NOT ECP5) CT256 and iCE40 UP5K (NOT ECP5) SG48 inherited unchanged from yosyshq/picorv32 (picosoc/hx8kdemo.v, icebreaker.v)	open (yosys synth_ecp5 -abc2 + nextpnr-ecp5 + ecppack for ulx3s.bit, picosoc/Makefile:109-127); same open iCE40 flow as upstream for hx8kdemo/icebreaker	Verilog (52 .v incl. new ulx3s.v/sdram.v/vga.v/vga2dvid.v/tmds_encoder.v/ps2.v/audio.v), C (34, firmware incl. NEW user.c/utility/), Python (8, unchanged from upstream)	Mixed, no single root license file in this fork: picorv32.v/ps2.v ISC-style header (Clifford Wolf, +Rene Rebe); picosoc/{sdram.v,vga.v} GPL-3.0-or-later (Rene Rebe); picosoc/vga2dvid.v MIT (Mike Field); picosoc/tmds_encoder.v vhd2vl-translated, copyright unchanged (unspecified)	? → 2021-05-12, ?	yosyshq__picorv32 (already catalogued); this row describes only what differs
sangwoojun__ulx3s_bsv	sangwoojun/ulx3s_bsv: Bluespec SystemVerilog library+demos for ULX3S (UART, SDRAM, PLL, float, RV32I core, NN accelerator)	85F (apio init -b ulx3s-85f)	open (bsc Bluespec compiler -> apio: yosys+nextpnr-ecp5+ecppack)	Bluespec (27 .bsv), Verilog (13, mostly bsc-generated), C++ (12, bsim testbench)	none found	? → 2025-03-09, ?	none
saul-rodriguez__ulx3s	Mixed ULX3S FPGA experiments (blink, picoRV32 SoC) plus unrelated 8-bit MCU assembler/C coursework	85F (nextpnr-ecp5 –85k in both Makefiles)	open: yosys+nextpnr-ecp5+ecppack	Verilog (blink 1 file, picoRV32_rom ~10 files) + large unrelated PIC/AVR-style asm+C tree	GPL-3.0 (blink/LICENSE); no top-level license	? → 2021-05-17, ?	none
secworks__cryptkey	CrypTkey: WIP port of the Tillitis TKey RISC-V security SoC (picorv32 + secworks crypto cores) to the ULX3S ECP5-85F, aiming to add CrypTech HSM functions	ECP5 85F (nextpnr-ecp5 –85k –package CABGA381, Makefile)	open (yosys + nextpnr-ecp5 + ecppack, TOOL_PREFIX=/opt/oss-cad-suite/bin)	Verilog (29 files)	BSD-2-Clause (LICENSE)	? → 2025-02-25, ?	none (vendors secworks’ own cores: picorv32, uart, timer, trng, uds; ck1 core)
sefbkn__versa-ecp5-demo	Versa ECP5-5G: dual-port Ethernet PHY passthrough bridge (SGMII/RGMII) with a small RV32I VexRiscv control core for MDIO bring-up and a UART CLI	um5g-45k / LFE5UM5G-45F (Lattice Versa ECP5-5G, CABGA381)	open (yosys+nextpnr-ecp5+ecppack+openFPGALoader) plus Rust riscv32i-unknown-none-elf firmware toolchain	Verilog (31 .v: 30 own + 1 vendored rtl/external/vexriscv/VexRiscv.v), Rust firmware (7 .rs), Go tool (1 .go, crc32_gen.go)	CERN-OHL-S-2.0 (RTL/constraints/sim) + MIT (firmware/tools/docs) per LICENSE and LICENSES/; vendored rtl/external/ keeps its own upstream license	? → 2026-03-11, ?	none
semify-eda__waveform-generator	Generic SystemVerilog waveform generator core (sine/mem stimuli, SPI/pattern drivers) with cocotb testbenches	85F (nextpnr-ecp5 –85k in top Makefile)	open: yosys+nextpnr-ecp5+ecppack (barebones) and LiteX/Migen SoC variant (ulx3s_soc.py)	SystemVerilog (33 .sv), Python (13, incl. LiteX SoC + cocotb testbenches)	Apache-2.0	? → 2022-07-18, ?	none (semify-eda own IP)
seminlim__bluerv32	blueRV32: reference-quality synthesizable RV32I/RV32IM RISC-V processor in Bluespec SystemVerilog, with riscv-arch-test conformance suite and ULX3S synthesis flow	85F (Makefile hardcodes –85k in the nextpnr invocation)	open: bsc (Bluespec compiler) -> yosys(implicit)+nextpnr-ecp5+ecppack via Makefile; extensive Bluesim + riscv-arch-test + differential-vs-spike verification	Bluespec SystemVerilog (11 .bsv), C (1), C++ (2, Bluesim/audit tooling), Python (3, arch-test tooling), Assembly (many .s test/software files)	none found	? → 2026-08-14, ?	none
seth16225__riscv-core-portfolio	RV32IM core portfolio (single-cycle to 6-stage pipelined+cached AXI4-Lite cores) in SystemVerilog, each synthesized for ULX3S ECP5-85F	ECP5 85F (common/make/fpga.mk: nextpnr-ecp5 –85k –package CABGA381)	open: yosys + nextpnr-ecp5 + ecppack via common/make/fpga.mk; ecppll generates the on-chip PLL clock	SystemVerilog (18 .sv), Verilog (26 .v, incl. vendored HDMI/USB helper IP)	MIT (LICENSE, copyright cis5710); riscv-tests/LICENSE and riscv-tests/env/LICENSE are separate upstream licenses	? → 2026-07-28, ?	unclear; LICENSE copyright is “cis5710” (a university course id), suggesting the common/docker/riscv-tests scaffolding derives from that course’s project template
smunaut__had2019-playground	HAD2019 badge playground (original): the Hackaday Supercon 2019 badge USB DFU bootloader (PicoRV32 + early no2usb core), 6 DFU zones incl. cartridge FPGA/IPL/filesystem	ECP5 45F (HAD2019 badge, NOT ULX3S) - DEVICE = 45k (projects/bootloader/Makefile:29)	open (yosys+nextpnr-ecp5+ecpbram+ecppack, build/project-rules.mk); RISC-V riscv-none-embed-gcc for fw/ (fw/Makefile:2)	Verilog (40 .v), C (13 .c, 12 .h fw), Python (4, bin2hex.py/usb_gen_strings.py)	per file: bootloader RTL BSD-3-Clause (LICENSE.bsd), USB core + fw LGPL-3.0-or-later (LICENSE.lgpl3); picorv32.v ISC-style header (rtl/picorv32.v:1-8)	? → 2019-11-13, ?	none (this is the origin repo; emard__had2019-playground forks THIS repo, adapted for ULX3S)
smunaut__ice40-playground	iCEBreaker: collection of iCE40 UP5K IP cores (no2fpga) and example projects (HDMI text overlay, memtest w/ HyperRAM+QSPI-PSRAM+video, HUB75 LED panel, RISC-V+USB, DOOM, USB audio/AMR)	iCE40 UP5K (NOT ECP5) - SG48 package (all projects: DEVICE=up5k PACKAGE=sg48)	open (yosys+nextpnr-ice40+icepack via no2build submodule build/, project-rules.mk)	Verilog (170 .v across cores/ + projects/)	Mixed: CERN-OHL-P-2.0 in most cores//LICENSE (e.g. no2ice40, no2hyperbus) but no2hub75 is CERN-OHL-W-2.0; spi_flash/spi_slave/video headers BSD-3; top LICENSE says MIT/BSD-3/GPLv3/LGPLv3/CERN-OHL per-file, texts in doc/LICENSE-.txt	? → 2023-08-21, ?	none
smunaut__ice40linux	iCEBreaker: Linux-on-RISC-V SoC gateware (VexRiscv CPU via SpinalHDL) for iCE40 UP5K with external HyperRAM or QSPI-PSRAM (32MB) providing full RV32I Linux (buildroot kernel+rootfs)	iCE40 UP5K (NOT ECP5) - SG48 package (DEVICE=up5k PACKAGE=sg48 in gateware/riscv_linux/Makefile)	open (yosys+nextpnr-ice40+icepack via no2build submodule)	Verilog (9 .v in gateware/riscv_linux/rtl, incl. SpinalHDL-generated VexRiscv.v)	CERN-OHL-P-2.0 (SPDX headers in gateware/riscv_linux/rtl/{sysmgr,platform,soc_bram,top}.v); doc/LICENSE-* also carries LGPL-3.0/BSD-2-Clause/MIT texts	? → 2023-02-15, ?	none
smunaut__mch2022-ice40	MCH2022 badge: Sylvain Munaut’s iCE40 UP5K gateware for the badge - HDMI/LCD video demo, psram_load, riscv_doom and tinygpu_doom SoCs; overlaps with badgeteam/mch2022-firmware-ice40	iCE40 UP5K (NOT ECP5) - SG48 package (DEVICE=up5k PACKAGE=sg48, projects/_common/build.mk)	open (yosys -abc9 -device u + nextpnr-ice40 + icepack via no2build project-rules.mk submodule; per-project pre-place SERDES script)	Verilog (57 .v across cores/ + projects/), no SystemVerilog found	Mixed: CERN-OHL-P-2.0 for HDL, MIT for software (top LICENSE statement); texts in doc/LICENSE-CERN-OHL-P-2.0.txt, doc/LICENSE-MIT.txt; per-project LICENSE files	? → 2022-08-02, ?	none (shares no2fpga cores/projects with badgeteam/mch2022-firmware-ice40, catalogued separately; no git fork relationship found in source)
spinalhdl__saxonsoc	SaxonSoc: SpinalHDL SoC framework (BMB bus, VexRiscv Linux/U-Boot); dedicated Radiona ULX3S minimal+SMP kits	12F (minimal, –12k) and 25F (smp, FPGA_KS=25k)	open; SpinalHDL -> Verilog, then yosys+nextpnr-ecp5+ecppack via makefile	Scala/SpinalHDL (99, HDL generator), C (34, BSP/software), Verilog (20, glue/PLL)	MIT	? → 2025-03-16, ?	none
splinedrive__kianriscv	KianV RV32IMA SV32 Linux SoCs (+ noMMU, XV6, ASIC)	85F default (12k..um-85k options)	open (-abc9)	Verilog (111 .v), C + submodule kianv-rv32-linuxcore: Verilog (30 .v)	mixed: ISC (LICENSE.md), Apache-2.0/BSD-2/GPL-2.0 file SPDX; submodule kianv-rv32-linuxcore: Apache-2.0 (LICENSE)	2021-09-25 → 2026-05-30, 354	none
spritetm__hadbadge2019_fpgasoc	Hackaday Supercon 2019 badge: ECP5 SoC (PicoRV32 CPU) with USB2 device, HDMI/VGA video, QPI PSRAM, audio synth/PDM DAC, and a set of badge apps/games (boot+IPL+SDK)	45F (LFE5U-45F-6BG381, –45k –package CABGA381)	open (yosys+nextpnr-ecp5+ecppack+ecpbram, freq 48MHz constraint; docs recommend a prebuilt xobs/ecp5-toolchain)	Verilog (95 .v own) + submodule picorv32: Verilog (41 .v)	multiple per-file licenses: LICENSE.bsd (soc.v), LICENSE.gplv3, LICENSE.lgpl3, LICENSE.mit, LICENSE.beerware, LICENSE.fatfs (ipl/fatfs); no single top-level LICENSE; submodule soc/picorv32: ISC-style (in-file header, Clifford Wolf); soc/picorv32/tests/LICENSE: BSD-3-Clause (Regents of UC, riscv-tests) - yet another license in the mix	? → 2023-11-30, ?	none
stnolting__neorv32	NEORV32 RISC-V microcontroller SoC (VHDL)	n/a	vendor-agnostic (GHDL→Verilog for yosys)	VHDL, C	BSD-3-Clause	2020-06-23 → 2026-09-20, 10828	none
tadeoroboticsgroup__axiomacore-328	AxiomaCore-328: open, binary-compatible ATmega328P clone (8-bit AVR core, 2-stage pipeline) in Verilog-2001, verified against independent oracles, targeting ULX3S ECP5	ECP5 (Makefile: ECP5_DEV/ECP5_PKG vars, synth_ecp5 -top axioma_ulx3s_top); exact device not pinned in the grepped Makefile lines - see rtl/fpga/ecp5/README.md	open (yosys synth_ecp5 + nextpnr-ecp5 + ecppack, Makefile:825-833); also verilator/iverilog/cocotb/sby for verification, plus a legacy/openlane/ Sky130 ASIC flow (phase 6, not started)	Verilog (70 files), Python (23, verification/vectors), C (6, fw/)	Apache-2.0 (LICENSE), with LICENSE-EXCEPTIONS.md third-party inventory	? → 2026-09-26, ?	none (clean-room AVR-ISA-compatible core, not derived from Atmel/Microchip RTL)
tarik-hamedovic__sdr-hls	tarik-hamedovic/SDR-HLS: Master’s-thesis SDR receiver comparing hand-written Verilog RTL vs Amaranth-HLS, targeting ULX3S 85F	LFE5U-85F-6BG381C (per .ldf device field)	diamond (Lattice Diamond + Synplify Pro synthesis, per .ldf projects); Amaranth used to generate some HLS modules	Verilog/SystemVerilog (235+75), Python/Amaranth (93)	none found	? → 2024-10-31, ?	none
theperfectcomputer__mannachip	MannaChip: Bluespec SystemVerilog UART/bus experiment targeting ULX3S (WIP)	85F (–85k in ulx3s_fpga/makefile; IDCODE 0x41113043 = 85F)	open (yosys+nextpnr-ecp5+ecppack; Bluespec via bsc/nix-shell generates the Verilog)	Bluespec (10 .bs, 1 .bsv), C (1, bdpi sim device)	none found	? → 2025-11-21, ?	none
thezoq2__tinytapeout02	TinyTapeout02: reconfigurable cell/routing logic fabric (config-chain programmable cells) written in the Spade HDL, TT02 ASIC shuttle entry with a ULX3S FPGA port	ECP5 LFE5U-85F CABGA381 (ULX3S; swim.toml [pnr] device=LFE5U-85F, package=CABGA381, pin_file=ulx3s_v20.lpf); primary target is the TT02 ASIC shuttle (Sky130, not an FPGA)	open (swim-driven: synth_ecp5, nextpnr-ecp5 architecture=ecp5, ecppack, fujprog upload, per swim.toml); Spade sources are compiled to Verilog by the (unfetched) Spade compiler before synthesis	Verilog (6 .v), SystemVerilog (2 .sv: top.sv, smolfpga/src/spade.sv wrapper), Spade (5 .spade: main/cell/config_chain/routing), Python (11, cocotb tests + tools), TypeScript (bootloader plugin)	none found at repo root (no LICENSE file); smolfpga/ submodule carries its own Apache-2.0 LICENSE	? → 2024-02-13, ?	none
thorkn__vga_clock_1	VGA digital clock display, hardware described in SpinalHDL/Scala and generated to Verilog for ULX3S 85k	85F (ulx3s/Makefile CHIP:=85k)	open: SpinalHDL (sbt run) generates Verilog, then yosys+nextpnr-ecp5+ecppack via ulx3s/Makefile (oss-cad-suite)	Scala/SpinalHDL (5 .scala)	Apache-2.0	? → 2023-06-02, ?	none
thorkn__vga_pong	Pong game with VGA output, SpinalHDL/Scala generating Verilog for ULX3S 85k (sibling project to vga_clock_1)	85F (ulx3s/Makefile CHIP:=85k)	open: SpinalHDL (sbt run) generates Verilog, then yosys+nextpnr-ecp5+ecppack via ulx3s/Makefile (oss-cad-suite)	Scala/SpinalHDL (5 .scala), Verilog (2 .v: generated VgaPong.v checked into both spinalHDL/ and ulx3s/)	GPL-3.0	? → 2023-11-27, ?	shares SpinalHDL scaffolding with thorkn/vga_clock_1 (same author, same pattern)
tinyvision-ai-inc__pico-ice-sdk	pico-ice / pico2-ice: RP2040/RP2350 C SDK for the onboard iCE40 UP5K FPGA, incl. small Verilog I2C-target core and ~19 yosys/nextpnr-ice40 example FPGA projects (blinky, UART echo, I2C 7-seg counter).	iCE40 UP5K (NOT ECP5) - SG48	open (yosys+nextpnr-ice40+icepack, apio wrapper for some examples); RP2040/RP2350 host side uses pico-sdk/CMake	Verilog (14 .v), SystemVerilog (6 .sv)	MIT, LICENSE.md, Copyright (c) 2024 tinyVision.ai; pico_ice.pcf also carries SPDX MIT header	? → 2026-03-06, ?	none
tom7980__ulxws	Custom RISC-V pipeline core RTL + verilator testbenches ("workspace for playing with the ulx3s")	unknown	n/a (verilator simulation only)	Verilog, ~24 files (components/, riscv/) + C++ verilator testbenches	none found	? → 2026-04-04, ?	none
tucanae47__litex_etpu	litex_etpu: VexRiscv+LiteX SoC on ULX3S ECP5-85F with a small systolic-array eTPU (NPU) on Wishbone, replicating a Skywater130 ASIC design	ECP5 85F (etpu_soc.py: device=”LFE5U-85F” default and –device arg)	open: LiteX/Migen -> yosys+nextpnr-ecp5+ecppack via the Trellis LiteX backend	Python/Migen (LiteX SoC), Verilog (3 .v: edu_tpu.v, npu_wb.v, sysa_pe.v)	none found at repo root; design/etpu/npu_wb.v carries its own header: CERN-OHL-P-2.0 (Camilo Soto)	? → 2022-12-23, ?	design/etpu ported from tucanae47/etpu (Caravel/Skywater130 ASIC project, per README)
ultraembedded__ecpix-5	ECPiX-5: RISC-V TCM SoC with AXI4 interconnect and IT6613-based HDMI/DVI framebuffer output	unknown (no nextpnr device flag in source)	unknown (no build script in source; only prebuilt bitstream/fpga.bit included)	Verilog (18 .v own), SystemVerilog (1 .sv own: ecp5pll), C (2 .c own drivers) + submodule core_soc: Verilog (12 .v), C (2 .c, 7 .h) + submodule dbg_bridge: Verilog (3 .v), Python (7 .py) + submodule riscv: Verilog (43 .v), C++ (11 .cpp), headers (21 .h)	none found (no LICENSE file in own repo, README states none); submodule src/core_soc: GPL-2.0 (LICENSE); submodule src/dbg_bridge: LGPL-2.1 (LICENSE); submodule src/riscv: BSD-style (LICENSE, ultraembedded) - three different licenses, none matching the top repo’s none-found status	? → 2020-07-05, ?	none
ulx3s__hazard3	Hazard3 RV32IMACZb* CPU: ULX3S/ULX4M-LD fork with dedicated build docs, incl. Hazard3-Doom validation	ULX3S 85F (–85k; 12F unsupported, BRAM too small); ULX4M-LD 85F (–um-85k –speed 8, LFE5UM-85F)	open: yosys+nextpnr-ecp5+ecppack	Verilog (core hdl/, ~15 files) + C (SoC firmware, example_soc/) + submodule libfpga: Verilog (57 .v)	Apache-2.0; submodule example_soc/libfpga: WTFPL (License) - differs from repo Apache-2.0	? → 2026-09-05, ?	Wren6991/Hazard3 (upstream, already cataloged as wren6991__hazard3)
ulx3s__hazard3-doom	ulx3s/Hazard3-Doom: Doom (DoomGeneric) running on the Hazard3 RISC-V core, for ULX3S (12F/85F) and ULX4M-LD	ULX3S 12F and 85F, plus ULX4M-LD	open (yosys+nextpnr-ecp5+ecppack, per .github/workflows/fpga-builds.yml CI)	Verilog (48 in this repo; Hazard3 core itself lives in an external submodule, not vendored here)	multi-license (CERN-OHL-W-2.0 for hw/gateware; per-file SPDX for software; see LICENSES/)	? → 2026-09-21, ?	uses ulx3s/Hazard3 (ulx-doom branch) as a pinned submodule; explicitly separate from upstream Wren6991/Hazard3
vladov3000__ulx3s	Custom small CPU + DVI video SoC on ULX3S: hand-rolled assembler/simulator toolchain (C/C++) plus SystemVerilog RTL (Cpu, Memory, Dvi, TmdsEncoder), driven by a Python build script	85F (build.py hardcodes nextpnr-ecp5 –85k)	open: yosys+nextpnr-ecp5+ecppack via build.py; also has a from-scratch cxxrtl-based C++ simulator for the design	SystemVerilog (7 .sv), C (2, assembler), C++ (1, cxxrtl-based simulator), Python (1, build.py orchestration)	none found	? → 2026-03-15, ?	none
wren6991__hazard3	Hazard3: 3-stage RV32IMACZb* core with debug, example_soc synthesizable for ULX3S	85F (DEVICE=um5g-85k, ECP5-5G silicon variant)	open; yosys+nextpnr-ecp5 via synth_ecp5.mk; ujprog program/flash	Verilog (49 .v), C (88, firmware/tests)	Apache-2.0 (root LICENSE)	? → 2026-03-12, ?	none
wren6991__hazard3-swd-soc	Example SoC: Hazard3 RISC-V core + OpenDAP SWD debug port + SRAM/UART/timer	85F (README: “ECP5-85k FPGA”; Makefile DEVICE=um5g-85k)	open: yosys+nextpnr-ecp5+ecppack via synth/Makefile	Verilog (3 .v top-level) + submodule lib/libfpga: Verilog (65 .v), lib/opendap: Verilog (9 .v)	Apache-2.0; submodule lib/libfpga: WTFPL (License); submodule lib/opendap: CC0-1.0 (LICENSE) - three different licenses in one project	? → 2023-04-20, ?	none; integrates author’s own Hazard3 and OpenDAP repos as submodules
wren6991__riscboy	RISCBoy: portable games console SoC - Hazard5 RV32IMC CPU, PPU graphics pipeline, AHB-Lite bus fabric, UART/GPIO; has a real ULX3S target	ECP5 85F (DEVICE=um5g-85k PACKAGE=CABGA381, synth/ULX3S.mk, include $(SCRIPTS)/synth_ecp5.mk) - real ULX3S target, 25 MHz osc per synth/riscboy_ulx3s.lpf (“FREQUENCY PORT clk_osc 25 MHZ”); also iCE40 HX8K (NOT ECP5) - CT256 (synth/HX8k-EVN.mk, DEVICE=hx8k PACKAGE=ct256, HX8k-EVN board, --freq 48); also iCEBreaker (UP5K, riscboy_fpga_icebreaker.v)	open; ECP5 target uses yosys+nextpnr-ecp5+ecppack via synth/synth_ecp5.mk (in the unfetched scripts submodule) + ujprog for program/flash; HX8k-EVN uses yosys+nextpnr-ice40+icepack via synth_ice40.mk, iceprog	Verilog (117 .v under hdl/, incl. 16 .v in hdl/hazard5 and 66 in hdl/libfpga); C (software/apps, bootloader)	WTFPL-style “DO WHAT THE FUCK YOU WANT TO AND DON’T BLAME US PUBLIC LICENSE Version 3” (no SPDX id; header in hdl/riscboy_core/riscboy_core.v, hdl/hazard5/License, hdl/libfpga/License, copyright Luke Wren 2018/2020)	? → 2025-12-01, ?	none (hdl/hazard5 and hdl/libfpga are the author’s own separate repos, fetched as gateware submodules; test/execution/riscv_compliance, test/riscv-formal and top-level scripts are unfetched submodules)
x653__xv6-riscv-fpga	xv6-riscv-fpga: from-scratch RV32IA_Zicsr RISC-V CPU (soc.v/rv32.v/clint.v/plic.v/uart.v/spi.v/sram.v) in Verilog, boots MIT xv6 UNIX from SD card, all-FOSS toolchain	iCE40 HX8K (NOT ECP5) - CT256 package (nextpnr-ice40 --hx8k --package ct256 --pcf ice40hx8k_evb.pcf, fpga/Makefile)	open (oss-cad-suite: yosys+nextpnr-ice40+icepack, TOOLPREFIX=/opt/oss-cad-suite/bin/); iceprogduino for upload via Olimexino 32u4 programmer	Verilog (11 .v, fpga/); C (bootloader fpga/boot/, xv6-riscv/ kernel+userland); Python (1, lsb2msb.py); no HDL in cube/ (OpenSCAD) or lisp/ (C)	MIT-style (LICENSE file, standard MIT permission text, Copyright 2023 Michael Schröder, no SPDX header); xv6-riscv/LICENSE separately covers the vendored MIT xv6 kernel (Copyright MIT)	? → 2023-03-05, ?	none (CPU/SoC RTL is original; xv6-riscv/ is a vendored/ported copy of MIT’s xv6-riscv, Copyright 2006-2022 Kaashoek/Morris/Cox)
yope__cpuv2	Simple from-scratch 32-bit CPU SoC on ULX3S with HDMI video, UART, and an experimental 10BASE-T Ethernet MAC/PHY (TX-only)	85F (Makefile nextpnr-ecp5 –85k)	open: yosys(+cpuv2.ys)+nextpnr-ecp5+ecppack via Makefile	Verilog (16 .v), Python (3: assemble.py assembler + sim.py/simtop.py cocotb-style sim)	none found	? → 2021-03-17, ?	none
yosyshq__picorv32	PicoRV32: size-optimized RISC-V (RV32IMC/E) CPU core, no longer under active development	iCE40 HX8K (NOT ECP5) - CT256 (nextpnr-ice40 --hx8k --package ct256, picosoc/Makefile:26); also iCE40 UP5K (NOT ECP5) - SG48 (--up5k --package sg48, picosoc/Makefile:72, icebreaker.v); also targets Xilinx 7-series (scripts/vivado/.xdc/.tcl) and Intel/Altera (scripts/quartus/.qsf/.sdc), both proprietary flows, generic system.v not board-pinned	open (yosys+nextpnr-ice40+icepack) for picosoc hx8kdemo/icebreaker; scripts/icestorm has a 3rd generic iCE40 example; scripts/vivado and scripts/quartus use proprietary Vivado/Quartus flows for area/speed benchmarking (no specific board)	Verilog (41 .v; picorv32.v core + picosoc/, scripts/, tests/.S asm)	ISC (COPYING)	? → 2026-09-07, ?	none
zipcpu__icozip	ICO Zip: ZipCPU demo SoC for the ICO board, AutoFPGA-generated, runs a tic-tac-toe (tttt) firmware demo	iCE40 HX8K (NOT ECP5) - CT256 package (nextpnr-ice40 –hx8k –package ct256 –freq 50, rtl/icozip/Makefile); older arachne-pnr -P ct256 recipe also present but commented out	open (yosys+nextpnr-ice40+icepack, rtl/icozip/Makefile); AutoFPGA generates auto.mk/board.h from auto-data/*.txt; verilator for simulation build	Verilog (98 .v total, incl. rtl/icozip/cpu/ ZipCPU core + wbubus), C/C++ (72, sw/host + sim/verilated models)	GPL-3.0 (per-file headers, e.g. rtl/icozip/Makefile, Gisselquist Technology LLC; no top-level LICENSE file)	? → 2021-05-05, ?	none (vendors ZipCPU core in rtl/icozip/cpu/, AutoFPGA-generated glue)
zipotron__neorv32-complex-setups	NEORV32 RISC-V SoC setups with extra hardware (SDRAM wishbone bridge) for the ULX3S	unknown (neorv32/ submodule – which holds the ULX3S board osflow/constraints – is not fetched in this clone; synthetize.sh calls neorv32’s own make with BOARD=ULX3S)	open; synthetize.sh drives neorv32/setups/osflow (yosys+nextpnr-ecp5+ecppack), but that Makefile lives in the unfetched submodule	VHDL (4, wishbone SDRAM bridge + top override), SystemVerilog (1, ecp5pll.sv)	none found	? → 2021-11-28, ?	wraps zipotron’s fork of stnolting/neorv32 (git submodule, not fetched in this shallow clone); overrides board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd
zipotron__ziposoc	Small RISC-V (ZipCPU-style) SoC for ULX3S ECP5	85F (DEVICE ?= 85k)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (14 .v)	none found	? → 2022-08-10, ?	none noted (zipocpu.v resembles a simplified ZipCPU derivative; no attribution given)
zyedidia__riscinator	Riscinator: 3-stage RV32I pipeline SoC in Chisel with SRAM/UART/GPIO/timer, synthesizable for OrangeCrab 25F or ULX3S 85F	ECP5 85F (ULX3S, README.md:60-61, tech/ulx3s/ulx3s_v20.lpf); also ECP5 25F (OrangeCrab, tech/orangecrab/orangecrab.lpf) - both targets are ECP5, no non-ECP5 board	open (oss-cad-suite: yosys+nextpnr-ecp5, README ‘Dependencies’); Chisel/firtool generates the Verilog; knit build tool	Scala (23, Chisel core/SoC), Verilog (2, tech/ top wrappers)	MIT (LICENSE)	? → 2023-04-13, ?	none

Retro computers, consoles and arcade

Repo	What	FPGA	Toolchain	HDL	License	Active (first → last, commits)	Fork / preferred copy
abhinavputhran__ttysky-raycast-test	raycaster: Wolfenstein-style DDA raycasting maze renderer, 640x480 VGA @25MHz, built primarily as a Tiny Tapeout (tt_um) Sky130 ASIC design	NOT ECP5 primarily: Tiny Tapeout tt_um_abhi_raycast.sv targets the ttsky25b shuttle (Sky130 ASIC, per gds/docs/test/fpga CI badges); no ECP5-specific top-level or constraints exist in this clone despite the README’s ‘Running on FPGA (ULX3S)’ section	Tiny Tapeout GDS flow (CI-only, not in this clone) for the ASIC; cocotb+icarus for RTL/GL simulation (test/Makefile)	SystemVerilog (7 .sv)	Apache-2.0 (LICENSE)	? → 2026-05-01, ?	none
alangarf__apple-one	Multi-board (Icepi Zero ECP5, iCE40 HX8K/UP5K, Xilinx Spartan-3E, Altera Cyclone, Gowin Tang Primer 25K): Apple 1 replica in Verilog (6502 core, WozMon/Basic ROM, UART/VGA+PS2); upstream of lawrie/apple-one’s ULX3S/ULX4M port	Multi-vendor (NOT ECP5-only): iCE40 HX8K/UP5K, ECP5 25F (Icepi Zero, CABGA256, nextpnr-ecp5 –25k), Xilinx Spartan-3E, Altera/Intel Cyclone, Gowin GW5A-25A (Tang Primer 25K)	both/mixed per board: open (yosys+nextpnr-ice40/ecp5+icepack/ecppack) for iCE40/ECP5 boards; Xilinx ISE WebPack (Spartan-3E); Altera Quartus (DE0/DE0CV); Gowin IDE (Tang Primer 25K, proprietary)	Verilog (44 .v), SystemVerilog (2 .sv, Icepi Zero HDMI: tmds_encoder.sv, vga2tmds.sv)	Apache-2.0 (LICENSE, root)	? → 2025-09-22, ?	none
badgeteam__mch2022-firmware-ice40	MCH2022 badge: iCE40 UP5K gateware collection - beginner demos (blink/RGB/Buttons/Forth/Snake/Ledcomm) plus RISC-V Playground and riscv_doom SoC cores; official badge-team firmware repo	iCE40 UP5K (NOT ECP5) - SG48 package (DEVICE=up5k PACKAGE=sg48, projects/_common/build.mk)	open (yosys + nextpnr-ice40 + icepack via no2build project-rules.mk submodule)	Verilog (82 .v across cores/ + projects/), no SystemVerilog found	Mixed: CERN-OHL-P-2.0 for HDL, MIT for software (top LICENSE statement); texts in doc/LICENSE-CERN-OHL-P-2.0.txt, doc/LICENSE-MIT.txt; per-project LICENSE files (e.g. cores/lcd/LICENSE)	? → 2022-11-14, ?	none (shares no2fpga cores/projects with smunaut/mch2022-ice40, catalogued separately; no git fork relationship found in source)
basman74__oberon_sdram	Project Oberon RISC5 + SDRAM cache controller, Lattice Diamond project for the FleaFPGA Ohm/2v4 board (upstream reworked by emard/oberon for ULX3S)	ECP5 (FleaFPGA Ohm A3 / FleaFPGA 2v4 board, not ULX3S) — exact LFE5U part not visible without extracting the archive; impl1/ECP5_FLASHROM.xcf and impl1/ECP5_SRAM.xcf (JTAG programming scripts) and the .vme files confirm ECP5 family	diamond (Lattice Diamond project bundle: Oberon_Ohm_SDRAM.ldf + impl1/ synthesis/PAR reports and a committed bitstream impl1/Oberon_SDRAM_impl1.bit; zipped, not extracted per read-only rule)	Verilog (~35 .v files listed inside the zip via unzip -l, several are Diamond-generated IP wrapper pairs [cache/dcm/vqueue/ioip x2-3 each]; core design files: RISC5.v, sdram.v, cache_controller.v, PS2.v, SPI.v, RS232R.v/RS232T.v, Divider.v, FPAdder.v/FPDivider.v/FPMultiplier.v, MouseM.v, PROM.v, hdmi_ioip.v) + 1 .vhd (.Real.Math.vhd)	none found (no LICENSE/README inside the zip listing)	? → 2018-03-12, ?	none (this is the upstream; emard__oberon’s catalogue row states it is a “rework of Basman74/Oberon_SDRAM”)
cheyao__nes_ecp5	NES (MiST-derived core) for ULX3S/ULX4M/icepi-zero via open toolchain, with ESP32 SD-card OSD loader	25F default (12/25/45/85 selectable; um-45 = ULX4M)	open: yosys+ghdl/ghdl-yosys-plugin+nextpnr-ecp5+ecppack	Verilog (30), SystemVerilog (18, incl. mappers/), VHDL (7, t65/ 6502 core)	none found	? → 2025-07-27, ?	emard__nes_ecp5 lineage (also see machdyne__nes_ecp5); MiST NES core originally by Sorgelig et al.
cheyao__oberon	Project Oberon (RISC/Oberon OS) core ported across multiple Lattice boards, primarily targeting Icepi Zero with ULX3S as the original base	12F/45F/85F all present: Diamond project.ldf explicitly sets device=”LFE5U-12F-6BG381C”; scripts/diamond_main.mk selects MASK_FILE LFE5U-45F.msk (x3) or LFE5U-85F.msk depending on target; icepi-zero Makefile uses nextpnr-ecp5 –25k (25F, non-ULX3S board)	both: open yosys+nextpnr-ecp5+ecppack (proj/ trellis path, trellis_main.mk) AND Lattice Diamond (scripts/project.ldf, diamond_main.mk, diamondc via .xcf scripts)	Verilog (39 .v), Python (8), VHDL (3)	none found	? → 2026-06-23, ?	explicitly forked from emard/oberon (README: “Ulx3s’s https://github.com/emard/oberon ported over and slightly reworked”)
cheyao__sega-sms	Sega Master System core; README still says ‘for the Ulx3s board’ but current tree only builds for Machdyne icepi-zero	unknown for ULX3S (icepi-zero build only)	open: yosys+nextpnr-ecp5+ecppack (icepi-zero/Makefile)	Verilog (src/, ~15 files) incl. Z80 core (tv80)	none found	? → 2025-09-15, ?	none listed (shares Z80/SMS lineage with danodus__ulx3s_sms/lawrie__ulx3s_sms family)
chriscamacho__yazsof	YAZSOF: Z80 (tv80) SoC, UART, 20x15 DVI text, HEX loader monitor	45F	open	Verilog	MIT (tv80 LGPL-style headers)	2019-12-01 → 2019-12-02, 5	none (Z80 from galaksija)
chrislikescisco__nes-fpga	Standalone NES PPU (2C02) register/timing model in SystemVerilog plus an NES-palette-to-RGB LUT; no CPU, no APU, no full system	unknown/none present (README-claimed only: ULX3S 85K = ECP5 LFE5U-85F, Colorlight i5 = ECP5 25F)	unknown (no build files present at all)	SystemVerilog (3: ppu.sv, ppu_tb.sv, rgb_converter.sv)	none found	? → 2026-04-14, ?	none
cliffordwolf__icotools	icotools: IcoBoard toolset - icoprog programmer, icosoc PicoRV32 SoC generator, example designs (blinky, icezero), MachXO2 aux-FPGA programmer	iCE40 HX8K (NOT ECP5) - default ct256 package (arachne-pnr -d 8k, no -P, examples/blinky/Makefile); examples/icezero uses TQ144:4k package (arachne-pnr -d 8k -P tq144:4k); mxoprog/ targets a MachXO2 auxiliary FPGA (JTAG/SVF programmer, not iCE40)	open (yosys+arachne-pnr+icepack+icetime); icosoc/icosoc.py (Python) auto-generates Makefile/pcf fragments per example	Verilog (19 .v), Python (12, icosoc.py generator + prog scripts), C (19, icoprog/mxoprog host tools + picorv32 firmware)	none found (no LICENSE/COPYING at any depth or in README)	? → 2019-11-10, ?	none
cube1us__ibm1410fpga	IBM1410FPGA: gate-level VHDL replica of the IBM 1410/1401 Data Processing System, built module-by-module from IBM SMS ALDs, each with its own testbench	Xilinx (NOT ECP5) - exact device unknown (IntegrationTest5_fpga.vhdl: “library UNISIM; use UNISIM.vcomponents.all;”; VHDL/udp/EthernetVerilogTest.xpr Vivado project; no XDC/UCF device string found in the clone to confirm the part)	Xilinx Vivado (proprietary; UNISIM library use + .xpr project; no Makefile/open-source flow found)	VHDL (1319 .vhdl files: ~881 gate-level ALD modules + 438 *_tb.vhdl per-module testbenches), Verilog (2: VHDL/udp/udp_fpga.v, udp_fpga_core.v)	none found (no LICENSE/COPYING/README at any depth in the clone)	? → 2026-08-21, ?	none
dan-rodrigues__icestation-32	icestation-32: compact retro FPGA game console, secondary port to ULX3S (primary target is iCE40 UP5K/iCEBreaker)	85F (Makefile ECP5_SIZE=85; README notes 45F/85F needed for 128KB BRAM, 25F possible with external RAM)	open; yosys synth_ecp5 + nextpnr-ecp5 + ecppack for ULX3S; nextpnr-ice40 for the primary UP5K path	Verilog (62 .v), C (24) + C++ (15, firmware/tools)	MIT	? → 2021-08-07, ?	none
danodus__msx_fpga	MSX 8-bit home computer reimplementation (Z80 CPU + video/PS2/ROM) for ULX3S and GMA1EVB (GateMate) boards	85F (DEVICE?=85k in ulx3s/Makefile)	open; yosys synth_ecp5, nextpnr-ecp5 –85k –package CABGA381, ecppack; fujprog to flash	Verilog (19 .v: msx.v, Z80/tv80_core.v core, video.v, keyboard.v, ps2.v)	MIT	? → 2025-05-03, ?	none
danodus__ulx3s_68k	68000 CPU experiments (fx68k core) on ULX3S, with OSD loader and GCC/asm test ROMs	85F (DEVICE ?= 85k)	open: yosys+nextpnr-ecp5+ecppack	Verilog/SystemVerilog (fx68k core + jt89 PSG + peripherals, ~30 files)	none found	? → 2020-07-13, ?	lawrie__ulx3s_68k (already cataloged, identical git commit hash - unmodified fork)
danodus__ulx3s_sms	Sega Master System core for ULX3S and ULX4M, HDMI/VGA out, ESP32 OSD ROM loader	ULX3S 85F (DEVICE ?= 85k); ULX4M via src/ulx4m_sms.v + ulx4m/ulx4m_v002.lpf	open: yosys+nextpnr-ecp5+ecppack	Verilog (src/, ~15 files incl. tv80 Z80 core)	none found	? → 2023-05-19, ?	lawrie__ulx3s_sms (already cataloged, identical git commit hash); shares Z80/SMS lineage with cheyao__sega-sms
doctorwkt__verilog_tic-tac-toe	Tic Tac Toe (Warren Toomey upstream) UART + HDMI	45F	open	Verilog	GPL-3.0	2018-11-27 → 2026-01-14, 23	none (upstream)
emard__apple-one	Apple 1 (alangarf apple-one) with ULX3S HDMI/PS2	25F	open	Verilog	Apache-2.0	2018-01-02 → 2019-12-31, 189	fork via lawrie; lawrie copy more complete
emard__apple2fpga	Apple II+ (Stephen Edwards apple2fpga) ULX3S port	85F default (25/45/85)	diamond (trellis mk present, unused)	VHDL, Verilog (OSD), Python (ESP32)	none found (Apple ROMs Apple copyright; cpu6502 P. Wendrich)	2019-12-18 → 2024-03-28, 130	upstream S. Edwards; best ULX3S copy (v31 support, 2024)
emard__cortex	Powertran Cortex (TMS9995-based 1983 home computer) with ancient Unix, ported to ULX3S	12F (make.sh: nextpnr-ecp5 –12k; comment says “assumes 25F device” but flag targets 12F – inconsistent)	open; yosys+nextpnr-ecp5+ecppack (make.sh)	Verilog (9 .v)	none found	? → 2020-08-19, ?	fork of mini-cortex FPGA project (ancient Unix on TMS99xx)
emard__fpga_snake_game	fpga_snake_game: classic Snake game, VGA output converted to HDMI/DVI (GPDI); multi-board (ULX3S, MiniSpartan6+, FFM boards)	ECP5 12F (FPGA_SIZE=12, proj/lattice/ulx3s/makefile.trellis) and 45F (DDTCMD -dev LFE5U-45F, proj/lattice/snake_ulx3s_hdmi/Makefile); also Xilinx Spartan6/Artix7 (proj/xilinx/scarab, ffm-a7100-ise) and Altera Cyclone5 (proj/altera/ffm-c5a4-sd-lcse) - NOT ECP5, other proj/ subdirs	both: open (yosys+nextpnr-ecp5+ecppack via scripts/trellis_main.mk) and Lattice Diamond (snake_ulx3s_hdmi/Makefile drives diamondc+ddtcmd); Xilinx ISE and Altera Quartus for the non-ECP5 targets	VHDL (29 files), Verilog (4 files)	none found at repo root; dvi/tmds_encoder.vhd, rtl_emard/vga/hdmi/*.vhd and rtl_emard/vga/altera/cyclone4/serializer.vhd carry LGPL-2.1+ header comments (Emard boilerplate)	? → 2019-05-06, ?	none
emard__galaksija	Galaksija (1983 Yugoslav Z80 computer), tv80	12F	both (trellis default; diamond flash broken)	Verilog, VHDL (dvi)	none found (tv80 MIT-style headers)	2018-06-12 → 2025-07-06, 62	from mmicko fpga101-workshop; upstream + newest (2025)
emard__jupiter_ace	Jupiter Ace (Z80 Forth computer), HDMI + PS/2	25F	open	Verilog	none found (tv80 MIT-style)	2020-01-08 → 2020-01-11, 8	fork of lawrie/jupiter_ace
emard__minimig_ecs	Minimig ECS: Amiga 500 OCS/ECS from FleaFPGA Ohm	25F (25/45)	diamond (trellis mk not default)	VHDL, Verilog	GPL-3.0-or-later (headers; no LICENSE file)	2018-02-06 → 2022-05-17, 140	derived from FleaFPGA Ohm Diamond project zip
emard__nes_ecp5	NES (MiST core) on ULX3S: DVI, SDRAM, ESP32 OSD, USB gamepads	12F default (12/25/45/85)	open (yosys + ghdl plugin)	Verilog, SystemVerilog, VHDL (T65)	GPL (nes.v header; no COPYING)	2019-11-23 → 2020-11-12, 144	fork of ironsteel/nes_ecp5 + Nov-2020 fixes (more features)
emard__next186	Next186: 80186 PC SoC (FreeDOS, VGA, OPL3) from FleaFPGA Ohm	85F	diamond	Verilog (in zip), VHDL (dvi)	custom permissive (N. Dumitrache)	2018-02-03 → 2020-01-03, 33	fork of basman74__next186 + ULX3S port (only ULX3S copy)
emard__oberon	Project Oberon RISC5 (Wirth) 1024x768, SDRAM cache, SD disk	85F trellis / 12F diamond	both (trellis default)	Verilog, SystemVerilog, VHDL, Python	no repo LICENSE; per file: Project Oberon permissive notice in RISC5 files, hdl/sdram.v + cache_controller.v LGPL-2.1-or-later (Next186/opencores header)	2019-04-23 → 2020-12-06, 110	rework of Basman74/Oberon_SDRAM; proj_pnru alt top
emard__papilio-arcade	Papilio Arcade: Pac-Man, Scramble, Frogger ULX3S ports (HDMI, OSD, USB joystick, SPDIF)	12F/25F/45F/85F (per-size projects)	diamond	VHDL (240 .vhd)	mixed: MikeJ BSD-style (pacman/scramble), GPL-3.0 (A2601); arcade ROMs copyrighted	2011-07-14 → 2018-11-30, 134	fork of GadgetFactory Papilio-Arcade (only ULX3S copy)
emard__snes_mister_ulx3s	SNES (MiSTer core) ULX3S port, emard’s branch: merged from gatecat’s work then extended with ESP32/OSD	85F	open: yosys+ghdl+nextpnr-ecp5+trellis	VHDL/Verilog mixed (same core as gatecat’s fork)	GPL-3.0	? → 2020-10-25, ?	srg320/SNES_MiSTer via gatecat__snes_mister_ulx3s (merge commit ‘Merge remote-tracking branch upstream/ulx3s’)
emard__ti99_2	TI-99/2 ULX3S build + ESP32 HEXBUS server (overlay of pnru)	12F default	open	Verilog, SV, Python	none found (pnru public domain)	2019-11-29 → 2020-06-30, 14	companion of pnru__ti99
emard__uk101onfpga	UK101 + ORAO (Yugoslav) on FPGA, DVI	12F (orao), 45F (uk101)	diamond	VHDL, Verilog, Python (ESP32)	none found (Grant Searle non-commercial terms; T65 BSD-style)	2015-06-02 → 2020-05-05, 235	fork of Grant Searle UK101onFPGA
emard__ulx3s_c64	emard/ulx3s_c64: Commodore 64 core for ULX3S, ported from MiSTer C64_MiSTer to open-source tools	12F default	both	VHDL (48), Verilog (11)	none found	? → 2024-04-04, ?	MiSTer-devel/C64_MiSTer (ported)
emard__ulx3s_galaksija	emard/ulx3s_galaksija: Galaksija Z80 retro-computer core ported to ULX3S (from mmicko/fpga101-workshop)	12F default; FPGA_SIZE var supports 12/25/45/85	both: open (yosys+nextpnr-ecp5+ecppack via makefile.trellis) and diamond (makefile.diamond)	Verilog (~19 files), VHDL (3)	none found	? → 2025-07-06, ?	none (port of mmicko/fpga101-workshop)
emard__ulx3s_vic_20	Minimal Commodore VIC-20 core for ULX3S	85F (DEVICE ?= 85k)	open: yosys+nextpnr-ecp5+ecppack	Verilog (src/, ~15 files) + SystemVerilog (ecp5pll.sv)	none found	? → 2023-01-22, ?	lawrie__ulx3s_vic_20 (already cataloged; emard’s fork pushed 991 days after forking)
emard__verilog_tic-tac-toe	Tic Tac Toe, EMARD DVI port	25k default (file named 45F)	both (mainly open)	Verilog	GPL-3.0	2018-11-27 → 2018-12-05, 28	fork of DoctorWkt (original DVI port)
emard__vhdl_c64_c1541_sd	Commodore 64 + 1541 disk emulation (FPGA64/DarFPGA) adapted for HDMI output on the ULX3S; author states it does not work	45F (proj/lattice/ulx3s/Makefile: DDTCMD -dev LFE5U-45F)	diamond; Lattice Diamond diamondc project flow (proj/lattice/ulx3s/Makefile), no open-toolchain path for the ULX3S target	VHDL (56 .vhd, dominant: C64/1541/SID/VIC-II cores), some Verilog (1)	none found	? → 2018-01-30, ?	adaptation of DarFPGA’s FPGA64_027 + 1541_SD (darfpga.blogspot.fr), Copyright 2005-2008 Peter Wendrich; multi-board repo (de0_nano, de1, de2 variants also present)
emard__vhdl_phoenix	Phoenix (Amstar) arcade, DarFPGA core, HDMI/SPDIF/OSD/USB joystick	25F default	diamond	VHDL, Verilog (usb)	none found (“educational use only”; ROMs user-extracted)	2016-10-02 → 2019-11-27, 140	from DarFPGA vhdl_phoenix
emeb__up5k_vga	iCE40 UP5K custom up5k_usb board: complete 65C02 home computer with 800x600 VGA text/graphics, PS/2 keyboard, UART, 4-voice sigma-delta audio, SPI-flash-loaded OSI BASIC interpreter and C’MON monitor.	iCE40 UP5K (NOT ECP5) - package not pinned in Makefile (pcf pin numbers <=48 consistent with SG48)	open (yosys+nextpnr-ice40+icepack, icestorm)	Verilog (17 .v in src/+icestorm, plus verilog-6502 submodule cpu_65c02.v/ALU.v)	MIT (LICENSE, repo root, Copyright 2019 Eric Brombaugh)	? → 2019-06-11, ?	emeb/up5k_basic (README: VGA+65C02 successor to author’s earlier NTSC-composite up5k_basic project)
evansm7__arcdvi	ArcDVI: passive digital (DVI) video tap for the Acorn Archimedes VIDC chip, reconstructing video for modern monitors	not found via flag grep in top Makefile (toolchain keyword present but no –Nk match; README/PCB context implies a mid-size ECP5, likely 25F or 45F, unconfirmed)	open: yosys+nextpnr-ecp5+ecppack via root Makefile	Verilog (12 .v), C (8, firmware/), header/other (8 .h)	none found	? → 2021-12-04, ?	none (own design, companion adapter PCB in a separate evansm7/ArcDVI-PCB repo)
felipesanches__anotherworld_fpga	Another World bytecode VM in hardware, HDMI (WIP)	12F	open (emard trellis mk)	Verilog, VHDL	CERN-OHL-1.2	2020-02-23 → 2020-04-06, 34	none (original)
gatecat__snes_mister_ulx3s	SNES (MiSTer core by srg320) ported to ULX3S via open toolchain (yosys+ghdl+nextpnr+trellis)	85F (ULX3S 85k per README)	open: yosys+ghdl+ghdl-yosys-plugin+nextpnr-ecp5+trellis	VHDL (SNES core src/) + Verilog (ulx3s/ port layer) + SystemVerilog, mixed	GPL-3.0	? → 2025-09-05, ?	srg320/SNES_MiSTer (MiSTer core); independent ULX3S port, diverged from emard__snes_mister_ulx3s
gojimmypi__z80386-ulx3s-doom	CPU-only bring-up of the z386 (x86-compatible, from nand2mario/z386_MiSTer) on ULX3S 85F — first milestone toward eventually running FreeDOS/Doom; no SDRAM/VGA/IDE/audio/Doom wired up yet	85F (README explicit: ‘ULX3S 85F’, ECP5-85K, CABGA381, validated at 25MHz/seed 56)	open; Yosys (via read_slang plugin, requires Yosys >=0.67) + nextpnr-ecp5 (seed-search across multiple seeds for timing closure) + ecppack + openFPGALoader/fujprog	SystemVerilog 1 (rtl/z80386_synth_probe.sv) + generated Verilog 1 (ROM) + x86 asm 2 + shell 7, plus submodule z386_MiSTer: Verilog (64 .v) + SystemVerilog (59 .sv) + VHDL (2) ao486-derived MiSTer PC SoC wrapper; its own CPU (src/z386) is a nested unfetched submodule	none found (repo has .gitattributes/.gitignore/.gitmodules but no LICENSE file); submodule z386_MiSTer: also no LICENSE file, mixed per-file headers - LGPL-3.0-or-later (sys/ MiSTer framework e.g. sd_card.sv), BSD-2-Clause (src/soc/vga.v (c) Aleksander Osman, src/soc/ide.v (c) Alexey Melnikov), no header on some nand2mario files (src/system.sv, src/memory/sdram.v)	? → 2026-07-29, ?	fork/derivation: CPU core is git submodule third_party/z386_MiSTer -> nand2mario/z386_MiSTer (now fetched); however z386_MiSTer itself vendors the real z386 CPU as ITS OWN nested submodule src/z386 -> nand2mario/z386 (branch z386x), which is still empty/unfetched. patches/ dir carries compatibility patches
hoglet67__ice40atom	Ice40Atom: Acorn Atom 6502 retro-computer core (CPU, MC6847 video, SID audio, PS/2 keyboard) for BlackIce	iCE40 HX4K (NOT ECP5) - built with device size hx8k / package tq144:4k (arachne-pnr -d 8k -P tq144:4k, icetime -d hx8k, blackice/build.sh); matches hx-boards-survey note that BlackIce (HX4K) is built as hx8k	open (yosys+arachne-pnr+icepack+icetime, blackice/build.sh); Ice40Atom.core FuseSoC descriptor also references icestorm backend, icarus/modelsim simulators	Verilog (19 .v), memory init (4 .mem/.hex, charrom+ROM images)	none found at repo root; src/cpu.v carries a permissive notice (Arlet Ottens, free to use with attribution kept); src/sid/sid_6581.v ported SID core, no explicit license in header	? → 2019-06-01, ?	none (bundles Arlet Ottens’ 6502 core and a ported SID 6581 core, see reuse)
hoglet67__ice40beeb	Ice40Beeb: BBC Micro Model B retro-computer core (6502 CPU, MC6845 CRTC, SAA5050 teletext, SN76489 sound, VGA scandoubler) for BlackIce	iCE40 HX4K (NOT ECP5) - built with device size hx8k / package tq144:4k (arachne-pnr -d 8k -P tq144:4k, icetime -d hx8k, blackice/build.sh); matches hx-boards-survey note that BlackIce (HX4K) is built as hx8k	open (yosys+arachne-pnr+icepack+icetime, blackice/build.sh)	Verilog (21 .v)	none found at repo root; src/mist_scandoubler.v carries GPL-3.0-or-later header (Till Harbaum, MiST project); src/cpu.v carries Arlet Ottens’ permissive free-use notice	? → 2017-12-18, ?	none (bundles Arlet Ottens’ 6502 core and Till Harbaum’s MiST scandoubler, see reuse)
htfab__asicle2	Asicle v2: Wordle clone in raw silicon (Tiny Tapeout ttsky25b/Sky130), with FPGA ports for ULX3S (ECP5), Pico-Ice (iCE40) and Basys3 (Xilinx)	ECP5 85F (fpga/ulx3s/apio.ini: board = ulx3s-85f); ALSO iCE40 (NOT ECP5) via fpga/pico-ice/apio.ini (board = pico-ice) and Xilinx 7-series (NOT ECP5) via fpga/basys3/vivado_build.tcl (xc7a35tcpg236-1)	both: open (apio/yosys+nextpnr for ULX3S and Pico-Ice) and Diamond-free Vivado for Basys3 (fpga/basys3/vivado_build.sh)	SystemVerilog (23 .sv)	Apache-2.0 (LICENSE)	? → 2025-10-30, ?	none (v2 of the author’s own Asicle, originally taped out on MPW6)
ibm2030__ibm2030	IBM2030: cycle-accurate IBM System/360 Model 30 CPU + multiplexer channel emulation in VHDL, for a Xilinx Spartan-3 dev board	Xilinx Spartan-3 (NOT ECP5) - XC3S1000 (IBM2030.xise: Device=xc3s1000, Device Family=Spartan3)	diamond-equivalent: Xilinx ISE Webpack (proprietary; IBM2030.xise project, digilentSP3.ucf constraints)	VHDL (59 .vhd/.vhdl files: cpu.vhd, ibm2030-cpu.vhd, ~90 FMD2030_* gate-level modules, ccros.vhd microcode, vga/panel/switch drivers)	GPL-3.0 (COPYING, GPLv3 text)	? → 2025-09-24, ?	none
ironsteel__nes_ecp5	NES on ECP5 upstream (Rangel Ivanov)	12F default	open (yosys + ghdl plugin)	Verilog, SystemVerilog, VHDL	GPL (header)	2019-11-23 → 2026-01-11, 139	upstream of emard__nes_ecp5
lawrie__apple-one	Apple 1 Verilog, ULX3S HDMI + PS/2 + UART (32KB RAM, ULX4M)	25F	open	Verilog	Apache-2.0	2018-01-02 → 2022-04-20, 195	fork of alangarf/apple-one; best ULX3S copy
lawrie__fpgacosmacelf	Cosmac ELF: CDP1802 + CDP1861 in SpinalHDL, UART loader	12F default (12-85)	open (SpinalHDL)	SpinalHDL, generated Verilog	GPL-3.0	2019-12-14 → 2020-01-31, 39	fork of Winston Lowe FPGACosmacELF
lawrie__jupiter_ace	Jupiter Ace (1982 Forth-based home computer) core, for ULX3S and ULX4M boards	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (14 .v)	none found	? → 2022-05-04, ?	none
lawrie__slabboy	SlabBoy: Game Boy in SpinalHDL on ST7789/SSD1331	25F (idcode 12F)	open (sbt SpinalHDL)	SpinalHDL, generated Verilog	MIT (boot ROM likely Nintendo)	2018-04-10 → 2020-03-05, 85	fork of Craig Bishop slabboy
lawrie__ulx3s_68k	Experimental 68000 CPU core testbed for ULX3S (fx68k-based)	85F default (DEVICE ?= 85k in ulx3s.mk)	open: yosys+nextpnr-ecp5+ecppack via shared ulx3s.mk	Verilog (28 .v), Assembly (7 .asm), SystemVerilog (4 .sv), Python (4)	none found	? → 2020-07-13, ?	none found (lawrie’s own experiments; likely shares fx68k core with ulx3s_mac128)
lawrie__ulx3s_acorn_atom	Acorn Atom 8-bit home computer core ported to ULX3S (from Ice40Atom)	85F (ulx3s/ulx3s.mk DEVICE?=85k); ulx4m variant uses um-45k	open (yosys+nextpnr-ecp5+ecppack via ulx3s.mk)	Verilog (21 .v)	none found	? → 2022-04-20, ?	port of hoglet67/Ice40Atom (ICE40); not one of our other cloned slugs
lawrie__ulx3s_altair_8800	Altair 8800 (1975 kit computer) front-panel emulation on ULX3S, HDMI front panel display	85F required per README (“does not run on a 12f because of BRAM used for background image”); ulx3s.mk default DEVICE ?= 12k conflicts with Makefile’s own DEVICE=85k override — 85k is the actually-used value	open: yosys+nextpnr-ecp5+ecppack via shared ulx3s.mk	Verilog (25 .v), SystemVerilog (1 .sv), Python (4)	none found	? → 2021-04-28, ?	CPU implementation from the Odysseus project (ulx3s/fpga-odysseus, i.e. goran-mahovlic/odysseus_sprites lineage); partly based on MiSTer-devel/Altair8800_Mister
lawrie__ulx3s_amstrad_cpc	Amstrad CPC 664 emulation (1 disk drive) for ULX3S, VGA-over-HDMI + audio + on-screen-display disk loader	85F required per README (“only works on an 85F because of the amount of BRAM it uses”); ulx3s.mk DEVICE ?= 85k	open: yosys+nextpnr-ecp5+ecppack via shared ulx3s.mk	Verilog (31 .v), Python (5), SystemVerilog (2)	none found	? → 2022-05-04, ?	none found (lawrie’s own port); also has a ulx4m (different board) variant
lawrie__ulx3s_atari_2600	Atari 2600 (VCS) console core for the ULX3S and ULX4M boards	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (20 .v), 6502/TIA assembly test ROMs (13 .asm)	none found	? → 2022-05-08, ?	none
lawrie__ulx3s_ay_3_8500	AY-3-8500 “Pong-on-a-chip” recreation for the ULX3S	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (6 .v)	none found	? → 2020-05-01, ?	none
lawrie__ulx3s_bbc_micro	BBC Micro home computer core for the ULX3S	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (21 .v)	none found (code); bundled copyrighted BBC OS/BASIC ROM images in roms/	? → 2023-02-05, ?	fork/port of hoglet67/Ice40Beeb for ECP5
lawrie__ulx3s_colecovision	ColecoVision game console core for ULX3S, also ported to a distinct ‘ulx4m’ board variant	85F for ulx3s/ target (DEVICE ?= 85k in ulx3s/ulx3s.mk); ulx4m/ulx4m.mk targets a different device (um-45k, not ULX3S)	open: yosys+nextpnr-ecp5+ecppack via shared ulx3s.mk / ulx4m.mk	Verilog (24 .v), Python (4), SystemVerilog (1)	none found	? → 2023-05-15, ?	none found (lawrie’s own port)
lawrie__ulx3s_cpm_z80	CP/M on Z80 (port of Ice40CPMZ80 / Grant Searle’s Multicomp) for the ULX3S	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (16 .v)	none found	? → 2020-04-18, ?	port of hoglet67/Ice40CPMZ80 (itself derived from Grant Searle’s VHDL Multicomp)
lawrie__ulx3s_gamegear	Sega Game Gear console core for ULX3S	85F (DEVICE ?= 85k)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (21 .v, 1 .sv), Python (4)	none found	? → 2021-01-16, ?	none (shares Z80/osd/lattice framework with lawrie__ulx3s_sg_1000, same author family)
lawrie__ulx3s_mac128	Macintosh Plus (128K/512K-derived) emulation core for ULX3S, HDMI video + SDRAM + floppy + sound	85F default (DEVICE ?= 85k in ulx3s.mk)	open: yosys+nextpnr-ecp5+ecppack via shared ulx3s.mk	Verilog (25 .v), SystemVerilog (4 .sv), Python (5, esp32 tools)	none found	? → 2022-08-08, ?	derives from PlusToo and Mist/Mister-board Mac Verilog sources; CPU is fx68k (ijor/fx68k) 68000 core
lawrie__ulx3s_msx	MSX 8-bit home-computer core for ULX3S	85F default (DEVICE ?= 85k in ulx3s.mk)	open: yosys+nextpnr-ecp5+ecppack via shared ulx3s.mk	Verilog (31 .v), Python (5), SystemVerilog (1)	none found	? → 2023-05-14, ?	none found (lawrie’s own port)
lawrie__ulx3s_pdp_11	lawrie/ulx3s_pdp_11: (no code) “Experiments with the PDP 11 instruction set on the Ulx3s Ecp5 FPGA board”	unknown	n/a	none	none found	? → 2022-03-21, ?	none
lawrie__ulx3s_ql	Sinclair QL home computer core for the ULX3S	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (22 .v), some SystemVerilog (4 .sv), 68k assembly (7 .asm/.mx1), C (3), Python (5)	none found	? → 2020-09-07, ?	none
lawrie__ulx3s_sg_1000	Sega SG-1000 console core for ULX3S	85F (DEVICE ?= 85k in ulx3s.mk)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (20 .v, 1 .sv), Python (3, osd/font tools)	none found	? → 2020-07-02, ?	none (shares Z80/osd/lattice framework with lawrie__ulx3s_gamegear, same author family)
lawrie__ulx3s_sms	Sega Master System / SG-1000: TV80, VDP, SN76489, SDRAM carts, ESP32 OSD	85F default (12F works)	open	Verilog	none found at repo level; src/osd/spirw_slave_v.v BSD, osd.v/spi_osd.v no header, TV80 MIT, sdram.v GPL-3.0 (MiST); Sega BIOS in roms/ (proprietary)	2020-12-25 → 2023-05-19, 46	none (original)
lawrie__ulx3s_trs_80	TRS-80 Model I: TV80, HDMI, PS/2, ESP32 OSD .cas/.cmd	85F default	open	Verilog, Python	none found (Level II ROM in repo)	2020-05-14 → 2020-05-20, 23	none (original; emard OSD)
lawrie__ulx3s_vic_20	Commodore VIC-20 home computer core for the ULX3S	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (16 .v), 6502 assembly (4 .xa), Python (7)	none found (code); bundled copyrighted Commodore kernal/basic/character ROM images in roms/	? → 2020-05-14, ?	none
lawrie__ulx3s_z80_template	Reusable Z80 computer template/base for building retro Z80 machines (TRS-80, ZX80/81, Jupiter Ace, Spectrum, etc.) on the ULX3S	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (21 .v), Python (5)	none found	? → 2021-02-27, ?	none (this is itself the shared base other lawrie Z80 repos, e.g. ulx3s_z80_trs80, are built from)
lawrie__ulx3s_z80_trs80	TRS-80 Model 1 home computer core for the ULX3S, built from the ulx3s_z80_template base	85F (Makefile DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	Verilog (22 .v), Python (5)	none found (code); bundled copyrighted TRS-80 BOOT.ROM and character ROM, plus cassette-image games (.cas)	? → 2021-02-27, ?	derived from lawrie/ulx3s_z80_template (shares its code base)
lawrie__ulx3s_zx81	ZX80/ZX81: TV80, HDMI scandoubler, PS/2, ear/audio	85F default	open	Verilog, SV	none found (Sinclair ROM)	2020-01-13 → 2022-05-04, 14	none (original; best copy)
lawrie__ulx3s_zx_spectrum	Verilog ZX Spectrum 48K core for ULX3S (HDMI/VGA, PS/2, ESP32 game loading)	85F default (DEVICE ?= 85k in ulx3s.mk; DEVICE=12k selectable via make var)	open: yosys+nextpnr-ecp5+ecppack via shared ulx3s.mk	Verilog (28 .v), Python (7, esp32 tools), VHDL (3)	none found	? → 2020-05-05, ?	none found (lawrie’s own port); uses open ZX Spectrum Basic ‘opense.rom’, optionally real 48.rom
linuxjedi__minimig_ecs	Minimig ECS (Amiga emulator) portable core targeting Altera Cyclone-V, Lattice ECP5 (incl. ULX3S), Xilinx Artix-7	25F/45F (LFE5U-25F-6BG381C and LFE5U-45F-6BG381C per README)	both: trellis_main.mk (open, yosys+nextpnr) and diamond_main.mk/diamondc side by side	VHDL (Minimig core, source_emard/) + Verilog (rtl_emard/), mixed	none found	? → 2022-05-17, ?	robinsonb5/Minimig-AGA/minimig_tc64 lineage; originally a FleaSystems ‘Ohm’ board port
machdyne__nes_ecp5	NES core fork, ULX3S-only variant: simpler than cheyao’s, no ULX4M/OSD/mapper extensions	12F default (FPGA_SIZE ?= 12; supports 12/25/45/85, no um-45)	open: yosys -abc9 +nextpnr-ecp5+ecppack	Verilog/SystemVerilog/VHDL, same file set as cheyao__nes_ecp5 minus icepi-zero/ulx4m extras	none found	? → 2026-01-11, ?	cheyao__nes_ecp5 / common nes_ecp5 lineage (identical commit hash to ironsteel__nes_ecp5, already cataloged)
markus-zzz__myc64	[WIP] Commodore 64 implementation in Verilog, with Verilator simulator and optional USB-keyboard SoC variant	25F (build-ulx3s.sh: nextpnr-ecp5 –25k)	open: yosys (ulx3s-top.ys script) + nextpnr-ecp5 + ecppack via syn/build-ulx3s.sh	Verilog (13 .v), Shell (5), C++ (3, Verilator testbench)	none found	? → 2020-09-20, ?	none (own project); optional MyC64-SoC variant depends on author’s separate usbdev and retrocon repos (not vendored here)
mikeakohn__apollo11_fpga	Apollo Guidance Computer CPU reimplementation for iceFUN (16-bit AGC ISA), with SPI LCD, servo, UART and EEPROM peripherals	iCE40 HX8K (NOT ECP5) - CB132 (Makefile: nextpnr-ice40 –hx8k –package cb132, icefun.pcf)	open (yosys synth_ice40 + nextpnr-ice40 + icepack, Makefile); test ROMs assembled with naken_asm (author’s own assembler)	Verilog (7 .v, 2137 lines: agc.v, display_spi.v, servo_control.v, uart.v, eeprom.v, spi.v, memory.v) + 16 .asm test programs	MIT (LICENSE, Michael Kohn 2024)	? → 2024-12-25, ?	none (mikeakohn’s CPU-in-Verilog series, same family as mikeakohn__riscv_fpga already catalogued)
msiddalingaiah__centurion	Centurion (Warrex) minicomputer CPU6 (Am2900 bit-slice) reimplementation in Verilog, microcoded, runs on Alchitry Cu (iCE40 HX8K)	iCE40 HX8K (NOT ECP5) - CB132 (Makefile active target: Alchitry Cu, DEVICE=hx8k PACKAGE=cb132, ice40_alchitry_cu.pcf); iCEBlink40 HX1K -VQ100 pcf present but commented out of Makefile	open (yosys synth_ice40 + nextpnr-ice40 + icepack, Verilog/Makefile); simulation via Icarus Verilog (iverilog+vvp)	Verilog (13 .v, 1466 lines: CPU6.v, Am2901.v, Am2909.v, Am2911.v, Instructions.v, MapROM.v, CodeROM.v, RegisterRAM.v, Clock.v, PLL.v, LEDPanel.v, iCE40.v, CPU6TestBench.v)	MIT (LICENSE, Madhu Siddalingaiah 2022)	? → 2022-08-01, ?	none (recreates Warrex Centurion CPU6 board; schematics/microcode refs from Meisaka/CenMiniCom and sjsoftware/centurion-cpu6)
msinger__iceboy	iceboy: Game Boy (DMG) reimplementation in Verilog/SystemVerilog (SM83/LR35902 CPU, PPU, MBC1, LCD drivers), targets iCE40HX-8K	iCE40 HX8K (NOT ECP5) - CT256 ($(NEXTPNR) --hx8k --package ct256, src/Makefile.am:140, board=hx8k_brk)	open (yosys+nextpnr-ice40+icepack); GNU autotools build (configure.ac/automake, ./configure --enable-board=hx8k_brk)	SystemVerilog (73 .sv, src/cpu,ppu,mbc,lcds), Verilog (13 .v, incl. src/boards/hx8k_brk-top.sv is .sv not .v - recount: cpu/lr35902_cpu.v and lr35902_dbg_ifc.v are .v)	CERN-OHL-W v2 (LICENSE, README)	? → 2025-03-29, ?	none
nullobject__m68k-ulx3s	Motorola 68000 SoC on ULX3S using the fx68k core, with OLED display, framebuffer/GPU and ACIA serial	85F (Makefile DEVICE=85k)	open: yosys+nextpnr-ecp5+ecppack via Makefile; Verilator used for gpu.v simulation	Verilog (12 .v + vendored fx68k core), C (2, ROM programs), C++ (1, verilator tb)	mixed: repo root has no LICENSE; lib/fx68k/LICENSE covers the vendored CPU core only	? → 2025-06-06, ?	uses vendored lib/fx68k (fx68k core by another author, own LICENSE)
pnru__ti99	TI-99/2 in Verilog (pnru, gitlab): TMS99000 CPU, HDMI, PS/2, HEXBUS	25F (idcode 12F)	open	Verilog	public domain (headers); TI ROM other terms	2019-10-19 → 2020-11-29, 35	none (original)
quigleyj97__nesgate	NESgate: WIP VHDL NES emulator (MOS 6502 datapath in progress), CI-built as a ULX3S bitstream on every push	ECP5 85F (synth: nextpnr-ecp5 –85k –package CABGA381)	open: ghdl-yosys-plugin (hdlc/ghdl:yosys), nextpnr-ecp5 (hdlc/nextpnr:ecp5), ecppack (hdlc/prjtrellis), all via Docker in synth; per-core cocotb+GHDL tests	VHDL (22 .vhdl/.vhd)	Hippocratic License 3.0 (non-OSI, LICENSE.md, BDS-CL-LAW-MIL variant)	? → 2025-04-20, ?	none
remyciterin__dooom	DOoOM: out-of-order RISC-V CPU (Bluespec) with HDMI/SDRAM, boots DOOM	85F (–85k in Makefile)	open (yosys+nextpnr-ecp5+ecppack)	Bluespec (45 .bsv), Zig (16, soft/ firmware), Rust (15, rust/ tool), Verilog (11)	GPL-2.0 (LICENSE)	? → 2026-01-01, ?	none directly; shares SDRAM/HDMI/simulation infra with remyciterin__3driscv (same author, earlier iteration)
rob-ng15__pawsv2	PAWSv2: RV32IMAFC+B/RV64GC+B RISC-V retro-console-style CPU + BIOS, written in Silice	85F only, per README (“BUILD_ulx3s/PAWSv2-32.bit”); no explicit nextpnr flag found in inspected files	open: Silice -> yosys/nextpnr-ecp5 (via Silice’s own build pipeline, not visible as raw nextpnr flags in Makefile)	Silice (top), C (865 .c/622 .h software), Forth (240 .fth), Assembly (36+34)	MIT (RV32/LICENSE, RV64/LICENSE, Rob S 2021); many bundled 3rd-party licenses (newlib, pforth, imgui, fat_io_lib, etc.)	? → 2025-11-29, ?	inspired by sylefeb’s ICE-V (not cloned here); bundles many 3rd-party C libs (newlib, pforth, imgui, fat_io_lib)
ruebenschus__atari-fpcartridge	Ruebenschus/Atari-FPCartridge: Atari ST cartridge emulator using ULX3S — FPGA cart-emulation gateware + KiCad level-shifting adapter PCB	12k (DEVICE := 12k in Makefile, CABGA381 package)	open (oss-cad-suite: yosys+nextpnr-ecp5+ecppack+openFPGALoader)	Verilog (4)	none found	? → 2026-06-25, ?	none
schlae__graphics-gremlin	Graphics Gremlin: ISA video card FPGA logic emulating IBM MDA (monochrome) and CGA graphics adapters, outputs VGA + NTSC composite	iCE40 HX4K (NOT ECP5) - TQ144 (DEVICE = hx8k + nextpnr-ice40 --hx8k --package tq144:4k, verilog/Makefile:8,29; matches survey listing as HX4K-TQ144 target)	open (yosys+nextpnr-ice40+icepack+icemulti, verilog/Makefile)	Verilog (21 .v, verilog/*.v, 3006 lines)	CC-BY-SA-4.0 (LICENSE; hardware design, applies to gateware too per file headers)	? → 2024-10-24, ?	none
speccery__icy99	icy99: TI-99/4A home computer emulation, primary target ULX3S 85F (also a FleaFPGA Ohm 25F build)	85F (README: ‘ECP5 85F FPGA chip’; Makefile –85k for ti994a_ulx3s target)	open; yosys+nextpnr-ecp5+ecppack via Makefile, oss-cad-suite	Verilog (44 .v), Python (11, esp32/tools), assembly (2, TMS9900 test asm)	none found (no LICENSE/COPYING)	? → 2023-11-28, ?	none
sylefeb__silice	Silice HDL language/compiler + many ULX3S projects (DooM-chip, RISC-V, graphics)	12F/25F/45F/85F (default 85k)	open (+openFPGALoader)	Silice (578 .si), Verilog, C++ + submodule tinygpus: Silice (10 .si), C (10), Lua (9), C++ (2)	mixed: GPL-3.0 compiler, MIT examples/glue; submodule tinygpus: triple-licensed MIT/GPL-3.0/CERN-OHL-S-2.0 (LICENSE_mit/LICENSE_gplv3/LICENSE_ohls) - hardware .si files marked CERN-OHL-S	2019-10-07 → 2026-06-18, 3420	none
sylefeb__tinygpus	tinyGPUs: small experimental GPU/rasterizer cores in Silice HDL (incl. doomchip); ULX3S is only mentioned as a personal dev board, not an actual build target in this repo	iCE40 (NOT ECP5) - hardware/SOCs/ice40-dmc-1 (Silice .si targeting the ice40 dmc-1 board). README.md:149 mentions personally using a ‘ULX3S 85F’ for design-size headroom, but no ULX3S SOC/top exists in this repo: claim only, and a marginal/passing one, not a supported target	open (Silice -> yosys+nextpnr-ice40, per software/compile/ice40/make_image.si); no ECP5/ULX3S toolchain files present	Silice .si source (dozens of files, not counted by .v/.sv/.vhd extensions - 0 found by those), Python (2)	multi-licensed: GPL-3.0 (LICENSE_gplv3), MIT (LICENSE_mit), OHL (LICENSE_ohls) - which applies to which component not verified	? → 2024-01-25, ?	none
techprototyper__trs80-rev-z	TRS-80 Model 1 (Rev G) recreated in RTL for ULX3S-85F: Z80 (tv80 core) + video/keyboard/cassette/floppy, DVI 800x600 out, USB-HID keyboard; extensively documented with an ADR log and golden-model tests	85F (README states ULX3S-85F explicitly; boards/ulx3s/Makefile ‘make bit’ targets it)	open: yosys(+synth.ys)+nextpnr-ecp5+ecppack via boards/ulx3s/Makefile (‘make bit’/’make prog’); extensive Verilator golden-model + cocotb-style testbenches for every module	Verilog (37 .v incl. vendored tv80 core and usb_hid_host), SystemVerilog (36 .sv, mostly testbenches), Python (25, test/tooling scripts), C++ (6, Verilator sim harness)	MIT (repo LICENSE); tv80 and usb_hid_host vendored cores carry their own separate LICENSE/README; roms/README.md explicitly forbids committing the copyrighted Tandy/Microsoft Level II BASIC ROM (loaded at runtime from SD/ESP32 instead)	? → 2026-08-27, ?	vendors rtl/vendor/tv80 (Z80 core) and boards/ulx3s/vendor/usb_hid_host, each with their own LICENSE/attribution
ulx3s__apple2fpga	Apple II+ mirror (older snapshot)	25F	diamond	VHDL, Verilog	none found	2019-12-18 → 2020-01-20, 65	stale mirror of emard__apple2fpga (ancestor HEAD)
ulx3s__galaksija	Galaksija mirror + Olimex GateMate port	12F trellis / 25F diamond	both	Verilog, VHDL	none found	2018-06-12 → 2024-10-14, 35	fork of emard__galaksija (2019 content)
ulx3s__ulx3s_zx81	ZX81 mirror (early HDMI)	85F	open	Verilog	none found	2020-01-13 → 2020-02-19, 8	stale mirror of lawrie__ulx3s_zx81
victor-fisyuk__voodoo-fpga-public	3dfx Voodoo Graphics (Voodoo 1) 3D accelerator reimplementation in SystemVerilog, demoed on ULX3S+HDMI+SDRAM	not determinable (no source present); README states real hardware is a Radiona ULX3S with Lattice ECP5	n/a (no build files in this public repo)	none (0 HDL files; repo is README + images only)	none found	? → 2026-09-13, ?	none; public repo appears to be a showcase-only release of a private project
wifiboy__ok-ice40pro	iCE40 UP5K (OK:iCE40Pro board): open-source educational FPGA gamepad console with 10 apio tutorial examples plus 3 full SoCs - J1A Forth (swapforth port), PicoRV32 RISC-V SoC w/ LCD, and a ported NES emulator core with VGA output.	iCE40 UP5K (NOT ECP5) - SG48	open (yosys+nextpnr-ice40+icepack/icemulti, icestorm); tutorials use apio.ini wrapper	Verilog (43 .v total across j1a/nes/rv32/tutorials); Forth (.fs, J1A firmware/demos); C (rv32 SoC firmware, c-src/ + numbered examples)	MIT (LICENSE, repo root, Copyright 2021 WiFiBoy); bundled NES core files say ‘GPL Licensed, see COPYING’ but no COPYING file exists in this repo	? → 2023-05-06, ?	mixed ports: ok-j1a-forth-soc-src from jamesbowman/swapforth (J1A); ok-nes-vga-src from Strigeus/Shah MiST fpganes core; ok-rv32-soc-src built on cliffordwolf/picorv32 (board framework itself original)
zeldin__icegdrom	iceGDROM: Dreamcast GD-ROM drive emulator - IDE + Sega Packet Interface, CD-DA, VexRiscv RV32 softcore running SD-card-backed disc image firmware	iCE40 HX8K (NOT ECP5) - CT256 (gdrom_hw_emulator_DEVICE := --hx8k --package ct256, fpga/GNUmakefile:11, nextpnr-ice40 invoked at line 47)	open (yosys+nextpnr-ice40+icepack, fpga/GNUmakefile); README also lists arachne-pnr as a required tool but the Makefile actually invokes nextpnr-ice40, so the doc is likely stale	Verilog (20 .v under fpga/source, incl. vendored VexRiscv.v); C (67 files across rv32/source firmware + test/source Dreamcast test programs + tools/source host utilities)	GPL-3.0 (COPYING, README states “free software (and hardware) licensed under GNU GPLv3”)	? → 2023-02-18, ?	none (fpga/source/vexriscv/core/VexRiscv.v is vendored SpinalHDL-generated VexRiscv output, not a submodule - “Generator: SpinalHDL v1.4.0” header)

Other gateware (video, audio, radio, flash, instruments)

Repo	What	FPGA	Toolchain	HDL	License	Active (first → last, commits)	Fork / preferred copy
advikbahadur__ulx3s-superresolution-cnn	OV7670 camera super-resolution CNN accelerator on ULX3S 85F, plus an unrelated 6502 SBC firmware	85F (bitstream named ulx3s_85f_CSI; FPGA_CHIP lfe5u-85f option in Makefile)	both (open: GHDL+yosys+nextpnr-ecp5+ecppack via trellis_main_ghdl.mk; diamond: scripts/diamond_main.mk + .xcf flashing scripts)	Verilog (23 .v), VHDL (via ghdl plugin), C (cc65 6502 firmware)	MIT	? → 2024-08-15, ?	derived from AngeloJacobo’s ULX3S camera/Sobel projects (LICENSE copyright “Angelo Jacobo”); better copies cloned locally as angelojacobo__ulx3s_fpga_camera_streaming and angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670
agamez__whisperice	wspr-icebreaker: autonomous VHDL-93 WSPR (4-FSK) beacon transmitter for the iCEBreaker with GPS/PPS clock calibration	iCE40 UP5K (NOT ECP5) - SG48 (–up5k –package sg48, Makefile:130-138)	open (yosys -m ghdl for synth, nextpnr-ice40+icepack+icetime; GHDL 7.0.0-dev also used for –std=93 sim); Makefile	VHDL-93 (28 .vhd: 15 src + 13 sim tb), Python (5: tools/*.py + reference/wspr_reference.py)	MIT (LICENSE)	? → 2026-09-28, ?	none
alberto-grl__1bitsdr	1bitSDR: 1-bit oversampled AM/MW/SW SDR (NCO/DDS + 1-bit mixer + CIC + sqrt AM demod) on MachXO2, upstream of jamesrosssharp/1_bit_AM	MachXO2 LCMXO2-7000HE (NOT ECP5) - 4TG144C (FPGASDR.ldf: device="LCMXO2-7000HE-4TG144C")	diamond (Lattice Diamond .ldf/.lpf project, Synplify synthesis; generated IP cores e.g. PLL, Multiplier via .edn/.ngd)	Verilog (83 .v), VHDL (21 .vhd, incl. g3r/ math library)	Apache-2.0 (LICENSE.md)	? → 2020-05-21, ?	none (upstream ancestor of the already-catalogued jamesrosssharp__1_bit_am, per rfdsp_survey lineage)
alhusseingamal__r2sdf-fft	r2sdf-fft: radix-2 DIF SDF streaming FFT, parametric N (default 8, prebuilt 512-pt bitstream), iCE40 HX8K, plus a matching OpenLane/Sky130 ASIC flow	iCE40 HX8K (NOT ECP5) - CT256 (fpga/Makefile: DEVICE=hx8k PACKAGE=ct256 MHZ=104, NEXTPNR=nextpnr-ice40, fpga/LatticeiCE40HX8K.pcf)	open (fpga/Makefile: yosys+nextpnr-ice40+icepack) + a separate OpenLane/Sky130 ASIC flow (asic/config.json, asic/gds)	Verilog (12 .v: rtl/+tb/), Python (8, python_model/ bit-accurate numpy reference model)	none found (no LICENSE/COPYING at any depth)	? → 2026-09-22, ?	none
amin005__skywave_sdr	Skywave SDR: direct-sampling HF receiver, AD9226 12-bit/32MSPS ADC -> CIC decimate-by-4 -> own ULPI USB-HS stack (8MSPS, 4MHz BW); tuning/I-Q planned	ECP5 25F (NOT ULX3S) - CABGA256 (build_usb_hs_adc.sh: nextpnr-ecp5 –25k –package CABGA256 –speed 6)	open (yosys+nextpnr-ecp5+ecppack via build_usb_hs_adc.sh; openFPGALoader -c ft2232 program); Icarus Verilog for simulation	Verilog (21 .v), Python (3, host/ capture+analysis)	BSD-3-Clause (LICENSE)	? → 2026-07-17, ?	none
antoinevg__hello-ethernet	hello-ethernet: Amaranth experiments wiring a Waveshare LAN8720 RMII PHY breakout to a ULX3S ECP5-85F via the external daqnet MAC/IP stack	ECP5 85F (top.py: from amaranth_boards.ulx3s import *; platform = ULX3S_85F_Platform())	open: Amaranth -> toolchain/oss-cad-suite, yosys+nextpnr-ecp5+ecppack via platform.build(top, do_program=True)	Python/Amaranth (2 files: top.py, car.py)	none found	? → 2023-02-19, ?	none (uses the external daqnet package for MAC/IPStack, not vendored)
apfaudio__eurorack-pmod	Eurorack PMOD: AK4619 audio-codec PMOD gateware (calibration, I2C/UART drivers, DSP synth/effects cores) for many FPGA dev boards	ECP5-5G 85F (LFE5UM5G-85F, CABGA554, speed 8, ECPIX-5; gateware/boards/ecpix5/Makefile: DEVICE=um5g-85k PACKAGE=CABGA554). Also ECP5 25F/45F CABGA381 (colorlight_i5/i9, NOT ECPIX-5) and ECP5 25F CABGA256 (Tiliqua r5). Also iCE40 UP5K SG48 (NOT ECP5: icebreaker, icesugar, pico_ice) and Cologne Chip GateMate (NOT ECP5/Lattice: gatemate_evb)	open (yosys+nextpnr-ecp5+ecppack, gateware/mk/ecp5.mk; also mk/ice40.mk for SB_ boards, mk/gatemate.mk needs proprietary GateMate p_r toolchain); simulation via cocotb+Verilator (gateware/sim/*)	SystemVerilog (24 own .sv), Verilog (6 own .v + 21 .v in fetched no2misc submodule), Python (16 .py: cocotb testbenches)	CERN-OHL-S-2.0 (top-level LICENSE, “Strongly Reciprocal”; single license file, no per-file headers seen in gateware/*.sv)	? → 2026-01-29, ?	none (README credits schnommus/eurorack-pmod, now maintained under apfaudio; not a GitHub fork relationship)
apfaudio__guh	guh: Amaranth USB2 HS/FS host engine library (SIE, enumeration, HID/MSC/MIDI host classes) for Tiliqua, also runs on Cynthion	12F (LFE5U-12F, BG256, Cynthion) - README.md: LUNA_PLATFORM=cynthion.gateware.platform:CynthionPlatformRev1D4 pdm run python3 examples/midi_host.py --upload; primary target is Tiliqua R4/R5 (guh/platform/tiliqua.py, its own ECP5 SoM, resource names deliberately match Cynthion’s target_phy/control_vbus_en/led)	open (Amaranth build backend via pdm; pdm run test = pytest -n auto tests/)	Python/Amaranth (31 .py: usbh/engines/periph/platform/protocol/util), Rust (6 .rs: rs/guh-dma + rs/guh-usb-msc host/firmware helper crates)	BSD-3-Clause (LICENSE)	? → 2026-09-07, ?	none
arisotura__spi_flash	SPI flash emulator at 48 MHz SPI, WiiU gamepad hacking	85F	diamond	Verilog	none found (uart.v MIT)	2024-10-09 → 2025-03-08, 6	derived from spispy (rewritten)
bit-hack__icesid	reDIP-SID/iCESugar: open-source FPGA reimplementation of the MOS 6581/8580 SID chip audio synthesis, drop-in replacement for the C64 SID	iCE40 UP5K (NOT ECP5) - SG48 package (–up5k –package sg48, reDIP-SID/Makefile.mk and icesugar/Makefile.mk)	open (yosys+nextpnr-ice40+icepack)	Verilog (20 .v: 9 icesid core, 7 reDIP-SID board, 3 icesugar board, 1 verilator ice40 model), C++ (tablegen, verilator testbench)	CERN-OHL-S-2.0 (LICENCE, root; matching SPDX header in reDIP-SID/*.v by Sylvain Munaut)	? → 2022-05-31, ?	none
bjonnh__ulx3s-synth	MIDI-controlled synth/sampler experiment (I2S audio out) for the ULX3S	85F (Makefile nextpnr-ecp5 –85k)	open; yosys+nextpnr-ecp5+ecppack (Makefile)	Verilog (6 .v, 1 .sv), VHDL (1, unused), Python (3, code-gen for sine/note tables)	none found	? → 2022-12-10, ?	none
blazra__tdr	TDR (time-domain reflectometry) prototype driving/sampling a pulse over the ECP5 SERDES/DCU, LiteX SoC on an ECP5 Versa board with a matching KiCad daughter PCB	45F ECP5 (LFE5UM-45F, or LFE5UM5G-45F-8BG381C on the ECP5-5G Versa; exact part unverified, litex_boards.platforms.versa_ecp5 not present in this clone) – see serdes_survey.md Versa board row	open (LiteX/Migen -> yosys+nextpnr-ecp5+ecppack via litex_boards.platforms.versa_ecp5)	Python/Migen (6 .py files: clock.py, daq.py, serdes_ecp5.py, versa_ecp5.py, init.py, software/ctrl.py)	BSD (file headers in serdes_ecp5.py, versa_ecp5.py, clock.py: ‘Copyright (c) 2018-2020 Florent Kermarrec … License: BSD’); no repo-level LICENSE file	? → 2020-08-01, ?	none (tdr/serdes_ecp5.py explicitly adapted from enjoy-digital/liteiclink, per file header comment)
bornabiro__fpga_epaper	BornaBiro/FPGA_epaper: e-paper (ED060SC7 panel via Inkplate) display driver for ULX3S, built with Lattice Diamond	LFE5U-12F-6BG381I (per epaper.ldf device field)	diamond (Lattice Diamond 3.12.0.240.2 + Synplify Pro; README notes Diamond LSE failed to synthesize the PLL)	Verilog (topModule.v, epaperDriver.v — small)	MIT	? → 2023-03-04, ?	none
c-elegans__single_sdr	single_sdr: SpinalHDL SDR channel (IQ decimator wrapping a dblclockfft-generated 256-pt FFT) targeting ECP5 LFE5U-45F	ECP5 LFE5U-45F CABGA381 (Makefile: nextpnr-ecp5 –45k –package CABGA381 –basecfg empty_lfe5u-45f.config)	open (sbt->SpinalHDL generates Top.v; yosys synth_ecp5 + nextpnr-ecp5; no ecppack step in this Makefile)	Scala/SpinalHDL (5 .scala), Verilog (6 .v: rtl/ multiplier helpers + sim/MULT18X18D.v primitive model); the FFT core itself (fft-core/*.v) is generated by the unfetched dblclockfft submodule and is NOT present in this clone	none found (no LICENSE file; sim/MULT18X18D.v carries a Lattice Semiconductor 2007 copyright notice for the primitive model only)	? → 2019-04-23, ?	none (SpinalTemplateSbt scaffold; the FFT RTL is meant to be generated by the dblclockfft submodule, see notes)
c-elegans__ulx3s_sdram	Small SDRAM controller experiments/testbed for ULX3S (IS42S16160 driver)	85F (synth.sh: nextpnr-ecp5 –85k –package CABGA381)	open: yosys+nextpnr-ecp5+ecppack via synth.sh; also documents OpenOCD/JTAG flashing as a faster alternative to openFPGALoader	Verilog (10 .v/.vh)	none found	? → 2021-02-08, ?	none (own experiments)
cariboulabs__cariboulite	CaribouLite: 6 GHz SDR HAT for RPi; iCE40LP1K FPGA bridges dual RX/TX LVDS I/Q streams from RF chips to RPi over SMI (mixing/demod is off-FPGA)	iCE40 LP1K (NOT ECP5) - QN84 (–lp1k –package qn84, firmware/Makefile:8)	open (yosys+nextpnr-ice40+icepack; firmware/Makefile); programmed via the project’s own ice40programmer host tool	Verilog (9 .v: firmware/{top,complex_fifo,io_ctrl,lvds_rx,lvds_tx,smi_ctrl,spi_if,spi_slave,sys_ctrl}.v), C/C++ (54 .c, 57 .h, 17 .cpp: host driver/lib), Python (24: examples/tools)	CC-BY-SA-4.0 (README.md License section); firmware/*.v carry no separate header	? → 2025-07-24, ?	none
carlosedp__chisel-fpga-pinfinder	Chisel FPGA Pin Finder: small Chisel tool that serial-prints pin names to help identify unknown FPGA pins by probing; tested on ULX3S and an Intel Stratix V (Storey Peak) board	ECP5 (ULX3S; constraints/ecp5-ulx3s.lpf, README ‘For ULX3S, use 25000000’); also Intel/Altera Stratix V (NOT ECP5) - Storey Peak board (README, Quartus-style constraints shown inline)	open for ULX3S (Fusesoc + yosys/nextpnr, per README Fusesoc build instructions); Quartus (proprietary) for the Storey Peak/Stratix V target	Scala (4, Chisel)	MIT (LICENSE)	? → 2024-09-24, ?	none
carlraymond__ulx3s-container	‘Big Fake Nixie Tube Clock’ — ULX3S ECP5-12F + ESP32 driving 4x 800x320 LCD nixie-digit displays; repo is mostly a Docker/WSL2 dev-container toolchain setup, actual gateware is a stub	12F (blinker.lpf comment ‘ULX3S v3.x ECP5-12F’; ProjectIdea.md: ‘12K LUTs’)	open; detail=yosys+nextpnr-ecp5+ecppack, built inside a custom Docker toolchain image (Dockerfile compiles yosys/nextpnr-ecp5/openFPGALoader/Verilator/ESP-IDF from source)	Verilog 1 (blinker.v, 8-LED counter); C 1 (ESP32 blinker/main.c, unrelated stub)	none found (no LICENSE file)	? → 2026-03-23, ?	none
chiplet__ulx3s-blinky	Minimal ULX3S blinky, same Makefile/Makefile-style skeleton as chiplet’s acorechip-ulx3s (likely their project template)	85F (Makefile: PART_BASECONFIG=lfe5u-85f, –85k)	open; detail=yosys+nextpnr-ecp5+ecppack	Verilog 1 file	none found (README.md is empty, no LICENSE)	? → 2024-03-26, ?	none; structurally near-identical Makefile to chiplet__acorechip-ulx3s (same author, probably its template origin)
circuit-killer__fpga-usbhid-host	Minimal FPGA USB-HID host (joystick/mouse) state machine, with ULX3S 45F and 85F project variants	45F (ulx3s-saitek / ulx3s-dragonrise-oled project.ldf: LFE5U-45F) and 85F (proj/lattice/ulx3s/ulx3s-v20-85f-* variants)	both; proj/lattice/include/trellis/makefile (yosys+nextpnr-ecp5+ecppack) and project.ldf+diamondc (Lattice Diamond)	VHDL (25 .vhd: USB HID host state machine + CRC/packet helpers)	none found (no LICENSE/COPYING)	? → 2018-12-17, ?	derived from CoreAmstrad’s joystick USB host driver (per README)
circuit-killer__fpga-usbserial	USB1.1 full-speed device-side USB-to-serial core (VHDL), multi-board (also Xilinx), incl. ULX3S variants at several ECP5 sizes	12F/25F/45F/85F (separate build dirs + per-size .xcf flash/sram files; proj default FPGA_SIZE=12)	both; open (proj/lattice/ulx3s/scripts/ulx3s_trellis.mk: yosys+nextpnr-ecp5+ecppack) and Diamond (ulx3s_diamond.mk + .xcf/.ldf via ispVM/diamondc)	VHDL (16 .vhd), Verilog (1 .v ULPI wrapper)	GPL-2.0 (usb_serial/COPYING)	? → 2019-02-23, ?	none (README: “second attempt to get usb-serial from opencores”)
cronokirby__ck-snes	SNES emulator core targeting ULX3S (very early-stage / WIP)	unknown (min lpf implies a reduced pin set; no nextpnr device flag found in repo)	open (implied via oss-cad-suite/Nix flake; no explicit yosys/nextpnr commands found in repo)	VHDL (3: platform/ulx3s/Top.vhd, hdl/src/Uart.vhd, hdl/src/Test.vhd), Rust (asm/, tools/)	none found	? → 2026-04-05, ?	none
daglem__redip-sid	reDIP SID: iCE40UP5K DIP-28 board running cycle-accurate MOS 6581/8580 SID chip emulation, with I2S/SGTL5000 codec, I2C, optional USB (muacm)	iCE40 UP5K (NOT ECP5) - SG48I package (nextpnr-ice40 –up5k –package sg48 –freq 24, gateware/Makefile)	open (yosys synth_ice40 + nextpnr-ice40 + icepack; optional sv2v pre-pass for Yosys < 0.24)	SystemVerilog (14 .sv + 2 .svh), Verilog (8 .v)	CERN-OHL-S-2.0 (LICENSE, root; matching header in gateware/.sv,.v, Dag Lem 2022-2023)	? → 2024-09-23, ?	none
dan-rodrigues__ics-adpcm	ics-adpcm: programmable multichannel IMA-ADPCM decoder/mixer, ULX3S 85F demo	85F (ECP5_SIZE = 85)	open; yosys+nextpnr-ecp5+ecppack via demo/Makefile; symbiyosys formal tests in CI	Verilog (12 .v, core+demo)	MIT	? → 2020-12-28, ?	none
dan-rodrigues__mobile-fpga-bluetooth-demo	Mobile BLE-to-LED demo: iOS SwiftUI app + ESP32 BLE peripheral + ULX3S FPGA LED driver	85F (ECP5_SIZE = 85)	open; yosys+nextpnr-ecp5+ecppack via rtl/Makefile	Verilog (4 .v, small LED/SPI glue), Swift (5, iOS app), Python (3, ESP32 MicroPython)	MIT	? → 2020-12-12, ?	none
dan-rodrigues__ulx3s-bluetooth-gamepad	Bluetooth gamepad-to-LED demo: ESP32 (Bluetooth via unijoysticle2 fork) -> SPI -> FPGA shows gamepad state on LEDs	12F and 85F (prebuilt esp32_passthru/ulx3s_12f.bit and ulx3s_85f.bit; no explicit nextpnr flag found in Makefile snippet)	open: yosys+nextpnr-ecp5+ecppack via Makefile	Verilog (4 .v)	none found	? → 2020-10-24, ?	ESP32 firmware is a fork of ricardoquesada/unijoysticle2 (snes-spi branch), included as submodule
dangerousprototypes__buspirateultrahdl	BusPirateUltraHDL: Bus Pirate Ultra FPGA gateware - SPI/UART/PWM/ADC engines + MCU parallel interface for the NextGen Ultra debug probe	iCE40 HX8K (NOT ECP5) - CT256 (DEVICE=hx8k, arachne-pnr -P ct256, hdl/Makefile and components/uart/Makefile)	open (yosys synth_ice40 -blif + arachne-pnr + icepack), hdl/Makefile and components/uart/Makefile; programmed with iCEburn.py	Verilog: 26 .v (13 in hdl/, 13 in components/); no VHDL	GPL-3.0 (LICENSE, GPLv3 text)	? → 2019-12-03, ?	none (peripheral cores by Chris van Dongen/SMDprutser per file headers, written for Bus Pirate NextGen Ultra)
danielh186__6502-tapeout	Open-source 6502-compatible CPU core (Verilog) for an IHP SG13G2 ASIC tapeout via OpenROAD, with a genuinely FPGA-proven Radiona ULX3S build	ECP5 85F (fpga-test/Makefile: nextpnr-ecp5 –85k –package CABGA381), FPGA-proven per README; also IHP SG13G2 130nm (NOT ECP5, ASIC silicon process) via OpenROAD, ASIC/design/config.mk	both: open FPGA flow (yosys+nextpnr-ecp5+ecppack+fujprog via oss-cad-suite) and OpenROAD RTL-to-GDSII ASIC flow (IHP-Open-PDK); cocotb+Icarus for verification on both ASIC/src/ and cocotb-testbench/ copies	Verilog (8: cpu.v/include.v vendored 3x across ASIC/src, cocotb-testbench, fpga-test, plus fpga-test/top.v), Python (1: test_cpu.py)	none found	? → 2025-04-15, ?	none
danodus__ecp5_hdmi_audio_video	ULX3S/IcePi Zero: HDMI audio+video transmitter core (TMDS, packets, ECP5 serializer) with a color-bars+440Hz-tone demo test app for both boards	85F (ULX3S, CABGA381, –85k) and 25F (IcePi Zero, CABGA256, –25k)	open (yosys+nextpnr-ecp5+ecppack via oss-cad-suite)	Verilog (21 .v: 11 in rtl/, 2 shared test-app generators in boards/common/, 4 each in boards/ulx3s/ and boards/icepi_zero/)	MIT (LICENSE file: Copyright (c) 2026 Daniel Cliche, Copyright (c) 2019 Sameer Puri)	? → 2026-05-19, ?	hdl-util/hdmi (Sameer Puri, MIT/Apache-2.0), ECP5 serializer adapted from BrunoLevy/learn-fpga ULX3S_hdmi examples
daveshah1__pmods	pmods: David Shah’s collection of PMOD daughterboard hardware designs (KiCad/gerber) plus two small iCE40 LCD-parallel-interface Verilog demos	iCE40 HX8K (NOT ECP5) - device inferred from arachne-pnr -d 8k / icetime -d hx8k (lcd_test/Makefile), no explicit package in .pcf; also iCE40 UP5K (NOT ECP5) - SG48 (lcd_test_icebreaker/Makefile: –up5k –package sg48)	both: open (yosys+arachne-pnr+icepack, lcd_test/Makefile) and open (yosys+nextpnr-ice40+icepack, lcd_test_icebreaker/Makefile)	Verilog (6 files: lcd_test/{lcd_test,lcd_pll,video}.v and lcd_test_icebreaker/{lcd_test,lcd_pll,video}.v); rest of repo is KiCad schematics/PCB/gerber (csi, dacpmod, pmod_lcd35 dirs, no HDL)	none found (no LICENSE file at any depth)	? → 2019-09-19, ?	none
daveshah1__prjtrellis-dvi	Project Trellis DVI: simple VGA-to-DVI/TMDS test-pattern example for ULX3S, dual open-toolchain/Diamond flow	12F default (FPGA_SIZE ?= 12 in both trellis and diamond mk; project.ldf device LFE5U-12F-6BG381C)	both; prjtrellis/yosys+nextpnr-ecp5 via ulx3s_trellis.mk, and Lattice Diamond diamondc via ulx3s_diamond.mk	Verilog (9 .v), VHDL (6)	none found (no LICENSE/COPYING)	? → 2019-01-20, ?	none
detegr__ulx3s-projects	Detegr/ulx3s-projects: personal ULX3S experiments — digital-video signal generation + a “box” blink/test project	25F (nextpnr-ecp5 –25k)	open	Verilog (11)	CC-BY-4.0	? → 2019-02-27, ?	none
dibyx__flux	flux GPU v2.0: educational SystemVerilog GPU (compute + graphics pipeline: shader core, rasterizer, VGA output) targeting ULX3S FPGA and, later, ASIC tape-out	ECP5 85F (hw-tools/fpga/Makefile: DEVICE=85k PACKAGE=CABGA381); also ASIC (NOT ECP5/FPGA) via hw-tools/asic/Makefile (OpenLane + SkyWater sky130A, unrun placeholder)	open (yosys synth_ecp5 + nextpnr-ecp5 + ecppack, hw-tools/fpga/Makefile); ASIC path uses OpenLane/SkyWater (not run)	SystemVerilog (12 files), Python (11, firmware/graphics driver+demo scripts)	CERN-OHL-S v2 (hardware, LICENSE), Apache-2.0 (software), CC-BY-SA (docs)	? → 2026-02-09, ?	none
dicethrow__amaram	amaram: Amaranth-HDL Python library providing an async-FIFO SDRAM interface (single- and n-FIFO) for LUNA-style RAM peripherals	ECP5 85F (nextpnr-ecp5 –85k –package CABGA381, build_top.sh)	open (Amaranth -> yosys synth_ecp5 + nextpnr-ecp5 + ecppack + openFPGALoader; build_top.sh/top.ys/top.lpf auto-generated)	Python/Amaranth (20 files), generated Verilog (1 file, top.debug.v)	none found	? → 2022-04-09, ?	none (uses amlib/LUNA conventions; split off an amtest sub-repo per README)
dpks2003__dice_crap_game	Verilog dice/craps game FSM (top, FSM, random generator, 7-seg decoder) — no board integration	unknown	n/a; no LPF, no build script, no board pin constraints found anywhere in repo	Verilog 4 files (one, seven_seg_decoder.v, is 0 bytes/empty)	none found	? → 2024-03-10, ?	none
dstrbad__janestreet-advent-fpga	Neural-network inference engine (Advent of Code 2025 Day 7 solver) on FPGA, written in Jane Street Hardcaml	85F (synth/ulx3s/Makefile DEVICE=85k; README also says ECP5 85K)	open; yosys+nextpnr-ecp5+ecppack via local oss-cad-suite (synth/ulx3s/Makefile)	OCaml/Hardcaml (9 .ml, 8 .mli, generates Verilog), Verilog (2, generated top + testbench glue)	MIT (LICENSE.md, from Jane Street template)	? → 2026-01-15, ?	built from Jane Street’s hardcaml_template_project
dulatello08__neocorefx-dram	neocorefx-dram: minimal 25 MHz SDR SDRAM bring-up scaffold for ULX3S-85F (native + LiteDRAM-generated controller paths, UART diag, BIST)	85F (Makefile DEVICE := 85k; filename ulx3s-85f-min.lpf)	open; yosys synth_ecp5 + nextpnr-ecp5 –85k –tmg-ripup + ecppack –compress –svf; LiteDRAM controller generated via scripts/gen_litedram_clean25.sh	Verilog (15 .v), YAML (21 LiteDRAM config .yml), shell (2 .sh)	none found (no LICENSE/COPYING file)	? → 2026-05-12, ?	none (branch of author’s own NeoCoreFX project family, pruned/minimal variant)
dulatello08__ulx3s-tests	ulx3s-tests: author’s UART-hello-world bring-up test for a personal ULX3S-85F project (toward a larger NeoCoreFX SoC)	85F (Makefile: DEVICE_OPTS := –85k –package CABGA381 –speed 6)	open; yosys (read_verilog -sv + synth_ecp5) + nextpnr-ecp5 –85k + ecppack	SystemVerilog (1 .sv)	GPL-3.0	? → 2025-10-16, ?	none
ecp5-pcie__ecp5-pcie	ECP5-PCIe: PCIe Gen1 x1 endpoint PHY/LTSSM/DLL/TLP stack for the ECP5 SERDES, written in Amaranth HDL	85F ECP5-5G (LFE5UM5G-85F, ECP5 Evaluation Board) – Tests/pcie_adapter.py: device=’LFE5UM5G-85F’, package=’BG381’; other Tests/*.py import amaranth_boards.versa_ecp5_5g	open (Amaranth HDL -> yosys+nextpnr-ecp5 via amaranth_boards platform build); simulation via Amaranth’s built-in sim (Tests/test_pcie_virtual.py, sim_*.py)	Python/Amaranth (71 .py total: 31 under Gateware/, 38 under Tests/)	none found (no LICENSE file; Gateware/setup.py has ‘# TODO license=’’’)	? → 2023-05-16, ?	none (successor to whitequark/Yumewatari per README, not forked)
emard__flearadio	FleaRadio: FM receiver, RLC + LVDS comparator as 1-bit ADC	n/a (XP2-8E, MachXO2-7000HE)	diamond	VHDL	mixed BSD (emard headers) + LGPL-2.1-or-later (opencores FM core); no LICENSE file	2015-12-25 → 2015-12-26, 13	none (FleaFPGA port)
emard__ledstrip	ledstrip: example VHDL WS2812B RGB LED strip driver with pushbutton colour-cycle demo (ROM colour sequence)	Lattice XP2 (NOT ECP5) - ulx2s.lpf / FleaFPGA_2v5 toplevel use rtl/lattice/lfxp2pll*.vhd (XP2-specific PLL wrappers); the driver itself (rtl/generic/ws2812b.vhd) is plain parametrized VHDL with no vendor primitives and would synthesize unchanged on ECP5/ULX3S (clk_Hz generic defaults to 25000000, matching the ULX3S clock)	Lattice Diamond (rtl/proj/lattice/common/build.tcl / build.sh, project.ldf / FleaRadio.ldf) - closed-source flow, no open-toolchain Makefile target found	VHDL (7 files)	none found (no LICENSE file; rtl/generic/ws2812b.vhd itself has no header; rtl/lattice/ulx2s_toplevel.vhd and FleaFPGA_2v5_toplevel.vhd carry LGPL-2.1+ header comments)	? → 2016-02-10, ?	none
emard__rdsfpga	RDS FM transmitter (107.9 MHz, no external parts)	n/a	diamond (+Quartus)	VHDL, Verilog, C	BSD in headers (no LICENSE file); genmsg C from PiFmRds GPL-3.0	2015-07-22 → 2015-08-03, 105	none
emard__synthowheel	Synthowheel: polyphonic additive synth, 128 gen x 9 harmonics, SPDIF + sigma-delta	45F	diamond	VHDL	BSD (LICENSE.txt AUTHOR=EMARD LICENSE=BSD)	2017-10-29 → 2019-10-24, 77	none
emard__tinyfpga-bootloader-ulx3s	Port of a 60MHz fork of the TinyFPGA Bootloader to the ULX3S board	85F (makefile.trellis and makefile.diamond both set FPGA_SIZE=85)	both; makefile.trellis (yosys+nextpnr-ecp5+ecppack) and makefile.diamond (Lattice Diamond diamondc) alternate flows both present	Verilog (1 .v), some vendored SystemVerilog (1 .sv)	none found	? → 2021-10-01, ?	fork of phdussud/TinyFPGA-Bootloader (60MHz variant)
emard__ulx3s-emi	emard/ulx3s-emi: ULX3S electromagnetic-interference (EMI) demo/test core (ESP32/GPDI/SDRAM/ADC toggled via DIP switches)	12F default (FPGA_SIZE=12)	both (trellis + diamond makefiles)	Verilog (7), VHDL (4), SystemVerilog (1)	none found	? → 2021-10-22, ?	none
emard__ulx3s-jtagthru	emard/ulx3s-jtagthru: ULX3S JTAG pass-thru core (use one ULX3S as a USB-JTAG programmer for another board)	25F (FPGA_SIZE=25 in makefile.trellis)	both	Verilog (1)	none found	? → 2019-01-28, ?	none
emard__ulx3s-passthru	ESP32 passthru: FTDI serial -> ESP32, ESP32 gets OLED/buttons	12F default (12/25/45/85 via FPGA_SIZE)	both (diamond mk + trellis mk with vhdl2vl)	VHDL	BSD (headers; no LICENSE file)	2018-09-18 → 2020-01-02, 31	none
emeb__iceradio	iceRadio: STM32F303 + iCE5LP4K HF/VHF SDR (rxadc_2 DDC: tuner->CIC->FIR, 40MSPS 10-bit ADC -> 19kSPS 16-bit I/Q via I2S)	iCE5LP4K (NOT ECP5) - SG48 (rxadc_2_syn.prj: set_option -part iCE5LP4K -package SG48)	diamond (Lattice iCEcube2/Synplify via rxadc_2_sbt.project + rxadc_2_syn.prj); no open-source flow	Verilog (14 .v), Python (7, coeff/sim generator scripts)	MIT (LICENSE)	? → 2017-03-22, ?	none (first generation of emeb’s DDC lineage; predates rpi_rxadc and OrangeCrab-Litex-ADC)
emeb__orangecrab-litex-adc	OrangeCrab Litex ADC: LiteX/Migen SoC SDR gateware for the OrangeCrab ADC FeatherWing (DDC->demod->PDM audio out), C firmware CLI	ECP5 25F (NOT ULX3S) - CSFBGA285 (hw/OrangeCrab-bitstream.py: device default "25F", litex_boards.platforms.orangecrab)	open; LiteX/Migen -> yosys+nextpnr-ecp5+ecppack via Trellis, dfu-util flash (hw/load.sh)	Verilog (12 .v excl. vendored deps), Python (5, LiteX/Migen), C (11, fw/)	MIT (LICENCE.md, Gregory Davill copyright)	? → 2020-09-17, ?	none (LiteX gateware behind the already-catalogued emeb__orangecrab_adc hardware/gateware repo, same AD9203 board)
emeb__orangecrab_adc	OrangeCrab ADC FeatherWing: AD9203 10-bit/40MSPS ADC + audio board, gateware for SDR tuning/AM demodulation (parallel Verilog + nMigen flows)	25F (LFE5U-25F-6BG285, –25k –package CSFBGA285, gateware/verilog/trellis/Makefile) - OrangeCrab r0.2 Feather	open (yosys+nextpnr-ecp5+ecppack, dfu-suffix/dfu-util flash); parallel Python/nMigen flow builds the same design (gateware/nmigen/top.py)	Verilog (16 .v, gateware/verilog/), Python (nMigen, ~13 .py, gateware/nmigen/)	none found	? → 2020-08-18, ?	none
emeb__rpi_rxadc	RPi RXADC gateware: iCE40UP5K digital down-converter (DDC) for a Raspberry Pi HF/VHF direct-sampling SDR HAT (icehat), decimating a 50 MSPS 14-bit ADC input to 24.414 kSPS I/Q	iCE40 UP5K (NOT ECP5) - SG48 (DEVICE = up5k, PACKAGE = sg48, gateware/icehat_rxadc/icestorm/Makefile)	open (icestorm: yosys synth_ice40 -dsp + nextpnr-ice40 –pre-pack SDC + icepack, gateware/icehat_rxadc/icestorm/Makefile); separate icarus/Makefile for iverilog simulation	Verilog (16 .v: gateware/icehat_rxadc/{icestorm,src}), C (27 .c/.h: software/audio_fulldup RPi driver + software/ice_tool), Python (5: system/ddc.py model + tools)	MIT (LICENSE)	? → 2020-07-18, ?	none
enjoy-digital__liteiclink	LiteICLink: Migen/LiteX inter-chip link cores - generic ECP5 SerDes (DCUA, 8b10b/PRBS) + SerWB soft link (incl. ULX3S) + Xilinx/Efinix transceivers	45F/85F ECP5-5G (LFE5UM5G, Versa bench/serdes/versa_ecp5.py, ECPIX-5 bench/serdes/ecpix5.py; serdes_ecp5.py = DCUA wrapper, 8b10b/PRBS). ULX3S 12F-85F via SerWB bit-banged link (LVCMOS, NOT hard SERDES: bench/serwb/ulx3s.py). Also Xilinx 7-series/UltraScale(+) and Efinix Trion/Titanium (serwb/efinixserdes.py).	open (trellis default in bench/serdes/{versa_ecp5,ecpix5}.py and bench/serwb/ulx3s.py); Xilinx benches use Vivado; Efinix path uses Efinity (not built here).	Python (53, Migen/LiteX; no .v/.sv sources)	BSD-2-Clause (LICENSE)	? → 2026-09-28, ?	none
enjoy-digital__litesata	LiteSATA: Migen/LiteX SATA host core (link/transport/command/BIST); ECP5 Gen2 PHY (SerDesECP5+OOB) validated on ECPIX-5, also Xilinx PHYs	45F/85F ECP5-5G (LFE5UM5G, ECPIX-5, bench/ecpix5.py –device; ecp5sataphy.py uses liteiclink DCUA SerDes). Also Xilinx 7-series/UltraScale(+) PHYs (a7/k7/gth3/gth4/gty4/gthe4/usp/us sataphy.py) via kc705/kcu105/genesys2/nexys_video/zcu102/acorn/xcu1525 benches.	open (LiteX Builder, toolchain="trellis" default in bench/ecpix5.py -> yosys+nextpnr-ecp5+ecppack); Xilinx benches use Vivado (toolchain arg).	Python (58, Migen/LiteX; no .v/.sv sources)	BSD-2-Clause (LICENSE)	? → 2026-09-28, ?	none
eringr__nmigen_fibonacci	nmigen_fibonacci: single-file nMigen toy processor computing a Fibonacci sequence, button-driven, LED output, for ULX3S ECP5-85F	ECP5 85F (fib.py: from nmigen_boards.ulx3s import ULX3S_85F_Platform)	open: nmigen_boards ULX3S platform wraps yosys+nextpnr-ecp5+ecppack; do_program=True also invokes openFPGALoader	Python/nMigen (1 file, 148 lines)	none found	? → 2021-10-13, ?	none
fm4dd__pmod-charlcd	CharLCD PMOD: HD44780 character-LCD PMOD hardware (KiCad + Gerbers) with Verilog display/driver examples for IceBreaker, ULX3S and GateMate	ECP5 85F (examples/ulx3s/display/Makefile: DEVICE=85k PACKAGE=CABGA381); also iCE40 (NOT ECP5) via icebreaker.pcf (examples/icebreaker/*); also GateMate (NOT ECP5, Cologne Chip) via examples/gatemate/{config.mk,gatemate.ccf} using synth_gatemate	open for ULX3S/IceBreaker (yosys+nextpnr-ecp5/nextpnr-ice40+ecppack/icepack); GateMate uses YosysHQ synth_gatemate + Cologne Chip’s p_r place&route + openFPGALoader	Verilog (14 files)	CERN-OHL v1.2 (hardware, LICENSE)	? → 2024-02-24, ?	none
gage1999__fpga-sdr-receiver	fpga-sdr-receiver: ECP5 iCESugar-Pro SDR (FM+RDS) with a 256-pt radix-2 FFT feeding a spectrum/waterfall LCD; also has Pico 2W and PlutoSDR targets	ECP5 LFE5U-25F-6BG256C (iCESugar Pro; icesugar_pro/top.lpf header, icesugar_pro/Makefile synth_ecp5/nextpnr-ecp5/ecppack); also targets a PlutoSDR (Xilinx Zynq, NOT ECP5) via plutosky/ host code and a Raspberry Pi Pico 2W (pico2w/, not an FPGA)	open (yosys synth_ecp5 + nextpnr-ecp5 + ecppack); icesugar_pro/Makefile:52,55,59 (yosys -p “synth_ecp5 …”, nextpnr-ecp5, ecppack)	SystemVerilog (63 .sv, icesugar_pro/src+tb), Verilog (1), C (36, host/pico2w/plutosky/shared), C++ (3), Python (4)	MIT (LICENSE)	? → 2026-09-08, ?	none
gatecat__trellisboard	TrellisBoard: WIP PCIe-card-form-factor ECP5 dev board (KiCad PCB) with a minimal LED demo bitstream and a LiteX platform definition	ECP5 LFE5UM5G-85F (CABGA756) - largest ECP5 (README “Largest ECP5; LFE5UM5G-85F”; gateware/simple/Makefile: nextpnr-ecp5 –um5g-85k –package CABGA756)	open (yosys synth_ecp5 + nextpnr-ecp5 + ecppack, SVF via openocd, gateware/simple/Makefile); also a LiteX platform file (gateware/litex/trellisboard.py, LatticePlatform) for LiteX-based SoC builds	Verilog (2 .v: demo.v, led_ctrl.v), Python (1 file, 271 lines: LiteX platform def); rest of repo is KiCad schematics/PCB (not HDL)	Modified ISC License (COPYING, hardware design + software), (c) 2018-2019 David Shah	? → 2019-07-04, ?	none
ghaworth__ulx3s-tinyai	Single SDRAM initialization module (presumably first building block toward an on-ULX3S tiny-AI/ML accelerator project); otherwise unstarted	unknown (no board target files at all)	n/a; no build script, no LPF, no Makefile in repo	Verilog 1 file (sdram_init.v)	404: Not Found (LICENSE file literally contains a GitHub ‘404: Not Found’ HTML/text page — not a real license)	? → 2026-07-16, ?	none
gojimmypi__ttgf-uart-fsm-trng-lab	Tiny Tapeout ttgf-UART-FSM-TRNG-Lab: UART/SPI-controlled TRNG ASIC project (GlobalFoundries 180) with a ULX3S FPGA test harness	85F default (Makefile DEVICE ?= 85k; commented-out DEVICE ?= 25k / 45k overrides also supported)	open; yosys (YOSYS_DEFS incl. -DULX3S) + nextpnr-ecp5 + ecppack, via ulx3s_build.sh; also has an ice40/ dir for a separate iCE40 flow	Verilog (18 .v), shell (22 .sh), Python (9 .py)	Apache-2.0	? → 2026-06-20, ?	companion of gojimmypi/ttsky-uart-fsm-trng-lab (Sky130 variant, developed in parallel); near-identical to ttgf0p3 milestone copy
gojimmypi__ttgf0p3-analog-uart-fsm-trng-lab	UART/SPI TRNG+FSM digital wrapper for a Tiny Tapeout GF180 analog ASIC lab, with an ULX3S FPGA test harness	85F default (DEVICE ?= 85k; Makefile also supports 25k/45k/85k override)	open (yosys+nextpnr-ecp5+ecppack via ulx3s/Makefile; also verilator lint)	Verilog (19 .v), Python (15, test scripts), Shell (28)	Apache-2.0	? → 2026-07-02, ?	derived from TinyTapeout ttsky-analog-template / ttsky-verilog-template / ttgf-verilog-template (per ATTRIBUTION.md)
gojimmypi__ttgf0p3-uart-fsm-trng-lab	Tiny Tapeout ttgf0p3-UART-FSM-TRNG-Lab: experimental GF ttgf0p3(Analog) shuttle copy of the ttgf UART/SPI TRNG ASIC lab, with ULX3S test harness	85F default (Makefile DEVICE ?= 85k; 25k/45k overrides available)	open; yosys (-DULX3S) + nextpnr-ecp5 + ecppack via ulx3s_build.sh; separate ice40/ flow also present	Verilog (18 .v), shell (22 .sh), Python (9 .py)	Apache-2.0	? → 2026-06-27, ?	near-identical milestone copy of gojimmypi/ttgf-uart-fsm-trng-lab (README: “identical … other than a different version text”)
gojimmypi__ttsky-uart-fsm-trng-lab	Tiny Tapeout ttsky-UART-FSM-TRNG-Lab: actively-developed Sky130 UART/SPI TRNG ASIC lab (superset of ttgf, adds dedicated UART core + hw test suite), with ULX3S harness	85F default (Makefile DEVICE ?= 85k; 25k/45k overrides available)	open; yosys (-DULX3S) + nextpnr-ecp5 + ecppack via ulx3s_build.sh; separate ice40/ flow also present	Verilog (17 .v), shell (14 .sh), Python (8 .py)	Apache-2.0	? → 2026-06-07, ?	companion/superset of gojimmypi/ttgf-uart-fsm-trng-lab (Global Foundry 180 milestone copy); this Sky130 repo is the active-development lead per its README
gojimmypi__ulx3s-adda	ULX3S-ADDA: AN108 AD9280/AD9708 adapter docs + test gateware	12F	open	Verilog	none found	2019-03-15 → 2019-03-16, 10	none (origin)
goran-mahovlic__gpdi_mirror	GPDI mirror: TMDS from PMOD gp9..12 re-driven to GPDI	unknown	unknown (no build files)	Verilog	none found	2020-01-04 → 2020-01-04, 2	none
goran-mahovlic__odysseus_sprites	ULX3S sprite-rendering sample (HDMI/VGA video with sprite ROM), dual open/Diamond build via shared trellis/diamond .mk scripts	unknown (no explicit –Nk / device size flag found in Makefile/scripts snippets read; only NEXTPNR_OPTIONS = –timing-allow-fail –speed 7 seen)	both; open (scripts/trellis_main.mk / trellis_main_sv.mk / trellis_main_ghdl.mk: yosys+nextpnr-ecp5+ecppack) and Diamond (scripts/diamond_main.mk + project.ldf + ulx3s_*.xcf)	Verilog (9 .v), SystemVerilog (1 .sv, ecp5pll.sv)	MIT	? → 2024-07-29, ?	none
gornjas__dvi_test	Minimal DVI/TMDS video-out test for ULX3S (VHDL)	12F (Diamond .ldf device=LFE5U-12F-7BG381C)	both (Diamond project ulx3s_dvi_test.ldf targets LFE5U-12F; ulx3s_fer.lpf pinout also usable with an open nextpnr-ecp5 flow)	VHDL (7 files)	BSD-2-Clause	? → 2025-03-02, ?	none
greatscottgadgets__amalthea	Amalthea: experimental Amaranth SDR gateware (IQ receiver, CORDIC demod, FFT) for a LUNA-based ECP5+AT86RF215 USB SDR board, with GNURadio blocks	ECP5 (package/size not stated in this repo) - confirmed via ECP5-only Amaranth Instance(“DELAYG”)/Instance(“IDDRX1F”) primitives in amalthea/gateware/radio.py:169-181; the platform class is luna.gateware.platform.get_appropriate_platform() (amalthea/gateware/device.py:22), i.e. lives in greatscottgadgets/luna	open (Amaranth HDL -> yosys+nextpnr-ecp5 via LUNA’s build_and_upload/top_level_cli flow); no local .lpf/platform file in this repo	Python/Amaranth (18 .py: 9 gateware, 4 gnuradio blocks, 3 tests, setup.py)	BSD-3-Clause (LICENSE)	? → 2023-02-07, ?	none (uses LUNA as a platform/USB library dependency, not a source fork)
greatscottgadgets__hackrf	HackRF firmware/fpga: Amaranth DSP gateware for the HackRF Pro (‘Praline’) baseband, iCE40UP5K - CIC, half-band FIR, NCO, complex mixer and DC-block chains for SDR RX/TX (MCU firmware and hardware NOT catalogued here, per task scope)	iCE40 UP5K (NOT ECP5) - SG48 (device="iCE40UP5K", package="SG48", firmware/fpga/board.py: PralinePlatform(LatticeICE40Platform))	Amaranth -> yosys/nextpnr-ice40 (amaranth.vendor.LatticeICE40Platform build flow, firmware/fpga/board.py/build.py); no Makefile in firmware/fpga, built by running build.py	Python/Amaranth (31 .py under firmware/fpga, catalogue scope); repo overall also has C MCU firmware (out of scope) and KiCad hardware (out of scope)	Repo-wide COPYING is GPL-2.0; firmware/fpga/*/.py carry their own SPDX BSD-3-Clause headers (e.g. board.py, dsp/nco.py, dsp/cic.py)	? → 2026-09-17, ?	none (catalogue entry scoped to firmware/fpga only)
greatscottgadgets__luna	LUNA: Amaranth USB 2.0/3.0 gateware framework (device/host/analyzer cores, PHY interfaces, applets), portable to many FPGA boards incl. ECP5	25F (LFE5U-25F, IDCODE 0x21111043, –25k –package CABGA256, examples/blinky_verilog/Makefile) - only concrete part in this clone; luna/gateware/ itself is platform-parametric, used on ECP5 boards (Cynthion LFE5U-12F, ECPIX-5, OrangeCrab, Nereid…) via external luna-boards defs, plus iCE40/Xilinx boards	open (Amaranth build backend: yosys+nextpnr-ecp5+ecppack for ECP5 targets, invoked via luna.top_level_cli/Amaranth build system); examples/blinky_verilog also ships a plain Makefile (yosys+nextpnr-ecp5+ecppack) as a toolchain-agnostic sanity check	Python/Amaranth (163 .py: 116 luna/gateware/, 26 tests/, 17 examples/, 3 applets/), Verilog (1 .v: examples/blinky_verilog/blinky.v)	BSD-3-Clause (LICENSE, root; per-file SPDX headers, e.g. examples/blinky/blinky.py)	? → 2026-08-19, ?	none
hariharan6307-coder__verilog-goertzel-audio-visualizer	verilog-goertzel-audio-visualizer: 8-band Goertzel spectrum analyzer with peak-hold + log bar scaler, fully sim-verified	unknown (NOT ECP5) - apio.ini board=”Soan-Papdi” is not a real apio board (checked local apio boards.json); no .pcf/.lpf; FPGA family/device not verifiable from this clone	apio (apio.ini board=Soan-Papdi, not a real apio board; no evidence of an actual build in this clone)	Verilog (10 .v: goertzel/spectrum/peak_hold/bar_scaler/visualiser_core + SubFolder tb + top-level tb)	none found	? → 2026-07-31, ?	none
harrowm__mackerel_030f	Mackerel-030F: FPGA SoC wrapping the external MH030 cycle-accurate MC68030 core (full 68020+ ISA, MMU, caches) with real ULX3S-85F board integration	ECP5 85F (ULX3S-85F, README + pld/mackerel-030f/ulx3s_v20.lpf); plan.md documents why ULX3S-85F was chosen over Tang Nano 20K/DE10-Nano	open only; Yosys+Project Trellis+nextpnr-ecp5+openFPGALoader via oss-cad-suite (README explicitly rejects Lattice Diamond)	Verilog (5 own: mackerel_030f.v, clk_pll.v, sdram_adapter.v, spi.v, uart.v); MC68030 core itself (MH030, SystemVerilog) is external and not present in this clone	MIT (LICENSE, Copyright 2026 Malcolm Harrow)	? → 2026-09-23, ?	none (SoC/board-integration layer around the separate harrowm/MH030 and harrowm/mh882 core repos, fetched not vendored)
hdl4fpga__hdl4fpga	hdl4fpga: portable VHDL library, ScopeIO oscilloscope, SDRAM graphics, eth/USB links	12F	diamond (no yosys/nextpnr flow in repo; only a GHDL syntax-check script)	VHDL (274), Verilog, JS	MIT (LICENSE; every HDL file checked is MIT); GPL-3.0-or-later appears only in Diamond build Makefiles, not in sources (docs/projects/hdl4fpga__hdl4fpga.md)	2013-06-05 → 2025-08-17, 11860	none
ipmgroup__fftd	ice40-fft: SPI-attached 1024-point radix-2 DIT FFT accelerator for a Raspberry Pi HAT (ICE40HX4K); planned Linux driver/libfft.so absent from clone	iCE40 HX4K (NOT ECP5) - TQ144 speed5 (config.mk FPGA_DEVICE=ice40hx4k FPGA_PACKAGE=tq144; hardware/synth/build_scripts/pnr.sh: –hx4k –package tq144 –speed 5)	open (yosys synth_ice40 + nextpnr-ice40 + icepack); hardware/synth/build_scripts/{synth.sh,pnr.sh,pack.sh}	Verilog (41 .v incl. 6 test .v), Python (23, host/bench/plot scripts), C (2)	MIT (LICENSE); root file hw is a copied ZipCPU dblclockfft header under LGPL-3.0 (Gisselquist Technology) - see notes	? → 2026-06-04, ?	none (root file hw is a leftover generated header from ZipCPU’s dblclockfft, see notes)
jamchamb__cojiro	iCEBreaker: Nintendo JoyBus device emulator - simulates an N64 controller with ephemeral Controller Pak, a Pokemon Snap Station, and a USB host mode for controller/Transfer Pak I/O	iCE40 UP5K (NOT ECP5) - SG48 package (–up5k –package sg48 –freq 12, Makefile)	open (yosys+nextpnr-ice40+icepack)	Verilog (10 .v: 8 own - top.v, top_snapstation.v, top_uart_host.v, n64_sender.v, n64_receiver.v, mempak.v, datacrc_8wide.v, seven_seg.v; 2 from osdvu submodule), Python (9, host tools in software/)	none found at repo root (no LICENSE file, README does not mention one); osdvu submodule itself is MIT (osdvu/LICENCE)	? → 2022-10-21, ?	none (vendors cyrozap/osdvu UART core as a git submodule)
jamesrosssharp__1_bit_am	jamesrosssharp/1_bit_AM: 1-bit oversampling-ADC AM radio transceiver experiment, targets ULX3S (and iCE40)	85F (FPGA_SIZE=85, lfe5u-85f, CABGA381)	open	Verilog (25)	MIT	? → 2024-09-28, ?	none
jamesrosssharp__ulx3s_mixer_pcb	100MHz PLL + RF mixer/demodulator PMOD board, with matching ULX3S SDR receiver HDL	85F (FPGA_SIZE = 85 default)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (26 .v), Python (12, filter/table generator scripts)	MIT-style notice in hdl/LICENSE.txt only (no repo-root LICENSE)	? → 2024-08-25, ?	HDL based on hackaday.io “FPGA 3-R-1-C mW SDR receiver” by Alberto Garlassi
joaln27__cordic	CORDIC-1: bit-serial CORDIC engine (TinyTapeout Sky130 ASIC) swept by a DDS as a sigma-delta sine generator; hardware-verified bit-exact on ULX3S 85F	ECP5 85F (fpga/ulx3s.lpf, README: ‘Verified on a real ULX3S 85F’); primary target is TinyTapeout SkyWater 130nm ASIC (NOT ECP5, ASIC shuttle)	open; the ASIC RTL is instantiated UNCHANGED on the FPGA (fpga/ulx3s_top.sv comment); Yosys+nextpnr-ecp5+ecppack+openFPGALoader for the FPGA harness, Yosys+OpenROAD(LibreLane)+SymbiYosys+Icarus/cocotb for the ASIC/formal/sim flow	SystemVerilog (6: src/{cordic.sv,project.sv}, fpga/{ulx3s_top.sv,synth-related}, fpga/meter/{meter_core.sv,ulx3s_meter.sv,tb_meter.sv})	Apache-2.0 (LICENSE; SPDX header in src/cordic.sv and src/project.sv)	? → 2026-09-25, ?	none
johnazoidberg__ulx3s-espi-analyzer	JohnAZoidberg/ulx3s-espi-analyzer: passive eSPI bus sniffer/analyzer for ULX3S (decodes POST codes, virtual wires, ACPI EC, 8042 KBC traffic)	12F default (flake.nix defaultSize=”12”); also builds 25/45/85	open (yosys+nextpnr-ecp5 via flake.nix/Makefile)	Verilog (13), SystemVerilog (1, ecp5pll.sv)	none found repo-wide (README notes ecp5pll.sv is BSD-licensed by EMARD)	? → 2026-03-08, ?	none
kazkojima__litex-lattice-ecp5-evn	LiteEth SGMII PHY (DCU ‘GBE’ mode) + litex-boards/linux-on-litex-vexriscv patches for SDRAM+SGMII addons on the ECP5-5G Evaluation Board	85F ECP5-5G (LFE5UM5G-85F, ECP5 Evaluation Board) – README: ‘Lattice LEF5UM5G-85G board’ [sic]; patch targets litex-boards lattice_ecp5_evn platform	open (LiteX -> yosys+nextpnr-ecp5+ecppack via patched litex-boards)	Python/Migen (1 file, ecp5sgmii.py, 749 lines) + 2 unified-diff patches	BSD-2-Clause (liteeth/ecp5sgmii.py file header, LiteEth/Florent Kermarrec); repo itself: none found (no LICENSE file)	? → 2021-05-25, ?	none (patches against enjoy-digital/litex-boards and litex-hub/linux-on-litex-vexriscv, not a fork clone of either)
kbeckmann__tt08-flame	TT08-Flame: Tiny Tapeout demoscene ASIC entry (fire/plasma visual + PDM voice audio), with a ULX3S FPGA companion port	ECP5 (ULX3S; ulx3s/Makefile sets DEVICE=85k, nextpnr-ecp5 --85k --package CABGA381 --freq 25 --lpf ulx3s_v20.lpf); primary target is the Tiny Tapeout ASIC shuttle (Sky130/GF180, caravel_template, not an FPGA)	open (yosys -DULX3S -p synth_ecp5 + nextpnr-ecp5 + ecppack, ulx3s/Makefile); ASIC flow via caravel_template/openlane (proprietary PDK flow, not this repo’s toolchain)	Verilog (9 .v incl. ulx3s/top.v,hdmi.v), SystemVerilog (1 .sv: ecp5pll.sv), Python (2, cocotb test infra)	Apache-2.0 (LICENSE)	? → 2024-09-06, ?	none
kelu124__lit3rick	lit3rick: single-channel ultrasound pulse-echo board - UP5K ADC/pulser, on-chip DFT envelope extraction, I2C/SPI/I2S readout (owner’s own board)	iCE40 UP5K (NOT ECP5) - SG48I (verilog/radiant/fft_adc/fft_adc.rdf: device=”iCE40UP5K-SG48I”, performance_grade High-Performance_1.2V; verilog/src/synth.ys: synth_ice40 -top top; top.v instantiates HSOSC/RGB iCE40 primitives)	both: open (yosys synth_ice40, verilog/src/synth.ys - no nextpnr/icepack script found in repo, output is a .blif only) and proprietary Lattice Radiant (verilog/radiant/fft_adc/*.rdf + ip_cores/ IP-catalog cores ebr_dp/sc_fifo/pll_adc/spi_slave, impl_1/ has completed P&R reports and fft_adc_impl_1.bin)	Verilog: 119 .v (verilog/src/rtl ~30 incl. fft/ subdir ~25, radiant/fft_adc IP-core copies, sigprocessing/ duplicate rtl); SystemVerilog: 5 .sv (verilog/src/tb testbenches)	GPL-3.0-or-later (gateware/software, Readme.md ## License); hardware TAPR-OHL-1.0 (TAPR.txt); docs CC-BY-SA-3.0 (Readme.md); per-file exceptions: MIT (verilog/src/rtl/i2c_slave_axil_master.v, (c) 2019 Alex Forencich, header) and OpenCores/no SPDX (verilog/src/rtl/spi_slave.v, opencores.org spi_verilog_master_slave project, Santhosh G)	? → 2024-07-13, ?	none
kelu124__un0rick	un0rick: single-channel open ultrasound imaging board - pulser/ADC acquisition FPGA gateware + SPI control interface (repo owner’s own HX4K board)	iCE40 HX4K (NOT ECP5) - TQ144:4K (usb/verilog/impl/icestorm/run_impl: nextpnr-ice40 --hx8k --package tq144:4k; the :4k package suffix is nextpnr’s way of targeting the HX4K-binned die, matching the HX4K-TQFP144 spec in README); also targeted via proprietary Lattice iCEcube2 (vhdl/MATTY_Implmnt/, usb/verilog/impl/icecube2/) for a VHDL variant of the same chip	both: open (yosys synth_ice40 + nextpnr-ice40 + icetime + icepack, usb/verilog/impl/icestorm/run_impl) and proprietary Lattice iCEcube2 (vhdl/MATTY_Implmnt/, usb/verilog/impl/icecube2/un0rick_sbt.project) for VHDL matty_main.vhd	Verilog: 40 .v (usb/verilog/src/rtl ~20, src/beh behavioural sim models ~6, src/tb testbenches 12); VHDL: 30 .vhd (vhdl/, iCEcube2 MATTY variant)	GPL-3.0-or-later (software/gateware, per README ## License section); hardware TAPR-OHL-1.0 (LICENSE.txt); docs CC-BY-SA-3.0 (README)	? → 2025-01-19, ?	none
krishkc5__trng-ring-oscillator	True Random Number Generator using ring oscillators, SystemVerilog + Verilator/cocotb sim, Python entropy analysis	85F (Makefile default 85k, note: change for 12F/25F/45F)	open: yosys+nextpnr-ecp5+ecppack+openFPGALoader; also verilator+cocotb for sim	SystemVerilog (4 .sv), C++ (1 verilator tb), Python (4, sim/analysis)	none found	? → 2026-02-08, ?	none
l0r3m1psum__videogame_verilog	Breakout-style video game in Verilog (HDMI/TMDS output), following ‘Designing Game Hardware in Verilog’ book	85F (nextpnr –85k in build.sh)	open: yosys+nextpnr-ecp5+ecppack+fujprog via build.sh	Verilog (1 .v, single monolithic file incl. hvsync_generator_hdmi, TMDS_encoder, ecp5pll)	none found	? → 2025-07-22, ?	none
lawrie__fpga_pio	fpga_pio: RP2040 PIO (programmable I/O state machine) reimplementation, with ULX3S makefile target	85F (DEVICE ?= 85k)	open; yosys synth_ecp5 + nextpnr-ecp5 + ecppack	Verilog (34 .v), assembly (13 .asm PIO programs)	BSD-2-Clause	? → 2023-05-03, ?	none
lawrie__ice40logicsniffer	Open Bench Logic Sniffer (SUMP) port, 100 MHz	12F (built –25k, idcode 12F)	open	Verilog	GPL-2.0-or-later (headers)	2018-02-05 → 2019-12-30, 23	none (OLS port)
lfglabs-dev__lean-silicon	Assurance/verification framework for a Lean-model-derived scalar coprocessor (LSC-1/LSC-1u), targeting ASIC (Tiny Tapeout SKY130) with an FPGA smoke-test/UART harness	85F (docs/ULX3S_SMOKE_AND_UART.md: “FPGA: LFE5U-85F, IDCODE 0x41113043”)	open; yosys+nextpnr-ecp5+ecppack (fpga/ulx3s/Makefile, build_smoke.sh/build_uart.sh)	Python (126, dominant: formal/assurance tooling), SystemVerilog (74, ASIC + FPGA harness RTL), Lean (30, formal spec), plus extensive logs/JSON evidence	Apache-2.0	? → 2026-09-07, ?	none
logoposeidon__ulx3sjukebox	SD-card PCM jukebox / audio player for ULX3S (PWM DAC, 7-button song select)	unknown (no build script committed; only prebuilt bitstream + .config, device not stated)	open (implied; no build script in repo, only prebuilt ulx3s.bit)	Verilog (5 files)	none found	? → 2024-10-19, ?	none
lucysrausch__colorlight-led-cube	Colorlight 5A-75B “LED cube” hack: HUB75e RGB panel driver (up to 6x 64x64) fed over UDP via LiteEth, replaces vendor capture-card firmware	25F (LFE5U-25F-6BG256, –25k –package CABGA256, fpga/syn/Makefile) - Colorlight 5A-75B v7.0	open (yosys+nextpnr-ecp5+ecppack, JTAG SVF flash via openocd/Glasgow) - fpga/syn/Makefile; fpga/liteeth_core.v is generated by the external liteeth_gen tool (LiteX/LiteEth), not vendored source	Verilog (6 .v own; liteeth_core.v is generated, not hand-written)	GPL-3.0 (LICENSE, root)	? → 2023-01-10, ?	none
machdyne__fpga-dac	Machdyne Konfekt/Lakritz/Noir: experimental sigma-delta PCM audio DAC/player that streams 48kHz 16-bit stereo PCM from SPI flash, Verilog for ECP5.	ECP5 12F (Konfekt/Lakritz, CABGA256) and 45F (Noir, CABGA256)	open (yosys+nextpnr-ecp5+ecppack)	Verilog (3 .v)	custom permissive, LICENSE.md, Copyright (c) 2022 Lone Dynamics Corporation, 1-clause BSD-like redistribution	? → 2024-06-17, ?	none
machdyne__tinydfu-bootloader	TinyDFU Bootloader: multi-board USB DFU bootloader (bit-banged USB-to-SPI bridge derived from TinyFPGA Bootloader/tinyfpga_bx_usbserial), Machdyne ECP5 boards plus iCE40/Xilinx variants	ECP5 (Machdyne Lakritz/Obst/Konfekt/Kopflos/Klinge/Minze/Schoko/Kaugummi/Kuchen/Riegel boards, NOT ULX3S) - boards/lakritz/lakritz_v0.lpf etc; also iCE40 (tinyfpga_bx, boards/tinyfpga_bx/pins.pcf) and Xilinx XC7 (arty_a7, boards/arty_a7/arty_a7.xdc)	open (yosys+nextpnr-ecp5+ecppack for the ECP5 boards, e.g. boards/lakritz/Makefile ecppack --bootaddr; yosys+nextpnr-ice40+icepack for tinyfpga_bx); Xilinx flow for arty_a7 (boards/arty_a7/bootloader.tcl)	Verilog (42 .v), Verilog headers (13 .vh, per-board boardinfo.vh), Python (4, constraints.py/make.py)	Apache-2.0 (LICENSE.txt, 202 lines, top-level, applies repo-wide)	? → 2026-09-06, ?	descends from tinyfpga/TinyFPGA-Bootloader via davidthings/tinyfpga_bx_usbserial (README.md “Origins”); Machdyne/Lone Dynamics added the ECP5 boards
makisness__inductiq	InductIQ: FPGA lock-in amplifier + impedance sweep instrument for eddy-current coil sensing (NCO/DDS excitation, ADC sampling, digital lock-in mixing) on ULX3S	ECP5 85F (ULX3S; apio board=ulx3s-85f, hdl/rtl/apio.ini; hdl/rtl/ulx3s_v20.lpf)	apio (apio.ini -> yosys+nextpnr-ecp5+ecppack for board ulx3s-85f); hdl/synth/synth.ys + sources.f present as an alternate manual yosys script	SystemVerilog (39 .sv), Verilog (6 .v: uart_rx/tx, adc_sampler, adc_spi_master, debouncer, configurable_nco), Python (13: GUI + analysis/sim scripts)	MIT (LICENSE)	? → 2026-09-15, ?	none
marph91__pocket-bnn	pocket-bnn: framework to map Binarized Neural Networks (BNN, trained with LARQ) onto ULX3S FPGA over UART	85F (Makefile: nextpnr-ecp5 –85k –package CABGA381)	open: yosys (ghdl plugin, VHDL toplevel generated from trained model) + nextpnr-ecp5 + ecppack via top-level Makefile	VHDL (21 .vhd, generated+hand-written), Python (21, LARQ model training + playground scripts) + submodule icestick-uart: VHDL (5 .vhd, marph91 UART core)	MPL-2.0; submodule submodules/icestick-uart: MPL-2.0 (LICENSE) - same license family as the main repo, no conflict	? → 2021-06-13, ?	none (own framework, sibling of author’s pocket-cnn project)
marph91__yaaes	YAAES: VHDL AES-128/256 block cipher core (ECB/CBC/CFB/OFB), 8/32/128-bit interface widths	85F (synth.sh: nextpnr-ecp5 –85k –package CABGA381)	open: yosys (ghdl-yosys-plugin for VHDL) + nextpnr-ecp5 + ecppack via syn/synth.sh	VHDL (13 .vhd), Python (8, cocotb testbenches)	LGPL-3.0	? → 2021-08-08, ?	none (own IP core)
mattvenn__fpga-sdft	fpga-sdft: sliding DFT (32-bin) spectrum analyzer, 8-bit ADC in, VGA bar-graph display out (most-starred Lattice FFT repo surveyed, 76 stars)	iCE40 HX8K (NOT ECP5) - CT256 (default DEVICE=hx8k PACKAGE=ct256 in Makefile, arachne-pnr –device 8k –package ct256); also has an iCE40 HX1K icestick pin file hdl/icestick.pcf (not wired into any Makefile target seen)	open (yosys synth_ice40 + arachne-pnr + icepack); Makefile ($(ICESTORM_DIR)/yosys -p “synth_ice40 -top top -blif”, arachne-pnr –device 8k, icepack)	Verilog (11 .v), Python (6, twiddle-factor generation + VCD/model tooling)	none found (no LICENSE/COPYING at any depth, no SPDX header seen)	? → 2020-04-24, ?	none
maxhpc__ecpix-5	ECPIX-5 gateware collection: LEDs, UART, DDR3 top (via ultraembedded core_ddr3_controller), FIFO/DPRAM libs, Vortex-GPU stub design (vx/)	ECP5-5G 85F (LFE5UM5G-85F, CABGA554, ECPIX-5; build.mk: nextpnr-ecp5 --um5g-85k --lpf ../ecpix5.lpf --package CABGA554 --freq 100)	open (sv2v -> yosys synth_ecp5 -> nextpnr-ecp5 -> ecppack, build.mk); vx/tb/Makefile uses Verilator for simulation only, not synthesis	SystemVerilog (11 own .sv: top ecpix5.sv, leds/uart/vx designs, libs), C++ (4 own: vx/sw + vx/tb)	none found (no LICENSE file; no per-file license headers in libs/.sv, uart/.sv, leds/*.sv)	? → 2025-02-09, ?	none
maxzischka1__fastfouriertransformproject	FastFourierTransformProject: 16-point radix-2 single-delay-feedback FFT IP (SB_MAC16 twiddle complex multiplier) with UART I/O, for iCE40 UP5K	iCE40 UP5K (NOT ECP5) - SG48 (Makefile: DEVICE=up5k PACKAGE=sg48; synth_ice40 -device u)	open (yosys synth_ice40 + nextpnr-ice40 + icepack; Makefile ~lines 110-125)	SystemVerilog (13 .sv), Python (2, inputsGen.py/twiddleGen.py Q1.15 stimulus generators), C++ (4, Verilator testbench harnesses)	none found (no LICENSE/COPYING at any depth)	? → 2026-09-28, ?	none
mb-sat__ulx3s-longwave-sdr	mb-sat/ulx3s-longwave-sdr: longwave/VLF direct-conversion SDR receiver for ULX3S 85F (12-bit ADC, Costas loop, FFT waterfall over HDMI)	85F (nextpnr-ecp5 –85k)	open (yosys synth_ecp5 + nextpnr-ecp5 –85k + ecppack)	Verilog (68), Assembly (38, mecrisp-quintus forth), Pascal (6)	GPL-3.0	? → 2025-06-18, ?	none
mebner86__icesugar-pro_sound2fft	iCESugar-Pro sound2fft: real-time audio spectrum analyzer (I2S mic -> FFT -> HDMI) built as 17 incremental step-by-step Verilog projects with CI	25F (LFE5U-25F-6BG256, –25k –package CABGA256, projects/01_blinky/Makefile) - iCESugar-Pro	open (yosys+nextpnr-ecp5+ecppack, icesprog flash) - VS Code Dev Container ships Yosys/nextpnr-ecp5/Trellis/Icarus/Verilator/cocotb; per-project Makefile	Verilog (56 .v)	MIT (LICENSE, root)	? → 2026-04-03, ?	none
meharbaan2__systemverilog-ofdm-phy-core	systemverilog-ofdm-phy-core: fixed-point 64-subcarrier OFDM TX/RX PHY with 64-pt radix-2 FFT/IFFT, QAM mapper, LS channel est.	iCE40 UP5K (NOT ECP5) - SG48 (synth/run_synth.sh: nextpnr-ice40 –up5k –package sg48 –freq 12)	open; yosys (slang plugin, read_slang) + synth_ice40 + nextpnr-ice40 –up5k –package sg48 (synth/run_synth.sh); no icepack/bitstream step	SystemVerilog (20, rtl/+tb/+sim/), Python (2, sim/generate_vectors.py + generate_scoreboard_vectors.py)	none found	? → 2026-06-11, ?	none
mehrdadh__lora-modulator	LoRa modulator: chirp-spread-spectrum LoRa TX (chirp/phase-LUT generator, sin/cos LUT, LVDS I/Q serializer) for the tinySDR board’s AT86RF215	ECP5 25F (NOT ULX3S) - BG256I (lora_tx.ldf: device="LFE5U-25F-6BG256I")	diamond (Lattice Diamond .ldf/.lpf project; project/lora_tx_clarity/my_pll_64mhz generated PLL IP core)	Verilog (17 .v)	NC-AGPL-3.0 (custom Non-Commercial AGPL, LICENSE; non-commercial use only, not an OSI/SPDX license)	? → 2025-02-20, ?	none
mithro__asus-d16-ulx3s-interface	ULX3S LiteX SoC bench-controller bridging RPi5 USB to ASUS KGPE-D16 debug/control connectors (JTAG/UART/SPI-flash/wishbone)	45F (bring-up), aiming to shrink to 12F	open; detail=LiteX SoC planned, no HDL/build present yet	Python 6 (wiring/pinmap tooling only, no HDL files)	Apache-2.0	? → 2026-07-20, ?	none
mole99__tt05-one-sprite-pony	One Sprite Pony: Tiny Tapeout 5 ASIC macro producing SVGA 800x600 output with one sprite; FPGA emulation targets include ULX3S and iCEBreaker	ECP5 (ULX3S, fpga/constraints/ulx3s_v20.lpf); also iCE40 (NOT ECP5) - iCEBreaker (fpga/constraints/icebreaker.pcf); primary target is the Tiny Tapeout 5 ASIC (Skywater 130nm), not an FPGA	open (yosys+nextpnr-ecp5 for ULX3S emulation, implied by fpga/ layout and Makefile sim-* targets; the TT05 ASIC flow itself uses OpenLane, not present in this clone)	SystemVerilog (12), Verilog (5), Python (5, sprite2bit.py + tb_cocotb.py)	Apache-2.0 (LICENSE)	? → 2025-02-09, ?	none
msrraju07__iop	OV7670 camera Sobel edge-detection pipeline on ULX3S with HDMI output, built via Icestudio blocks + generated Verilog	85F (Makefile PART_NEXTPNR=–85k, PART_BASECONFIG=lfe5u-85f)	open: yosys+nextpnr-ecp5+ecppack+fujprog via Makefile; also buildable from Icestudio	Verilog (15 .v)	MIT	? → 2021-11-17, ?	none (by Angelo Jacobo; same author’s Sobel design also cloned separately elsewhere as ULX3S_FPGA_Sobel_Edge_Detection_OV7670)
mysteriouswolf__vna_fpga_dsp	VNA_FPGA_DSP: phase/amplitude detector and RBW (FIR) filter DSP core for MysteriousWolf’s open 8-16 GHz VNA thesis project	iCE40 UP5K (NOT ECP5) - SG48I (device=”iCE40UP5K-SG48I” in VNA_FPGA_DSP.rdf:1)	diamond (Lattice Radiant 2023.2.1.288.0 project VNA_FPGA_DSP.rdf; adc_counter/pll_core are Radiant IPgen black-box IP); no open-source (yosys/nextpnr) flow found	Verilog (28 .v: source/{core,dsp,spi}.v plus Radiant IPgen wrappers/testbenches for adc_counter, pll_core, raw_meas_ram), VHDL (3 unused IPgen template .vhd + 1 stray macOS AppleDouble junk file ‘.Real.Math.vhd’, not real HDL)	none found (no LICENSE/COPYING; no source header)	? → 2025-03-02, ?	none
nh428__ulx3s-tft-display-sobel-object-detection	Camera (OV7670) to TFT display pipeline with Sobel edge detection for flying-object detection, built with Icestudio	85F (Icestudio LPF comment ‘Board: ulx3s-85f’)	open; detail=Icestudio front-end generating Yosys/nextpnr-ecp5/ecppack flow (ice-build/ dir)	Verilog 1 generated top file (from Icestudio visual blocks)	none found	? → 2026-07-27, ?	none
nicocavallu__rf-dds-lo	Direct Digital Synthesizer (DDS) local oscillator for RF/DSP (LoRa de-chirp front-end), Verilog with iverilog testbenches	unknown (ulx3s.lpf present but no nextpnr device flag found in repo; README only lists yosys/nextpnr as deps)	open: yosys+nextpnr-ecp5 (per README prose only; no Makefile/script found), iverilog+gtkwave used for simulation	Verilog (8 .v), Python (1, sine table generator)	none found	? → 2026-08-06, ?	none
nicocavallu__rf-fft-engine	RF-FFT-Engine: only the ping-pong I/Q buffer (2.5x decimation) is implemented; the Radix-2 FFT + peak-bin detector in the README are empty stubs	ECP5 85F claimed only (README: Radiona ULX3S, LFE5U-85F); no board/constraint/build file of any kind present in the clone	unknown (README lists intended tools – iverilog, yosys, nextpnr-ecp5, fujprog – but there is no Makefile or build script in the repo)	Verilog (3 files, but only 1 has code: src/ping_pong_buffer.v is 63 lines; src/radix2_fft.v and src/peak_finder.v are both 0 bytes/empty stubs)	GPL-3.0 (LICENSE, full GNU GPLv3 text)	? → 2026-08-21, ?	none
nicocavallu__rf-sdr-frontend	RF-SDR-Frontend: LoRa-dechirp digital downconverter (mixer+CIC+FIR+dither) using sister repo rf-dds-lo as LO, for ULX3S	ECP5 85F (README: “Radiona ULX3S (Lattice ECP5 LFE5U-85F)”; modules/rf-dds-lo/ulx3s.lpf); claimed, no synth/PnR script targets it in this clone	open (README lists yosys/nextpnr-ecp5/fujprog) but no Makefile/build script present; only iverilog+vvp+gtkwave sim scripts (run_sim.sh, scripts/sdr_frontend_test.sh)	Verilog (18 .v incl. rf-dds-lo submodule)	none found	? → 2026-08-18, ?	none (own IP; vendors sister repo rf-dds-lo as a submodule for the LO)
nkrackow__singularitysurfer-fpga-lock-in-amplifier	SingularitySurfer: FPGA lock-in amplifier (MCP33131D ADC -> mixer x DDS sine/cos -> CIC/IIR filter -> CORDIC rect->polar) with LCD UI, on iCE40UP5K	iCE40 UP5K (NOT ECP5) - QFN48 (FPGA/HDL/Makefile: nextpnr-ice40 –up5k; README says QFP package)	open (yosys+nextpnr-ice40+icepack via FPGA/HDL/Makefile)	Verilog (36 .v), Python (4: sinegen.py + PYTHON_FILTER/ IIR design scripts)	MIT (LICENSE)	? → 2023-05-11, ?	none
orbcode__orbtrace	ORBTrace: Cortex-M SWD/JTAG debug + parallel TRACE probe gateware (CMSIS-DAP over USB), primarily for ORBTrace mini, also builds for ECPIX-5	ECP5-5G 45F/85F (LFE5UM5G-45F/85F default 85F, BG554, ECPIX-5; orbtrace/platforms/ecpix5.py add_arguments –device choices 45F/85F; verilog/Makefile ECPIX_5_85F target: –um5g-85k –package CABGA554). Also ECP5 25F/45F BG256 (orbtrace_mini.py: LFE5U-{25F,45F}-8BG256C, NOT ECPIX-5) and iCE40 HX8K/UP5K (NOT ECP5: verilog/Makefile ICE40HX8K_B_EVN/ICEBREAKER targets)	open; two flows: (1) orbtrace_builder.py (LiteX/Migen SoC + Amaranth glue, oss-cad-suite yosys/nextpnr-ecp5/ecppack under the hood, invoked via pdm); (2) legacy verilog/Makefile (plain Verilog: yosys+nextpnr-ecp5+ecppack+ecpprog, also nextpnr-ice40+icepack)	Python (64 own .py: LiteX/Migen SoC + Amaranth glue + orbtrace_builder.py), Verilog (9 own .v: legacy dbgIF/jtagIF/swdIF/traceIF/ram + 4 testbeds)	BSD-3-Clause (COPYING: “applies to all files in this distribution unless specifically indicated”)	? → 2026-02-06, ?	none
osresearch__spispy	SPI Spy: SPI flash emulator from SDRAM for firmware/TOCTOU research	12F	open	Verilog	none found (uart.v MIT)	2019-06-01 → 2019-10-01, 169	none (upstream of arisotura__spi_flash)
ox-computing__real-time-analytics-fpga	Real-Time-Analytics-FPGA: 2048-pt BFP FFT/Welch-PSD feature extractor driving a weightless-NN (DWN) stress classifier	ECP5 LFE5UM5G-85F CABGA381 (ecp5-evn board, DESIGN=wesad default, FAMILY=ecp5, nextpnr-ecp5 –um5g-85k, rtl/constraints/ECP5/constraints_ecp5_wesad_i2c.lpf - carries the 2048-pt FFT) + iCE40 UP5K SG48 (NOT ECP5, DESIGN=mnist, nextpnr-ice40 –up5k, rtl/constraints/UP5K/dwn_uart_mnist.pcf - no FFT, LUT-only classifier)	open; yosys+nextpnr-ice40+icepack (MNIST/iCE40, DEVICE=up5k) and yosys+nextpnr-ecp5+ecppack (WESAD/ECP5, DEVICE=um5g-85k); one Makefile, FAMILY=ice40|ecp5	SystemVerilog (33, wesad/), Verilog (18, rtl/ MNIST DWN + power tb), Python (44, training/verification/scripts)	Apache-2.0	? → 2026-08-31, ?	none
pablogs9__rocketfpga	RocketFPGA: iCE40 UP5K breakout board w/ CH551 USB-to-SPI-flash bridge MCU; Verilog example projects for audio synthesis (ADC, echo, filters, waveform generators, mixer, ADSR).	iCE40 UP5K (NOT ECP5) - SG48	open (yosys+nextpnr-ice40+icepack)	Verilog (39 .v)	none found (no LICENSE/COPYING file; no SPDX in source)	? → 2020-04-11, ?	none
pat-pgt__multifrequenciesdetector	MultiFrequenciesDetector: parametric CORDIC-based 12-notes/octave audio frequency detector (no FFT, no mult/div IP)	iCE40 HX4K (NOT ECP5) - TQ144/CM225 (VHDL/Makefile: nextpnr-ice40 –hx4k –package tq144|cm225); ECP5 12F TQFP144 target present in the Makefile but commented out, never actually built	open; yosys -m ghdl (ghdl-yosys-plugin) + synth_ice40 + nextpnr-ice40 –hx4k (VHDL/Makefile); commented-out ecp5 target (synth_ecp5+nextpnr-ecp5 –12k); simulation via ghdl -a/-e/-r	VHDL (34, VHDL/), C++ (6, VHDL/CXX_VERIF/ verification), Python (3, Tek_and_gene/ coefficient exploration scripts)	AGPL-3.0	? → 2026-09-24, ?	none
pavlenkog__ecp5_pcie_analyzer	ECP5_PCIE_Analyzer: uses the ECP5UM(G) PCS block to deserialize/8b10b-decode PCI-Express lanes for protocol capture, read out over SPI by a Raspberry Pi	85F ECP5-5G (LFE5UM5G-85F-8BG381C, ECP5 Evaluation Board) – fpga_logic/script/make.tcl: prj_project new -dev LFE5UM5G-85F-8BG381C -synthesis synplify	diamond (Lattice Diamond + Synplify synthesis via make.tcl; Clarity Designer PCIe/EXTREF IP cores at fpga_logic/src/cores/{pcie,extref}/*.lpc); simulation via VUnit + Aldec Active-HDL (fpga_logic/sim/vunit/run.py, hardcoded Windows C:\Aldec paths + Lattice sim libraries)	VHDL (24 files under fpga_logic/src+sim), 1 Verilog stub (sim/vunit/dummy.v), Python capture/parse scripts (5, py_script/)	none found (no LICENSE file); fpga_logic/src/lfsr_scrambler.vhd header: ‘Copyright (C) 2009 OutputLogic.com … may be used and distributed without restriction’	? → 2023-10-06, ?	none
punchthatface__tinydma	TinyDMA-2C two-channel SPI-PSRAM DMA engine, primarily an ASIC/Tiny Tapeout core with a minimal ULX3S bring-up harness	12F (nextpnr-ecp5 –12k in build_fpga.sh)	open: yosys+nextpnr-ecp5+ecppack via build_fpga.sh / build_fpga_bringup.sh	SystemVerilog (14 .sv: core DMA/SPI/PSRAM logic + testbenches)	none found	? → 2026-04-28, ?	none (ULX3S build is a bring-up/test harness for an ASIC-targeted core; Tiny Tapeout wrapper files live in a separate repo)
rainbow1128__vhdl-aes-master	VHDL-AES-Master: unmodified mirror of marph91/yaaes AES-128/256 core (ECB/CBC/CFB/OFB), synthesized for ULX3S ECP5-85F	ECP5 85F (syn/synth.sh: nextpnr-ecp5 –85k –package CABGA381 –freq 100)	open: yosys -m ghdl (ghdl-yosys-plugin) + nextpnr-ecp5 + ecppack via syn/synth.sh	VHDL (13 .vhd), Python (8, vunit testbenches)	LGPL-3.0 (LICENSE)	? → 2023-05-02, ?	marph91/yaaes (identical file layout/content; CI badges still point at github.com/marph91/yaaes)
reddocmd__klaus	Klaus: Advent of Code 2025 solutions implemented as Hardcaml (OCaml) hardware designs, built for the ULX3S (85k LUTs)	ECP5 85F (src/build.ml: nextpnr-ecp5 –85k, README: “85k LUT’s”)	open: yosys (read_verilog -sv; synth_ecp5) + nextpnr-ecp5 + ecppack, invoked from OCaml via src/build.ml; Hardcaml emits Verilog	OCaml/Hardcaml (19 .ml, emits Verilog at build time)	none found	? → 2026-01-16, ?	none (test/build harness patterned after asinghani/advent-of-hardcaml-2024, per README)
riltonf__thermal_camera_ulx3s	Thermal (MLX90640) + color (OV7670) camera pipeline with VGA/DVI out and SDRAM framebuffer for ULX3S	25F (LFE5U-25F per Makefile; targets ULX3S v2.0/v3.0.3)	open: yosys+nextpnr-ecp5+ecppack (oss-cad-suite via direnv), vhd2vl/sv2v	SystemVerilog (~86 files), Verilog (10), Python tooling (15)	GPL-3.0	? → 2025-07-01, ?	none
rj45__vdp	Retro-inspired Video Display Processor (VDP) core in SystemVerilog, redo of the rjvdp project, plus Rust emulator/tooling	85F (ulx3s/ulx3s.mk DEVICE?=85k)	open; yosys+nextpnr-ecp5+ecppack via ulx3s.mk	SystemVerilog (32 .sv), Verilog (6 .v), Rust (5 .rs, emulator/tools)	MIT (LICENSE, portions Copyright Will Green)	? → 2026-01-25, ?	redo of rj45/rjvdp (was in Digital simulator) in SystemVerilog
romavis__lwdo-sdr-fw	LWDO-SDR firmware: LF/VLF SDR timing receiver, dual AD7357 ADC pipeline + TDC + PPS generator + DAC8551 DAC + FT245 sync-FIFO link, on iCE40HX4K	iCE40 HX4K (NOT ECP5) - TQ144 (fpga/Makefile: DEVICE=hx4k PACKAGE=tq144)	open (yosys+nextpnr-ice40+icestorm/icepack via fpga/Makefile)	Verilog (~26 .v excl. 3rdparty submodules)	MIT (LICENSE.txt); fpga/3rdparty/* carry their own licenses	? → 2025-03-25, ?	none (firmware for the separate lwdo-sdr-hw board repo, not in this collection)
seminlim__blueyosys	blueYosys: Bluespec SystemVerilog development flow (BSV -> Verilog -> Yosys -> nextpnr-ecp5) for Lattice ECP5, current real target ULX3S-85F	ECP5 85F (ULX3S-85F, README.md:5 ‘Current target: ULX3S-85F (BOARD=ulx3s-85f)’, boards/ulx3s/constraints/ulx3s.lpf); README.md:5 also says ‘The ICE40 backend is reserved for future support’ - not implemented, no iCE40 files exist in this clone: claimed-future only, not real	open (Yosys+nextpnr-ecp5+ecppack via OSS CAD Suite, README ‘Requirements’); Bluespec Compiler (bsc) generates the Verilog from BSV	Verilog (14, generated/board RTL), BSV source under boards/ and lib/ (not counted by std extensions), Python (5)	none found (no LICENSE file in this clone; README has no license statement)	? → 2026-09-23, ?	none
seminlim__sway	Sway: selective state-space-model (Mamba/SSM) accelerator in Bluespec SystemVerilog for ULX3S-85F, with FP32/INT8-PTQ MARS pose-regression baseline	ECP5 85F (hw/Makefile default BOARD=ulx3s-85f)	open; Bluespec Compiler (BSC)+Bluesim to Verilog, then the external blueyosys repo’s build.mk drives yosys+nextpnr-ecp5+ecppack (ROOTDIR must point at a sibling blueyosys checkout, not vendored here)	Bluespec SystemVerilog (13 .bsv), Python (23: sw/ model+PTQ scripts)	none found	? → 2026-09-28, ?	none (shares the seminlim/blueyosys build flow, external dependency)
seminlim__zfpe	CNN_Accelerator_with_ZFPe: lossy ZFP-style block compression for CNN fully-connected-layer weights, in Bluespec SystemVerilog, claimed ULX3S target	ECP5 85F claimed (Makefile: apio init -b ulx3s-85f) but unbuildable as cloned: no src/ directory exists at all, only projects/	open intent (apio -> yosys+nextpnr-ecp5+ecppack) but not reproducible from this clone (missing src/ tree)	Bluespec SystemVerilog (9 .bsv: NnFc.bsv/HwMain.bsv/ZfpCompress.bsv/ZfpDecompress.bsv x3 project variants), C++ (6, host test harness)	none found	? → 2021-08-20, ?	none
splinedrive__my_hdmi_device	my_hdmi_device: from-spec TMDS/HDMI encoder, multi-board	85F	open	Verilog, SV (ecp5pll)	ISC (ecp5pll BSD)	2021-02-15 → 2025-08-28, 20	none
stereoninja__stereoninjafpga	StereoNinjaFPGA: experimental dual MIPI-CSI camera streaming, ULX3S HDMI/passthrough test iterations	85F (old/…/HDMI_Transciever_Test Makefile: nextpnr-ecp5 –85k)	open; yosys+nextpnr-ecp5+ecppack, per-project Makefiles	Verilog (111 .v), C++ (93, cocotb/verilator testbenches)	none found (no LICENSE/COPYING at any depth)	? → 2023-05-15, ?	none
stuij__odyssey	ULX3S-85F project driving an ST7789 SPI LCD (‘segpdi’ variant) with VGA-style video generator and PS/2 keyboard input; name/purpose otherwise undocumented (README says ‘what: tbd’)	85F (Makefile FPGA_SIZE=85, FPGA_CHIP=lfe5u-85f)	both: scripts/trellis_main.mk drives yosys+nextpnr-ecp5+ecppack (README says this is the only tested path); scripts/diamond_main.mk is present for Lattice Diamond (diamondc/ddtcmd) but untested per README	Verilog (4 .v), SystemVerilog (1 .sv: ecp5pll.sv)	none found	? → 2023-02-03, ?	none
tallenintegsys__hdmi-orangecrab	OrangeCrab: HDMI video+audio transmitter, porting Sameer Puri’s hdl-util/hdmi IP to Lattice ECP5 via yosys+synlig SystemVerilog frontend	25F (OrangeCrab r0.2, CSFBGA285)	open (yosys with synlig plugin for SystemVerilog frontend, nextpnr-ecp5 –25k, ecppack)	SystemVerilog (12 .sv), Verilog (2 .v: hdmi_pll.v, LFSR.v)	none found (no LICENSE/COPYING file; a “COPYRIGHT_NOT_ASSERTED” HDMI audio parameter is not a real license header)	? → 2024-07-07, ?	hdl-util/hdmi (Sameer Puri) - ported/porting per README, not a git fork
thata__ulx3s-playground	Small ULX3S playground: blinky + BRAM controller demo (Japanese comments)	85F (nextpnr-ecp5 –85k)	open: yosys+nextpnr-ecp5+ecppack	SystemVerilog, 4 files	CERN-OHL-1.2	? → 2024-12-18, ?	none
thorkn__layr_audio	LAYR_AUDIO: ULX3S ECP5-85F port of the C64 SID (6581) sound chip	ECP5 85F (src/Makefile: CHIP=85k, nextpnr-ecp5 –85k –package CABGA381)	open: yosys (synth_ecp5) + nextpnr-ecp5 + ecppack via src/Makefile; oss-cad-suite 2026-02-12 recommended	Verilog (2 .v: sid.v 5147 lines, pll.v)	none found	? → 2026-05-14, ?	CornN64/C64-SID-on-a-FPGA (per README “Origin of the code”)
thorkn__spinalsynth_ulx3s	SpinalHDL polyphonic synthesizer (voice/envelope/SVF filter) ported to ULX3S, largely AI-generated per README	85F (Makefile: CHIP := 85k)	open; detail=SpinalHDL (generates Verilog) -> yosys+nextpnr-ecp5+ecppack	Verilog 4 (generated top + core + 2 PLLs); SpinalHDL source not included (only its Verilog output)	none found	? → 2026-06-11, ?	none
tinyfpga__tinyfpga-bootloader	TinyFPGA USB Bootloader: USB virtual-serial-to-SPI-flash-bridge gateware bootloader; iCE40 LP8K origin of the old ULX3S US2 bootloader lineage	iCE40 LP8K (NOT ECP5) - CM81 (boards/TinyFPGA_BX/Makefile DEVICE=lp8k); also iCE40 UP5K (ICEBreaker_bitsy, Tomu_Fomu), Xilinx Artix-7 (Digilent-Arty .xpr), and ECP5 LFE5U-12F-6MG285C (boards/TinyFPGA_EX/diamond.ldf)	open (yosys+nextpnr-ice40+icepack) for the iCE40 boards; diamond for TinyFPGA_EX (ECP5); Vivado project for Digilent-Arty	Verilog (common/*.v: 13 files; plus one bootloader.v per board dir)	Apache-2.0 (LICENSE)	? → 2020-01-14, ?	none (upstream origin); ULX3S port lives in a separate repo, emard__tinyfpga-bootloader-ulx3s, itself a fork of phdussud’s 60MHz variant of this bootloader
toasterllc__mdccode	mdccode (Photon camera): iCE40 HX8K gateware bridging image sensor/SDRAM/SD card to MSP430/STM32 MCUs; repo also holds the MCU firmware	iCE40 HX8K (NOT ECP5) - BG121:4k package (Code/ICE40/SynthOptAll.sh: “–dev hx8k –pkg bg121:4k”; Code/ICE40/Pins.pcf pin map)	open (yosys+nextpnr-ice40+icepack), but via toasterllc’s own vendored forks (submodules Tools/yosys, Tools/nextpnr, Tools/icestorm -> yosys-MDC/nextpnr-MDC/icestorm-MDC, not fetched into this clone); Code/ICE40/Synth.py drives nextpnr with a mango-tuned placer (SynthOptAll.sh)	Verilog: 58 .v under Code/ICE40 (find Code/ICE40 -name ‘*.v’ | wc -l); separately, MCU firmware in C/C++: ~165 files Code/STM32, ~31 Code/MSP430 (not gateware)	public domain (LICENSE.md, one line, no SPDX id)	? → 2026-03-20, ?	none (own project; Tools/{yosys,nextpnr,icestorm} submodules are toasterllc’s own forks of the upstream tools, not fetched here)
toni3141__rastericer	iCE40 UP5K (iCEBreaker board): RasteriCEr, an OpenGL-ES-like fixed-function rasterizer/GPU core with SPI command interface, SPI TFT display controller, and a C++ IceGL driver library for MCU hosts (tested rendering Tuxracer).	iCE40 UP5K (NOT ECP5) - SG48 iCEBreaker; also targets Xilinx Artix-7 35T (Arty), NOT ECP5	open (yosys+nextpnr-ice40+icepack) for iCE40; Xilinx Vivado (closed) for Artix-7; Verilator for simulation	Verilog (17 .v, 2 .vh) RTL; C++ driver/simulation (IceGL, TnL, Rasterizer.cpp, sim_rasterizer.cpp)	GPL-3.0 (LICENSE, repo root; per-file headers confirm GPLv3-or-later)	? → 2021-10-23, ?	none
tucanae47__ulx3s-experiments	tucanae47/ulx3s-experiments: small ULX3S experiments — SSD1331/1351 OLED pattern generator + OV7670 camera capture/VGA display	85F (apio.ini board = ulx3s-85f)	open (apio: yosys+nextpnr-ecp5+ecppack)	Verilog (27)	none found	? → 2022-09-24, ?	none
tvelliott__dsp_ice	DSP_ICE: custom iCE40HX8K+STM32F417 SDR/audio board; FPGA glue for SPI/ADC + 8-channel audio synth, MCU does Ethernet/DSP	iCE40 HX8K (NOT ECP5) - CT256 (Makefile: DEVICE=hx8k, arachne-pnr -P ct256)	open; legacy flow: yosys synth_ice40 -blif + arachne-pnr + icepack (firmware/fpga/src/Makefile), not nextpnr	Verilog (5 .v, 1340 lines: fpga_top.v, spi_master.v, pll.v, bram_delay.v) under firmware/fpga/src/; bulk of project is C firmware (STM32F4 + lwIP + CMSIS DSP) and Eagle PCB files	MIT (LICENSE, tvelliott 2017)	? → 2017-10-03, ?	none
ulixxe__usb_cdc	Fomu / TinyFPGA-BX: USB_CDC, a from-scratch Full-Speed (12Mbit/s) USB CDC-ACM device core in plain Verilog, with board examples (bootloader, demo, loopback, soc)	iCE40 UP5K (NOT ECP5) - SG48/UWG30 (Fomu); iCE40 LP8K (NOT ECP5) - CM81 (TinyFPGA-BX)	open (yosys+nextpnr-ice40+icepack; iverilog/GTKWave sims); examples also support Lattice iCEcube2	Verilog (51 .v), VHDL (3 .vhd)	MIT (LICENSE)	? → 2024-03-10, ?	none
ultraembedded__core_ddr3_controller	Lightweight AXI-4 DDR3 memory controller (DLL-off, <=125MHz) with DFI PHYs for Xilinx 7-series and Lattice ECP5	ECP5-5G 45F/85F (LFE5UM5G-45F/85F, BG554, ECPIX-5; README: “LambdaConcept ECPIX-5 (Lattice ECP5 + MT41K256M16RE-125)”; examples/ecpix_ecp5/fpga.lpf has no device-size flag, clk 100MHz). Also Xilinx Artix-7 (NOT ECP5) via examples/arty_a7 (arty_revb.xdc, src_v/phy/xc7/ddr3_dfi_phy.v)	open, but no build script included in source; likely yosys+nextpnr-ecp5+ecppack (typical ECP5 flow, not verified in-repo); tb/ddr3_core_xc7/makefile needs Xilinx Vivado (xelab/xsim, proprietary sim, VIVADO_PATH)	Verilog (11 own: 6 in src_v + 5 in examples), SystemVerilog (1 own: examples/ecpix_ecp5/ecp5pll.sv)	Apache-2.0 (file headers e.g. src_v/ddr3_core.v, src_v/phy/ecp5/ddr3_dfi_phy.v; no top-level LICENSE file)	? → 2021-10-10, ?	none
ulx3s__ulx3s-adda	mirror of gojimmypi/ulx3s-adda	12F	open	Verilog	none found	2019-03-15 → 2019-03-16, 10	byte-identical mirror
uttamcoomar__mac-units-for-various-number-formats	MAC Units for ULX3S: multiply-accumulate units in six number formats (bf16, fp16, int8, lns8, mxfp8, posit8), MyHDL-generated Verilog with a UART test wrapper	ECP5 85F (int8/Makefile: PACKAGE=CABGA381, nextpnr-ecp5 –85k)	open (yosys + nextpnr-ecp5 + ecppack, per-format Makefile), BOARD=ulx3s_dfu for openFPGALoader flashing	Verilog (30 files, MyHDL-generated MAC cores + hand-written UART/top), Python (12, MyHDL sources + host test scripts)	none found	? → 2026-03-13, ?	none
uttamcoomar__nn_digits	mlp_accel: MNIST handwritten-digit MLP inference accelerator for the Radiona ULX3S (ECP5-85F)	ECP5 85F (README.md:1,4; syn/ulx3s.lpf) - ULX3S-only, no other FPGA/board target found in this clone	open (yosys+nextpnr-ecp5+ecppack+openFPGALoader, README.md:81)	Verilog (5, rtl/), Python (6, tests/host)	MIT (LICENSE)	? → 2026-03-23, ?	none
volnirr__verilog-uart	Standalone 8N1 UART transmitter/receiver core for ECP5/ULX3S, no vendor primitives, with iverilog testbenches	unknown (ulx3s.lpf present but no nextpnr device flag found anywhere in repo)	open: yosys+nextpnr-ecp5+openFPGALoader (per README prose only, no committed build script), Icarus Verilog for tb/*.v testbenches	Verilog (4 .v: 2 core + 2 testbenches)	none found	? → 2026-08-15, ?	none
voltcyclone__hurra-fpga	hurra-fpga: Amaranth bounded USB FS mouse host+device-clone relay for Cynthion r1.4, with report injection and multi-MCU firmware	12F (LFE5U-12F, BG256, Cynthion r1.4) - src/hurra_cynthion/gateware.py docstring “Cynthion r1.4 top level”; platform.request(‘target_phy’)/(‘aux_phy’) (ULPI); no other board targets found	open (Amaranth build backend, yosys+nextpnr-ecp5+ecppack via oss-cad-suite in docker/); nextpnr requires --placer-heap-timingweight 60 to close timing, enforced/documented in build_env.py	Python/Amaranth (64 .py: src/hurra_cynthion gateware+host + 24 sim-backed tests), C (103 .c: firmware/ch32h417 + firmware/mcxn947 MCU firmware, not FPGA)	MIT (LICENSE)	? → 2026-09-19, ?	none
voltcyclone__hurricanefpga	HurricaneFPGA: plain-Verilog Cynthion gateware - USB FS/LS sniffer/passthrough, USB host mode (enumeration+HID), HID injection over UART	12F (LFE5U-12F-8BG256C, Cynthion r1.4) - HDL/hardware/constraints/cynthion_pins.lpf (60MHz on A8) + HDL/Makefile (nextpnr-ecp5 –12k –package CABGA256); no other board targets found	open (yosys + nextpnr-ecp5 –12k –package CABGA256 + ecppack –compress, HDL/Makefile); flash via openFPGALoader --board cynthion; separate Docker/Makefile build system wraps the legacy Amaranth backend	Verilog (31 .v: 11 rtl + 7 testbenches + top.v), Python (17 .py: legacy/ Amaranth backend + tools/test_*.py), Rust (12 .rs: firmware/samd51_hid_injector)	MIT (LICENSE)	? → 2025-12-28, ?	ramseymcgrath__hurricanefpga (previous name/owner: README/CI badge still points there; not confirmed as a formal GitHub fork)
vyges__fast-fourier-transform-ip	fast-fourier-transform-ip: configurable 256-4096pt radix-2 DIF FFT accelerator IP (APB/AXI/bus-master, auto BFP rescale)	ECP5 25F (nextpnr-ecp5 –25k, flow/fpga/Makefile FPGA_FAMILY=ecp5) + iCE40 HX8K CT256 (NOT ECP5, default FPGA_FAMILY=ice40, flow/fpga/openfpga/constraints/hx8k-ct256.pcf) + Xilinx 7-series (FPGA_FAMILIES lists xilinx7; no constraint/flow files found)	open; yosys+nextpnr-ice40+icepack (default, flow/fpga/openfpga/Makefile ice40_synth) and yosys+nextpnr-ecp5 –25k (ecp5_synth/ecp5_pnr); also an xilinx7 family option (no vivado flow files seen)	SystemVerilog (30, rtl/+tb/sv_tb/+flow/synthesis), Python (14, tb/cocotb+scripts)	Apache-2.0	? → 2026-08-08, ?	none
w531t4__fpga_led_display	w531t4/fpga_led_display: LED matrix panel driver (RGB24/565, chained matrices), supports “panelith” custom board (default) and ULX3S (secondary)	unknown (no explicit device size found for the ulx3s target in mk/config.mk; v316 LPF implies a standard ULX3S board rev but size isn’t pinned in this file)	open (yosys via mk/yosys.mk, oss-cad-suite)	SystemVerilog (98 .sv + 8 .svh)	MIT	? → 2026-07-12, ?	none
whitequark__yumewatari	Yumewatari: Migen PCIe Gen1 PHY for ECP5 (DCUA SERDES, 8b10b align, PIPE-like phy_rx/phy_tx); dormant since 2019, predecessor of ECP5-PCIe	45F ECP5-5G Versa (LFE5UM5G-45F assumed via external migen.build.platforms.versaecp55g, unverified in this repo; DCUA+EXTREFB in yumewatari/gateware/platform/lattice_ecp5.py; ispclock/versa5g-pcie-ispCLOCK-{100,200}MHz.jed for the board’s PCIe refclk synthesizer).	unknown (no build script/toolchain arg in this repo; imports external migen.build.platforms.versaecp55g platform, typically yosys+nextpnr-ecp5 via Migen Builder, unverified here).	Python (26, Migen; no .v/.sv sources)	0BSD (LICENSE-0BSD.txt)	? → 2019-04-02, ?	none
williamsharkey__pruned-sha256-miner	Pruned 64-stage double-SHA256 Bitcoin miner pipeline for ULX3S ECP5-85F, single-bit hit-pulse output to reduce routing congestion	ECP5 85F (README and run.py: nextpnr-ecp5 –85k –package CABGA381 –speed 6)	open: yosys synth_ecp5 + nextpnr-ecp5 + ecppack, orchestrated by run.py; but run.py’s NEXTPNR path points outside this repo (../68-ecp5-partial-unroll/toolchain/bin/nextpnr-ecp5, absent) and its scripts/copies/logs/mapped/routes dirs are all missing	SystemVerilog (7 .sv: factory75.sv, factory75pruned.sv, formal75.sv, 4 tb*.sv)	none found	? → 2026-08-13, ?	none (own design)
wren6991__smoldvi	iCEBreaker/iCEstick/iCESugar/TinyFPGA-BX: SmolDVI, a small direct DVI/TMDS output core (pixel-doubled RGB666 640x480p60) for iCE40 UP5K/HX1K/LP8K boards	iCE40 UP5K (NOT ECP5) - SG48 (iCEBreaker, iCESugar); iCE40 HX1K (NOT ECP5) - TQ144 (iCEstick); iCE40 LP8K (NOT ECP5) - CM81 (TinyFPGA BX)	open (yosys+nextpnr-ice40+icepack, via Wren6991/fpgascripts submodule Makefiles)	Verilog (12 .v)	CC0-1.0 (LICENSE.md)	? → 2021-07-15, ?	none
xtrinch__fpga-bitcoin-miner	Bitcoin miner: pipelined double-SHA256 FPGA miner (fork of progranism/Open-Source-FPGA-Bitcoin-Miner) for the Lattice ECP5-EVN board	85F (LFE5UM5G-85F-8BG381 ECP5-EVN board, –um5g-85k –package CABGA381 –freq 50, Makefile; README states “LFE5UM5G-85F-8BG381”)	open (yosys+nextpnr-ecp5+ecppack; yosys connect_rpc runs src/ecp5pll.py as a Python PLL-generator frontend); openocd svf via ecp5-evn.cfg for programming	Verilog (12 .v: 8 in src/, 4 in testbenches/), Python (6 .py: helpers/ scripts + src/ecp5pll.py)	MIT (LICENSE, root; “Copyright (c) 2011 fpgaminer@bitcoin-mining.com; Copyright (c) 2021 Mojca Rojko”)	? → 2022-04-01, ?	progranism/Open-Source-FPGA-Bitcoin-Miner (per README: “Adaptation of … for the Lattice ECP5 evaluation board”)
zipcpu__sdr	ZipCPU/sdr: ‘Gateware Defined Radio’ - AM/FM/QPSK transmitter and receiver designs for an iCEBreaker + SX1257 radio PMod, with CORDIC-based demodulation	iCE40 UP5K (NOT ECP5) - iCEBreaker, SG48 (rtl/Makefile: synth_ice40 -device u, nextpnr-ice40 --up5k -r --package sg48)	open (yosys+nextpnr-ice40+icepack via rtl/Makefile) plus AutoFPGA (generates rtl/toplevel.v, rtl/sdr.pcf, sim/software glue from autodata/*.txt) and Verilator for simulation	Verilog (43 .v: rtl/ + wbuart/hexbus/wbscope subtrees), C++ (11, sim/ and sw/ host tools)	GPL-3.0-or-later (file headers throughout rtl/, e.g. rtl/cicfil.v: “either version 3 … or any later version”; no LICENSE file in this clone)	? → 2024-01-18, ?	none
zipcpu__sdspi	SD-Card cores (ZipCPU/Gisselquist): Wishbone sdspi (SPI-mode), sdio (SDIO/eMMC), sdslave (SDIO slave) Verilog controllers	vendor-neutral (NOT ECP5-specific) - no .pcf/.xdc/.lpf/.sdc anywhere in repo; README names the XuLA2-LX25 (Xilinx Spartan-6) as the original SPI-mode target board; cores are meant to be dropped into any Wishbone/AXI-lite SoC via autodata/*.txt (autofpga) or sdspi.core (FuseSoC)	open: verilator + iverilog for simulation, SymbiYosys for formal (bench/formal/Makefile); FuseSoC .core lists verilator as its simulator; no synthesis-to-bitstream flow included, integrator supplies top+constraints	Verilog: 37 files in rtl/ (find rtl -name ‘*.v’ | wc -l), 48 more testbench/model .v files in bench/ (85 total .v in repo)	GPL-3.0 (per-file headers, e.g. rtl/spi/sdspi.v “License: GPL, v3”; doc/src/gpl-3.0.tex bundled; no top-level LICENSE/COPYING file)	? → 2026-08-01, ?	none
zipotron__ulx3s_sdram8	SDRAM test/experiment for ULX3S, a VHDL translation of lawrie’s Verilog SDRAM controller (8-bit)	85F (Makefile/ulx3s.mk DEVICE=85k)	open: yosys+nextpnr-ecp5+ecppack via Makefile including ulx3s.mk	VHDL (1 .vhd, sdram.vhd core), Verilog (1 .v, top), SystemVerilog (1 .sv, ecp5pll.sv)	none found	? → 2021-10-12, ?	translated from github.com/lawrie’s Verilog SDRAM code (lawrie has multiple other cloned ULX3S repos in this survey but not this exact sdram8 one)
zyp__katsuo-pcie	katsuo.pcie: Amaranth PCIe Gen1 x1 endpoint (ECP5 SERDES PHY, abbreviated LTSSM, DLL, TL w/ config space+MSI); working PoC, no retransmit/flow control	ECP5-5G (LFE5UM, DCUA+EXTREFB in katsuo/pcie/phy/ecp5_serdes.py; resource name ‘pcie_x1’). No board file in this repo: pins/platform come from the consumer, e.g. zyp/litepcie-katsuo-poc’s Lattice Versa ECP5 –device LFE5UM.	not specified in this repo (no board/platform file; PHY is an amaranth wiring.Component consumed by an external board flow, e.g. litepcie-katsuo-poc’s trellis build).	Python (25, Amaranth; no .v/.sv sources)	MIT (pyproject.toml license field; no LICENSE file in repo)	? → 2026-04-28, ?	none (ecp5_serdes.py reuses code from Yumewatari under 0BSD, per its own header comment)
zyp__litepcie-katsuo-poc	LitePCIe-on-ECP5 PoC: katsuo.pcie PHY under LitePCIe on Lattice Versa ECP5 (Migen/LiteX); enumerates as Gen1 x1 (lspci in README)	45F ECP5-5G (LFE5UM or LFE5UM5G-45F, Lattice Versa ECP5-5G dev board; lattice_versa_ecp5.py –device LFE5UM per README, platform default device="LFE5UM5G"). ecp5_pcie.py wraps katsuo.pcie’s PIPE datapath.	open (LiteX Builder, toolchain="trellis" in lattice_versa_ecp5.py -> yosys+nextpnr-ecp5+ecppack; README: pdm run ./lattice_versa_ecp5.py --device LFE5UM --build).	Python (2), Verilog (1: pregenerated ecp5_pcie.v)	MIT (pyproject.toml license field; no LICENSE file in repo)	? → 2026-04-28, ?	none (lattice_versa_ecp5.py is ‘lightly modified from the original from litex-boards’ per README)

Testbenches and simulation

Heuristic scan (.claude/skills/review-gateware-project/scan_tests.sh, 2026-09-27) over each shallow clone for test/sim directories (tb/, test/, sim/, …), testbench-named files (*_tb.v, tb_*.vhd, *_test.py, …) and simulator mentions (iverilog, Verilator, GHDL, cocotb, VUnit) in build scripts. It is a name/path heuristic, not proof the tests run or pass — verify before relying on one. Repos not listed here had nothing matching.

The Run by make column (make_tests, 2026-09-28) comes from scan_make_tests.py candidates checked by hand-reading the Makefiles: the make command, simulator and testbench files a target actually runs. Lint-only and synthesis-only uses of simulators are excluded. Nothing was executed.

Repo	Detected test/sim setup	Run by make
abhinavputhran__ttysky-raycast-test	dirs: ./test;tools: cocotb	test/Makefile:(cocotb include) [cocotb]: test/test.py - self-checking (assert dut.uio_oe.value==0xFF etc.)
acairncross__euphrates	dirs: ./test
adrmcintyre__vixen	dirs: ./lang/tests;tools: verilator,iverilog
agamez__whisperice	dirs: ./sim; 13 tb/test files	make sim (ghdl –std=93): sim/tb_.vhd analyzed+elaborated against src/.vhd, executed with –assert-level=error, stops on first failure (Makefile:145-165) - self-checking (VHDL asserts); make build (yosys -m ghdl + nextpnr-ice40 + icepack + icetime): synthesizes/packs the bitstream only, runs no testbench
alangarf__apple-one	3 tb/test files;tools: verilator,iverilog	none: %_tb.vvp/%_tb.vcd (iverilog) pattern rules in boards/*/yosys/Makefile need *_tb.v under rtl/ - none exist there; real tb files (uart_tb.v, vga_tb.v, apple1_tb.v) live in tools/iverilog/, run via shell scripts not make; icepi_zero lint is verilator –lint-only
alberto-grl__1bitsdr	3 tb/test files
alhusseingamal__r2sdf-fft	dirs: ./tb;1 tb/test files;tools: cocotb,verilator,iverilog	Makefile:run (verilator, TOP=tb_fft_top): tb/tb_fft_top.v + data/golden+data/stimulus - self-checking (computes/prints SQNR in dB vs numpy golden reference each run; no pass/fail assert, must read the printed dB); fpga/Makefile:sim (cocotb+iverilog) - none: expects tests/testbench.py, absent from this clone
amin005__skywave_sdr	2 tb/test files
anmho__ulx3_bsv	dirs: ./projects/test
antoinevg__cynthion-tutorials	1 tb/test files
antonblanchard__chiselwatt	dirs: ./tests ./src/test;1 tb/test files;tools: verilator	make check (scala_tests + tests/.bin): builds verilator sim of Core.v (generated by mill, absent in clone) + chiselwatt.cpp harness, runs tests via scripts/run_test.sh - self-checking (diff vs tests/.out, PASS/FAIL)
apfaudio__eurorack-pmod	dirs: ./gateware/sim;tools: cocotb,verilator	gateware/sim/{integration,ak4619,transpose,cal,vca,pmod_i2c_master}/Makefile and cores/util/filter/karlsen_lpf{,pipelined}_sim.mk (cocotb, via cocotb-config include): tb*.py e.g. sim/cal/tb_cal.py - self-checking (@cocotb.test() functions asserting clamped/expected values against a reference model)
apfaudio__guh	dirs: ./tests;6 tb/test files
aravindrajeshkanna__vernier-rv32	dirs: ./sim ./tests;65 tb/test files;tools: verilator,iverilog
asinghani__advent-of-hardcaml-2024	dirs: ./fpga/test
asinghani__advent-of-hardcaml-2025	dirs: ./day07/test ./day06/test ./day01/test ./day02/test ./day12/test
asinghani__pifive-cpu	dirs: ./cpu/rtl/test ./cpu/tests ./software/tests ./scripts/tests ./soc/tb;11 tb/test files;tools: verilator,iverilog
assured__ct-key	tools: verilator,iverilog	ctkey_package/src/ctkey/cores/aes/toolruns/Makefile:core.sim/keymem.sim/encipher.sim/decipher.sim/top.sim (iverilog, via $(CC) var - missed by scanner): src/tb/tb_aes_*.v - self-checking (error_ctr counter, $display ERROR on mismatch)
badgeteam__mch2022-firmware-ice40	dirs: ./projects/riscv_doom/sim ./projects/spi-to-rgb/sim ./projects/selftest/sim ./cores/spi_slave/sim;5 tb/test files
bhouvana__aegis-x86-processor	dirs: ./Decoder/tests ./Differential-Testing/tests ./RTL/tb ./Verification ./Emulator/tests;206 tb/test files;tools: cocotb,verilator	Verification/cocotb/Makefile:(cocotb include) [cocotb]: RTL/tb/.sv + Verification/cocotb/.py - self-checking (per-retire lockstep vs aegis_emu reference model, incl. test_fpga_top.py); lint/lint-leaf/lint-strict/lint-fpga [verilator] - none: lint-only, no sim run
bnossum__midgetv	tools: verilator	make -C work/tst .bin (verilator+g++): m_tb_inputmux.cpp/.v, m_tb_illegalop.cpp/.v exist - self-checking (ferr()/exit on mismatch); default 'all' target only builds m_ice40sim_* (not the tb targets)
bonfireprocessor__bonfire-basic-soc	dirs: ./tb;3 tb/test files
bonfireprocessor__bonfire-core	dirs: ./fusesoc-cores/tb ./tests ./docs/tests ./tb;32 tb/test files
bonfireprocessor__bonfire-ecp5-jtagg-led-demo	dirs: ./tests;3 tb/test files
bqqbarbhg__blipv1	dirs: ./blip/test
brunolevy__learn-fpga	dirs: ./FemtoRV/SIM;tools: verilator,iverilog	make -C FemtoRV BENCH.icarus/BENCH.verilator: RTL/femtosoc_bench.v + SIM/sim_main.cpp exist, runs firmware w/ OLED/GLFW display - no PASS/FAIL found, waveform/visual-only; *.lint targets (BENCH.lint, ULX3S.lint, etc) are verilator lint-only
brunolevy__tordboyau	tools: verilator
businessmanraduc__doggo-v6	dirs: ./tests;1 tb/test files;tools: verilator
c-elegans__single_sdr	dirs: ./sim (contains only a Lattice MULT18X18D primitive simulation model, not a testbench)	none: no Makefile target invokes a simulator; the Makefile only builds Top.v->Top.json->Top_out.config (synthesis/PnR), and the FFT RTL it depends on (fft-core/) is missing since the dblclockfft submodule was not fetched
c-elegans__ulx3s_sdram	1 tb/test files;tools: iverilog
callummcduff-droid__cpu	dirs: ./reference_model/tests ./tb;11 tb/test files;tools: verilator	Makefile:alu/decoder/cu/pc/registers/data_mem/inst_mem/cpu_pipeline (verilator, via $(VERILATOR) var - missed by scanner): tb/*_tb.sv - self-checking ($display(“PASS: TEST_ID: %d”…) in cpu_pipeline_tb.sv; regression target exits non-zero on failure)
cariboulabs__cariboulite	dirs: ./software/libcariboulite/test; 1 tb/test files
carlosedp__chisel-fpga-pinfinder	dirs: ./src/test
carlosedp__chiselv	dirs: ./chiselv/test ./gcc/test;tools: verilator	make verilator+verirun (verilator+g++): builds/runs chiselv.bin from generated/*.v (chisel output, absent in clone) + verilator/chiselv.cpp; make test runs Chisel/Scala-level tests (mill), not a Verilog testbench
cbalint13__e-verest	dirs: ./utils/test-firmware/sim;2 tb/test files;tools: iverilog	make -C utils/test-firmware sim / out/everest_tb.vvp (iverilog): sim/firmsoc_tb.v+clkdiv.v - waveform-only (only $finish in tb, no PASS/FAIL/assert)
cgarryza__advent-of-camel-2025	dirs: ./fpga/test
cheyao__icepi-zero	dirs: ./gateware/dvi/sim;tools: verilator,iverilog	none for most modules: verilator –lint-only (lint, not sim); gateware/dvi/Makefile ‘sim’ target (verilator+SDL3, sim/main.cpp exists) only builds the exe, no run step in the recipe - visual DVI viewer, not automated
cheyao__oberon	tools: verilator	none: lint only (verilator –lint-only)
cheyao__sega-sms	tools: verilator	none: lint only (verilator –lint-only)
chipdesign-bv__cdriscv-32s-20	dirs: ./verif ./tb;34 tb/test files;tools: verilator,iverilog	make sim (iverilog): tb/tb_cdriscv_subsys.sv - self-checking; bootsim/-fault: tb/tb_cdriscv_boot.sv - self-check (grep PASS); ~20 block-* benches (verif/block/*) grep PASS/FAIL; formal (sby): 7 properties; cosim vs spike - all tb files present, thorough suite
chipflow__example-socs	dirs: ./my_design/sim ./tests;3 tb/test files
chiplet__acorechip-ulx3s	dirs: ./ACoreChip/src/test;tools: cocotb	none via top Makefile (only ‘fw’ builds firmware, no test target); ACoreChip/src/test/cocotb/Makefile runs cocotb+icarus (test_pipeline.py exists) but VERILOG_SOURCES path ../../../verilog/ACoreChip.v is wrong (actual file is rtl/ACoreChip.v) - broken
chrislikescisco__nes-fpga	1 tb/test files
chrismoos__m6502	dirs: ./test;10 tb/test files;tools: cocotb,verilator	make test (pytest+cocotb via cocotb_tools.runner, sim=verilator default): 9 test_.py/.sv pairs in test/ - self-checking (python asserts); make test-klaus (verilator, tb_mcu_klaus.cpp+test_mcu_klaus.sv, Klaus 6502 functional test) - self-check unclear, no PASS/FAIL grep found
ckdur__riscvconsole	tools: verilator	sims/verilator/Makefile:debug/$(sim_files) (verilator): drives a chipyard-generated model (MODEL=RVCHarness from hardware/chipyard) - none: cannot confirm it runs, generated RTL/testbench source is absent from this clone (submodule not fetched)
cliffordwolf__icotools	tools: iverilog	examples/icezero/Makefile:testbench (iverilog): testbench.v - waveform-only ($dumpfile/$dumpvars, no pass/fail check, runs 100000 clocks then $finish)
cronokirby__ck-snes	dirs: ./hdl/test;1 tb/test files;tools: cocotb
cube1us__ibm1410fpga	8 tb/test files	none found: no Makefile/build script in the clone; testbenches are per-module .vhdl files with no automated runner (Vivado GUI/simulator assumed, not present)
daglem__redip-sid	tools: verilator	none run automatically: gateware/Makefile ‘sim’ target builds two verilator+g++ audio-model executables (sid_api_sim.cpp, –noassert flag) via –build but does not invoke them in the recipe; no PASS/FAIL check found - audio/waveform tool, not a testbench
damdoy__ice40_ultraplus_examples	dirs: ./riscv/simple_riscv_cpu/simulation;tools: verilator
dan-rodrigues__icestation-32	1 tb/test files;tools: verilator	none self-checking: software/common/core.mk ‘sim’ target builds (make -C simulator verilator_sim) and runs simulator/ics32_tb.v via ./verilator_sim - SDL/audio visual simulator (main.cpp, Simulation.cpp), no PASS/FAIL found
dan-rodrigues__ics-adpcm	dirs: ./sim ./sim/test;tools: verilator
dangerousprototypes__buspirateultrahdl	7 tb/test files
danielh186__6502-tapeout	1 tb/test files;tools: cocotb,verilator	make -C cocotb-testbench (icarus via cocotb): test_cpu.py + cpu.v - self-checking (verify_attr/verify_memory compare DUT regs/mem vs a maintained reference model after every instruction); make -C ASIC/src (icarus via cocotb): identical cocotb harness on the ASIC-flow copy of cpu.v - self-checking (same method)
danodus__onramp-fpga	dirs: ./sim;tools: verilator
danodus__xgsoc	dirs: ./rtl/sim;tools: verilator,iverilog	none self-checking: rtl/sim/Makefile ‘run’ target (verilator+SDL2, top.sv+sim_main.cpp) builds and runs a visual SDL display simulator, asserts are bounds-checks only; src/bench_coremark clean_tb only cleans that sim dir, not a test
darklife__darkriscv	dirs: ./sim;tools: verilator,iverilog	make (default, -> make -C sim): iverilog build of sim/darksimv.v + rtl sources, runs darksocv firmware and captures char/trace output - no explicit PASS/FAIL self-check, verdict is manual/trace-based (awk post-processing)
datanoisetv__colorlight-i9-aes67	dirs: ./sim;1 tb/test files;tools: verilator,iverilog	Makefile:sim (iverilog): sim/tb_ptp_clock.v - not self-checking (only $display prints of sec/nsec and PPS events, then $finish; no assert/PASS-FAIL) - waveform-only via dumped VCD; Makefile:lint (verilator): lint-only, does not run
daveshah1__ulx3s	1 tb/test files
detegr__ulx3s-projects	tools: iverilog	box/Makefile ‘simulation’ target (iverilog): test.v + top.v + digital_video sources - waveform-only ($dumpfile/$dumpvars only, no assert/PASS/FAIL)
dfiantworks__interactive-sim	dirs: ./tests;3 tb/test files;tools: verilator,iverilog	make e2e (python, tests/e2e.py): drives demo-vpi(iverilog)/demo-dpi(verilator)/demo-vhpi/demo-nvc(ghdl/nvc) sims + a reference viewer over a socket - self-checking (PASS/FAIL, sys.exit(1) on failure); demo-* targets alone are interactive human-driven demos, not automated tests
dibyx__flux	dirs: ./rtl/test ./sw-toolchain/sim;2 tb/test files;tools: cocotb
dicethrow__amtest	7 tb/test files
dlobato__cps1-musicbox	tools: verilator,iverilog
doctorwkt__ulx3s-blinky	tools: verilator	make all (verilator+g++): blinky_tb.cpp - builds, runs, writes blinky.vcd, waveform-only (no PASS/FAIL); Echo/Makefile (echo_tb.cpp) and TestPattern/Makefile (pattern_tb.cpp) same pattern, also waveform/image-only
doctorwkt__verilog_tic-tac-toe	tools: verilator	make all (verilator+g++): ttt_tb.cpp - builds and runs, writes VCD trace, waveform-only (no PASS/FAIL check found)
dschaefer__fpga-template	dirs: ./blinky/test
dstrbad__janestreet-advent-fpga	dirs: ./test
dulatello08__neocore-fx	dirs: ./tb;11 tb/test files;tools: iverilog	make run/core-smoke-run/core-any-run/mem-run/mem-nodebug-run/forward-hazard-run/frontend-timing-run/debug-mmio-run/debug-uart-router-run (iverilog via scripts/sim.py): tb/tb_*.sv - self-checking ($error “FAIL: …” on mismatch); large tb/ suite, all files present
dulatello08__neocorefx-dram	dirs: ./sim;5 tb/test files
dylansebastianheredia__e155_tuner_project	dirs: ./fpga/sim;10 tb/test files
ecp5-pcie__ecp5-pcie	dirs: ./Tests;23 tb/test files
egorxe__openglory	dirs: ./run/configs/sim ./hw/tb;tools: cocotb
emard__apple-one	3 tb/test files;tools: iverilog	none: same as alangarf__apple-one - %_tb.vvp/vcd (iverilog) pattern rule in boards/ulx3s/yosys/Makefile expects *_tb.v under rtl/, none exist there; real tb files are in tools/iverilog/, run via shell scripts not make
emard__apple2fpga	none found	make timing_testbench/i2c_testbench (ghdl, real VHDL sim not synth): timing_testbench.vhd, i2c_testbench.vhd exist, run via ghdl -e then executed to produce .vcd - waveform-only (no assert/report found), viewed in gtkwave
emard__cortex	1 tb/test files;tools: iverilog
emard__had2019-playground	dirs: ./cores/misc/sim ./cores/usb/sim;7 tb/test files;tools: iverilog	none: build/core-rules.mk make sim compiles cores//sim/_tb.v with iverilog but never runs vvp; project tbs dfu_helper_tb/top_tb same rule; testbenches dump waveforms, no pass/fail check
emard__papilio-arcade	3 tb/test files
emard__snes_mister_ulx3s	1 tb/test files;tools: ghdl-sim	make -C smpsim run (ghdl): smpsim/smp_tb.vhd exists, ghdl -e/-r; asserts are severity note only, not self-checking PASS/FAIL
emard__st7789py_mpy	1 tb/test files
emard__ulx3s-misc	dirs: ./examples/audio/testbench;1 tb/test files	none: ghdl used for synthesis only (trellis_main_ghdl.mk, yosys -m ghdl -> synth_ecp5)
emard__ulx3s_c64	dirs: ./rtl/test	none: ghdl used for synthesis only (trellis_main_ghdl.mk, yosys -m ghdl -> synth_ecp5)
emard__usb_host	dirs: ./tb;1 tb/test files;tools: iverilog
emard__verilog_tic-tac-toe	tools: verilator
embeddeddojo__ulx3s_examples	dirs: ./basic/binary_decoder/tb ./basic/pll_counter/tb;2 tb/test files;tools: iverilog	make sim (iverilog) x2: basic/binary_decoder/tb/hex2bin_decoder_tb.v - self-checking (PASS/FAIL display); basic/pll_counter/tb/nbit_counter_tb.v - waveform-only, no check
emeb__orangecrab-litex-adc	tools: cocotb	hw/deps/valentyusb/sim/Makefile:(cocotb include) [cocotb]: cocotb test-*.py testbenches for the vendored ValentyUSB core only - self-checking (cocotb assertions/pytest); does not exercise the SDR/DDC gateware itself
emeb__orangecrab_adc	dirs: ./gateware/nmigen/tests;2 tb/test files;tools: verilator,iverilog
emeb__rpi_rxadc	1 tb/test files;tools: verilator,iverilog
emeb__ulx3s_6502	1 tb/test files;tools: verilator,iverilog
emeb__up5k_osc	2 tb/test files;tools: verilator,iverilog
emeb__up5k_vga	1 tb/test files;tools: verilator,iverilog
enjoy-digital__litedsp	dirs: ./test ./sim;168 tb/test files
enjoy-digital__liteiclink	dirs: ./test;7 tb/test files
enjoy-digital__litesata	dirs: ./test;14 tb/test files
evansm7__arcdvi	dirs: ./tb;2 tb/test files;tools: iverilog	make sim (iverilog): tb/tb_top.v -> tb_top.vcd via vvp; tb/tb_comp_video_timing.v buildable too - both waveform-only, no assert/PASS/FAIL found
fm4dd__pmod-7seg9	tools: iverilog	examples/gatemate/config.mk:synth_vhdl (ghdl): none - invokes ghdl only as a Yosys VHDL frontend for synth_gatemate synthesis, not a simulation run (examples/gatemate/config.mk:38-41); no ULX3S-specific sim target found
fm4dd__pmod-charlcd	tools: iverilog	none: icebreaker/{pmod_charlcd,display}/Makefile test target runs iverilog -s <top>_tb ./*.v but no *_tb.v file exists anywhere in the clone (missing testbench, would fail); gatemate/config.mk’s iverilog/ghdl matches are tool-variable assignments (IVL=iverilog) and a VHDL synth recipe, not a run sim
fulig__tinyfpga_fft	2 tb/test files	none found (no Makefile in the repo; apio.ini has no test target; 8FFT/top_tb.v has no automated runner, would need manual iverilog)
fusesoc__blinky	1 tb/test files
fusetim__rusty-soc	tools: verilator,iverilog	hardware/lib/fusetim/spi/Makefile:${DST}/SpiMaster.vvp (iverilog): SpiMaster.v + its _tb.v - self-checking testbench pattern (per repo convention, *_tb.v drives directed vectors and reports pass/fail via $display); …(+2 similar targets for SpiMasterPeripheral variants)
gage1999__fpga-sdr-receiver	dirs: ./icesugar_pro/sim ./icesugar_pro/tests ./icesugar_pro/tb ./plutosky/tests ./tests;23 tb/test files;tools: verilator,iverilog	icesugar_pro/Makefile:sim_fft (iverilog): tb/tb_fft256.sv+src/fft256.sv+butterfly.sv+twiddle_rom.sv - self-checking (PASS/FAIL $display, DC-bin and single-tone peak-bin checks); other sim_* targets (sim_rds, sim_sdram, sim_audio_fifo, sim_i2s_tx, sim_compositor…) also iverilog-run, not all inspected
gatecat__snes_mister_ulx3s	1 tb/test files;tools: ghdl-sim	make -C smpsim run (ghdl): smpsim/smp_tb.vhd exists (identical to emard fork); asserts severity note only, not self-checking PASS/FAIL
ghaworth__ulx3s-bldc-foc	dirs: ./hardware/sim ./gateware/sim
gildobjanschi__riscv_processor	tools: iverilog
glasgowembedded__glasgow	dirs: ./software/glasgow/simulation ./software/tests;23 tb/test files
gmejiamtz__ulx3s-components	1 tb/test files;tools: verilator	make sim / gls / trellis_ulx3s_gls (verilator –binary, builds+runs exe): dv/ulx3s_tb.sv + dv/ulx3s_runner.sv - waveform-only ($dumpvars, no assert/check); make lint is lint-only
gojimmypi__nextpnr-issue235	tools: verilator
gojimmypi__ttgf-uart-fsm-trng-lab	dirs: ./test;8 tb/test files;tools: cocotb,verilator,iverilog	make -C test (cocotb+icarus, SIM=icarus): test/tb.v + test/test.py - self-checking (cocotb asserts on UART bits/response)
gojimmypi__ttgf0p3-analog-uart-fsm-trng-lab	dirs: ./test;8 tb/test files;tools: cocotb,verilator,iverilog	make -C test (cocotb+icarus, SIM=icarus): test/tb.v + test/test.py - self-checking (cocotb asserts on UART response, e.g. response==b”OK\r”)
gojimmypi__ttgf0p3-uart-fsm-trng-lab	dirs: ./test;8 tb/test files;tools: cocotb,verilator,iverilog	make -C test (cocotb+icarus, SIM=icarus): test/tb.v + test/test.py - self-checking (cocotb asserts on UART bits/response)
gojimmypi__ttsky-uart-fsm-trng-lab	dirs: ./test;8 tb/test files;tools: cocotb,verilator,iverilog	make -C test (cocotb+icarus, SIM=icarus): test/tb.v + test/test.py - self-checking (cocotb asserts, e.g. tx_idle==1, response prefix)
gojimmypi__ulx3s-examples	tools: verilator
gojimmypi__z80386-ulx3s-doom	tools: verilator
gonsolo__borg	dirs: ./hardware/borg/test ./hardware/memory/test ./hardware/peri/test ./hardware/hutt/test ./hardware/soc/test;7 tb/test files;tools: cocotb,verilator,iverilog	test/soc/Makefile (cocotb include): test/soc/{tb.v,tb_qspi.v}+test_rv32_boot.py - self-checking (cocotb asserts, test_rv32_boot.py); Makefile:lint/lint-wafer (verilator): lint only, not sim; asic/wafer.space/Makefile sim-* targets are ASIC gate-level sims, not ULX3S-specific
google__cfu-playground	dirs: ./common/_sim/sim;14 tb/test files;tools: verilator	proj/proj.mk:pytest (pytest/unittest): proj//test_.py - self-checking (unittest assertions), not ULX3S-specific; common/_sim/sim/ (14 files, verilator) are CFU functional testbenches run per-project, not via one scanned make target
greatscottgadgets__amalthea	dirs: ./tests; 3 tb/test files
greatscottgadgets__cynthion	dirs: ./firmware/moondancer/test ./cynthion/python/tests;7 tb/test files	none: cynthion/python/Makefile:tests runs python3 -m unittest, which only exercises host-side test_shared.py (USB VID/PID constant check) and firmware/moondancer/test/* (MCU firmware tests) - no gateware simulation
greatscottgadgets__hackrf	dirs: ./hardware/test ./firmware/fpga/test;10 tb/test files
greatscottgadgets__luna	dirs: ./luna/gateware/test ./tests;28 tb/test files;tools: cocotb
gtjennings1__hyperbus	dirs: ./sim;1 tb/test files
hanseo03__ulx3s-custom-riscv-cpu	dirs: ./test ./tb;2 tb/test files;tools: iverilog
hariharan6307-coder__verilog-goertzel-audio-visualizer	5 tb/test files
harrowm__mackerel_030f	dirs: ./pld/mackerel-030f/sim;1 tb/test files
hassan2203__system-on-chip-soc-design-and-verification	1 tb/test files
hdl4fpga__hdl4fpga	dirs: ./boards/ml50x/testbenches ./boards/ULX3S/testbenches ./boards/arty/testbenches ./boards/ULX4M_LS/testbenches ./boards/orangecrab/testbenches;12 tb/test files
heichips__heichips25-template	dirs: ./tb;tools: cocotb	none found (per scan_make_tests.py; make sim invokes cocotb via a Python runner not matched as a Makefile recipe pattern by the scanner)
hoglet67__ice40atom	1 tb/test files;tools: iverilog
hoglet67__ice40beeb	1 tb/test files;tools: iverilog
hsa-ees__piconut	dirs: ./systems/refdesign_c_soft_debugger/test ./sw/verification;tools: iverilog	make -C hw/peripherals/sdram_controller verify-sim (iverilog): sdram_controller_tb/sdram_controller_tb.v - self-checking (custom assert task w/ data compare); make -C systems/test_all verify-sim (sub-make -> sw/verification/riscof, riscof vs sail_cSim ref, self-checking); piconut.mk ghdl path is synth-only
htfab__asicle2	dirs: ./test;tools: cocotb	test/Makefile:(cocotb include) [cocotb]: RTL+GL testbench captures simulated gameplay frames and compares to test/reference/frame*.png - self-checking (per README, image compare)
icebreaker-fpga__icebreaker-verilog-examples	2 tb/test files;tools: iverilog	main.mk %_tb/%_tb.vcd (iverilog): only 2 *_tb.v found (gamepad-audio/pdm_sine_mod_tb.v, gamepad/gamepad_mod_tb.v) - waveform-only ($finish, no assert/PASS-FAIL); rest of tree has no _tb.v
icebreaker-fpga__icebreaker-workshop	tools: iverilog	none: sim rule (%_tb pattern, iverilog) exists in stopwatch/ and stopwatch-dual/ Makefiles but no *_tb.v testbench file present in either clone
icebreaker-fpga__icetwang	dirs: ./sim ./soc/ice-twang/sim;4 tb/test files
im-tomu__foboot	dirs: ./hw/tests;tools: cocotb	hw/deps/valentyusb/sim/Makefile (cocotb, via cocotb-config Makefile.inc/Makefile.sim): dut.v+tb.v+test-eptri.py - self-checking (cocotb TestFailure/assertEqual raised on mismatch, hw/deps/valentyusb/sim/test-eptri.py:109-115)
ipmgroup__fftd	dirs: ./hardware/rtl/tests ./hardware/sim;15 tb/test files;tools: verilator,iverilog	hardware/sim/Makefile:%.vvp (iverilog): tb_fft_full.v - self-checking (test_pass/test_fail counters, PASS/FAIL/checksum-mismatch $display, tests SPI protocol+status not FFT math); tb_fft_verify.v/tb_fft_core.v/tb_fft_compare.v - waveform/print-only (BRAM dump or per-cycle $display, no assert)
jadephilipoom__ulx3s-experiments	dirs: ./tests
jamchamb__cojiro	1 tb/test files;tools: iverilog	none: sim rule (top_tb/top_tb.vcd, iverilog) defined but top_tb.v testbench file not present in clone
jamesbowman__swapforth	1 tb/test files;tools: verilator,iverilog	j1a/icarus/Makefile:test_stack2pipe4.v (iverilog): stack2pipe4_tb.v - waveform/trace-only ($display of state, no pass/fail check); j1a/Makefile:bootstrap and j1b/Makefile:bootstrap/verilator targets build/verilator-simulate the J1 core interactively (Forth REPL boot), not self-checking regression tests
jamesrosssharp__1_bit_am	dirs: ./test;tools: iverilog	make -C test/ sim (iverilog) x6 (001_NCO,002_MIXER,003_CIC,004_AM_DEMOD,005_AM_GEN,006_AM_LITE): each has tb.v - waveform-only, no assert/PASS-FAIL found
jamesrosssharp__ulx3s_mixer_pcb	dirs: ./hdl/test;tools: iverilog	make -C hdl/test/ sim (iverilog) x8 (001_NCO..008_DPLL): each has tb.v - waveform-only, no assert/PASS-FAIL found (one false grep hit was module name only)
jamon__jspcpu	11 tb/test files;tools: iverilog	make sim (verilator, builds+runs Vcpu): cpu_tb.cpp - waveform-only, no assert; make -C core sim: core_tb.cpp - self-checking (asserts); make -C control sim: control_tb.cpp/.sv - self-checking; make -C alu sim: alu_tb.cpp/.sv - self-checking. iverilog target in core/ mismatched (expects core_tb.sv, file is tests_tb.sv)
jderobot__fpga-robotics	2 tb/test files;tools: verilator	none: all verilator targets (examples/, tutorial/, poc/, paper_verilator_ws) only build obj_dir/V*.h + link an interactive SDL2/ImGui/OpenCV GUI binary; no make target runs it and no self-check found - not automated testbenches
jeli180__shape-inference-soc	dirs: ./sim ./tb;9 tb/test files;tools: iverilog
jlopezr__mini-gpu	dirs: ./17.fpga-gpu-ram-v2/sim ./14.fpga-gpu-ram/sim ./22.fpga-gpu-bl8/sim;208 tb/test files
joaln27__cordic	dirs: ./test;2 tb/test files;tools: cocotb	test/Makefile:(cocotb include) [cocotb]: test/{tb.v,test.py,unit_cordic.py} - self-checking (cocotb drives all-angle/DDS-code sweeps and compares against a Python reference CORDIC/atan2 model)
joaln27__koti	dirs: ./test;23 tb/test files;tools: cocotb
joshajohnson__ecp5-mini-projects	dirs: ./verilog/fade/sim ./verilog/usb_serial/sim ./verilog/common/sim ./verilog/wtfpga/sim ./verilog/blink/sim;7 tb/test files;tools: iverilog	make -C verilog/ simulate (iverilog, common.mk): 6/24 proj dirs have _tb.v (blink,clock,fade,nightrider,usb_serial,wtfpga) - $finish only, no PASS/FAIL, waveform-only; other dirs lack a tb.v so target fails
kbeckmann__tt08-flame	dirs: ./test ./web/src/sim;tools: cocotb	test/Makefile (cocotb, icarus): tb.v+src/{hvsync_gen,scale_rom,tria,tt_um_top,voice}.v - test/test.py runs 25000 clock cycles but its check is commented out (# assert dut.uo_out.value == 50), so nothing is actually asserted: waveform-only, not self-checking
kbob__icebreaker-candy	dirs: ./sim;2 tb/test files;tools: iverilog	make -C queue %_tb/%_tb.vcd (main.mk, iverilog): queue/top_tb.v - only tb file matching pattern in repo (23 other dirs lack one); pdm/Makefile test (iverilog): pdm.v is itself tb module top_tb, $stop only - waveform-only
kelu124__lit3rick	dirs: ./verilog/src/tb;1 tb/test files
kelu124__un0rick	dirs: ./usb/verilog/sim
krishkc5__trng-ring-oscillator	dirs: ./tb;1 tb/test files;tools: cocotb,verilator	make sim (verilator C++ model, tb/sim_trng.cpp): collects bits, no PASS/FAIL - not self-checking; make cocotb (cd tb && make SIM=verilator): tb/test_trng.py - self-checking (assert entropy/ratio); make lint=verilator –lint-only, not sim
kulp__tenyr	dirs: ./test ./hw/verilog/sim;5 tb/test files
l0r3m1psum__videogame_verilog	tools: iverilog
lawrie__apple-one	3 tb/test files;tools: iverilog	none (make): boards/*/yosys/Makefile %_tb.vvp/%_tb.vcd (iverilog) pattern needs %_tb.v beside board sources - none exist under boards/; real tb (apple1_tb.v,uart_tb.v,vga_tb.v in tools/iverilog/) run via shell scripts not make - $finish only, no PASS/FAIL
lawrie__blackicemxbook	dirs: ./Simulation ./examples/sim;tools: verilator	examples/verilator/Makefile:sim [verilator]: thruwire.v via verilator+g++ harness - self-checking status unclear (custom C++ tb, no PASS/FAIL string seen, not run); none found in scan_tests-flagged dirs otherwise (Simulation/ is a .md chapter, examples/sim/ not inspected further)
lawrie__fpga_pio	dirs: ./sim;tools: iverilog	make -C sim sim (iverilog): sim/tb.v - runs pio core ~100 cycles, $dumpvars+$finish, no PASS/FAIL/assert - waveform-only
lawrie__fpgacosmacelf	dirs: ./verification
lawrie__hdmi_examples	tools: iverilog	none: every Makefile (root, ball_paddle/, hdmi_pmod_mx/, hdmi_pong/, hdmi_test/, hdmi_test_ibr/, hdmi_test_mx/) defines a tb: tb.v $(VERILOG_FILES) + sim: tb target, but no tb.v file exists anywhere in this clone, so none of the sim targets can actually run
lawrie__ice40logicsniffer	1 tb/test files;tools: iverilog
lawrie__ulx3s-nmigen-examples	dirs: ./camera/sim ./opc/tests;11 tb/test files;tools: iverilog	none: opc/tests/Makefile %.exe (iverilog) compiles ../opc6tb.v ../opc6cpu.v but neither file exists anywhere in the clone
lawrie__ulx3s_atari_2600	dirs: ./roms/tests
lawrie__ulx3s_cpm_z80	dirs: ./src/Test;2 tb/test files
lawrie__ulx3s_examples	1 tb/test files;tools: iverilog	make -C ps2send tb/sim, make -C test68 tb/sim (iverilog): ps2send/tb.v, test68/tb.v exist, $finish only - waveform-only; sdram16 & sdram8 tb/sim targets broken (ulx3s.mk copy-paste bug, missing test68.v/tb.v); basics/sum_vhdl uses ghdl for synthesis only
lawrie__ulx4m_amaranth_examples	3 tb/test files
lawrie__ulx4m_examples	1 tb/test files
lawrie__verilog_examples	tools: iverilog	none: fpga4fun/main.mk defines %_tb, %_tb.vcd, %_syntb, %_syntb.vcd targets (iverilog+vvp, vvp writes a .vcd) but no *_tb.v testbench source files exist anywhere in this clone, so the rules cannot actually run
lazardjurovic__edulent_rtl	dirs: ./rtl/tb;5 tb/test files;tools: verilator	verilator_scripts/Makefile:build/run (verilator, via $(VERILATOR) var - missed by scanner): tb/control_mov_tb.sv+src/control_unit.sv - waveform-only (dumps dump.vcd via testbench.cpp, no self-check found)
lfglabs-dev__lean-silicon	dirs: ./test ./sim ./fpga_harness/tests;64 tb/test files;tools: cocotb,iverilog	make -C test stream-alu/uart-bridge/packet-uart-bridge (iverilog): tb_stream_alu.sv etc - self-checking ($fatal on mismatch + PASS/$finish); make formal (sby): 16 .sby proofs under formal/ (gf8/gf128 mul, lsc1u protocol/reachability/xor_refinement, netlist_eq, etc); other targets are python unittest/pytest, not RTL sim
litex-hub__linux-on-litex-vexriscv	dirs: ./test;2 tb/test files
litex-hub__litex-boards	dirs: ./test;12 tb/test files
lucasebskora__wav-player	tools: verilator
machdyne__tinydfu-bootloader	dirs: ./testbenches;1 tb/test files	none: testbenches/i2c_master_tb.v has no make target in any boards/*/Makefile that runs iverilog/vvp on it - the tb exists but is never invoked from a build rule
machdyne__zeitlos	dirs: ./rtl/tests ./rtl/tb ./sim ./tools/ask/tests ./sw/test;57 tb/test files;tools: iverilog	make test_uart/test_usb/test_usb_cosim/…/test_blit (iverilog): rtl/tb/tb_*.v - self-checking (PASS/FAIL/$fatal); make -C rtl/cpu/zeitlos32/tests run/random/one (iverilog): tb_zeitlos32.v - self-checking (shell greps PASS/FAIL, directed+random diff tests)
makisness__inductiq	dirs: ./hdl/tb;1 tb/test files
mangelajo__orangecrab-usb	2 tb/test files;tools: cocotb	make -C hdl/i2s, make -C hdl/clkdiv (cocotb+icarus): test_i2s.py, test_clkdiv.py exist - self-checking (assert)
markus-zzz__hyperram-test	dirs: ./sim;tools: verilator
markus-zzz__max9850-test	dirs: ./sim;tools: verilator
markus-zzz__myc64	dirs: ./sim;tools: verilator
markus-zzz__zzz-rv	dirs: ./sim ./tests;tools: verilator,iverilog	Makefile:out/obj_dir [verilator] - waveform-only (Verilator C++ sim, sim/cpu-sim.cpp drives it, no automated pass/fail seen at this level); Makefile:out/soc.vvp / sim-iverilog [iverilog]: sim/sim-top.v + syn/ulx3s-top.v + Micron SDRAM model - not confirmed self-checking (no PASS/FAIL/$error found in sim/sim-top.v; likely waveform/log inspection)
marph91__pocket-bnn	dirs: ./submodules/icestick-uart/sim ./sim;11 tb/test files;tools: cocotb,ghdl-sim	make sim -> cd sim && pytest (cocotb+ghdl, SIM=ghdl set in conftest.py): sim/test_*.py (bnn, bnn_uart, convolution, pooling, etc.) - self-checking (assert)
marph91__yaaes	dirs: ./sim;tools: vunit
mattvenn__fpga-sdft	dirs: ./tests;5 tb/test files;tools: iverilog	Makefile:$(BUILD_DIR)/%.out and %.vcd (iverilog): tests/sdft_tb.v, top_tb.v, twiddle_rom_tb.v, freq_bram_tb.v, complex_mult_tb.v - waveform-only (no PASS/FAIL/assert in any tb; python/read_vcd.py + make model-sdft compare against numpy externally, not in-sim)
maxhpc__ecpix-5	dirs: ./vx/tb;tools: verilator	vx/tb/Makefile:all (verilator): tb.cpp+maxhpc.sv+vx_stub.sv - waveform-only (no assertions in tb.cpp; runs 200000 cycles, prints timestamps; requires external VORTEX_HOME/VX_gpu_pkg.sv not vendored)
maxzischka1__fastfouriertransformproject	1 tb/test files;tools: verilator	Makefile:waveform_TopLevel.vcd (verilator, tb_TopLevel.cpp): TopLevel.sv+SDFCell.sv+SBM16.sv+… - waveform-only (harness only dumps a VCD; no PASS/FAIL/assert found in tb_TopLevel.cpp)
mb-sat__ulx3s-longwave-sdr	dirs: ./testbench
mcejp__poly94	dirs: ./rtl/sim ./sim ./lib/verilog-uart/tb;3 tb/test files;tools: cocotb,verilator	make sim (verilator C++ model, sim/sim_main.cpp+rtl/top.sv): runs, no PASS/FAIL - not self-checking; make -f Makefile.coco (cocotb+icarus): rtl/sim/top_sim.sv, test_my_design.py - self-checking (assert); lib/verilog-uart/tb/uart_rx,uart_tx (cocotb): self-checking
mebner86__icesugar-pro_sound2fft	dirs: ./tests;27 tb/test files;tools: cocotb,verilator,iverilog	Makefile test (cocotb, via cocotb-config include): tests/test_/.py - self-checking (DUT vs Python/numpy reference model, e.g. test_pdm_cic); projects/*/Makefile $(VVP)/$(VCD) (iverilog): *_tb.v - self-checking via $display PASS/FAIL text in most (e.g. 09_pdm_sigma_delta_modulator, 13_fft_uart), but some (06_live_fft) are waveform-only
meharbaan2__systemverilog-ofdm-phy-core	dirs: ./sim ./tb;3 tb/test files;tools: verilator
michaelbell__nanov	11 tb/test files;tools: cocotb,verilator	test_cpu.mk/test_alu.mk/test_core.mk/test_register.mk/test_soc.mk (cocotb+icarus via make -f test_X.mk): tb_.v + test_.py - self-checking via cocotb assertions in Python; pico_ice/Makefile’s verilator lint line is commented out, never run
micki0271__maeri	dirs: ./test ./maeri/compiler/tests;7 tb/test files
mikeakohn__apollo11_fpga	dirs: ./test
mikeakohn__riscv_fpga	dirs: ./test;1 tb/test files
mit-plv__koika	dirs: ./tests ./examples/rv/tests;tools: verilator,iverilog	make -C examples/rv verilator-tests/cuttlesim-tests: compiled RV32I core (Coq-generated Verilog) run via Verilator/Cuttlesim C++ models against tests/*.rv32/.vmh - self-checking via exit status; compiler-level test, no hand-written tb file; ghdl/iverilog not used
mithro__asus-d16-ulx3s-interface	dirs: ./test ./sim
mkvenkit__learn_fpga	dirs: ./ice40up5k/i2s_mic/tb;2 tb/test files;tools: iverilog	make -C ecp5_ulx3s/uart_tx sim, ice40up5k/spram_test sim (iverilog): testbench.v - $finish only, waveform-only; ice40up5k/i2s_mic sim: tb/tb_i2s_receiver.v - self-checking (PASS/FAIL); picosoc_gpio spiflash_tb: spiflash_tb.v self-checking; lice40upsim/synsim broken (lice40up_tb.v missing)
mmicko__fpga101-workshop	dirs: ./tests;3 tb/test files
mole99__tt05-one-sprite-pony	dirs: ./tb;2 tb/test files;tools: cocotb,verilator,iverilog	Makefile:sim-icarus (iverilog): tb/tb_icarus.sv - waveform-only (dumps tb.fst, no assert seen); Makefile:sim-cocotb (cocotb): tb/tb_cocotb.py - self-checking (assert(not diff.getbbox()) image-compare vs software render, tb/tb_cocotb.py:290); Makefile:sim-verilator (verilator): tb/tb_verilator.cpp - not inspected further
mpardalos__clash-blinky	dirs: ./tests ./tests/Tests
msiddalingaiah__centurion	tools: iverilog	Verilog/Makefile:test / CPU6TestBench (iverilog+vvp): CPU6TestBench.v runs programs/*.txt against CPU6.v - not self-checking (no PASS/FAIL $display, only $finish); verification is via VCD waveform trace inspection (see parse_vcd.py), per README
msinger__iceboy	dirs: ./sim ./sim/test ./tests	tests/Makefile.am (sby/SymbiYosys, via generated alu/.sby cpu/ld8|ld16/.sby): formal property checks per ALU op / CPU instruction - self-checking (SymbiYosys BMC/prove pass/fail, not a waveform sim); sim/Makefile.am (verilator, nodist_sm83_sim_SOURCES generated design.cc): sm83_sim.cc / sm83_dbg_ifc_sim.cc against sim/test/sm83/* vectors - self-checking (compares simulated CPU trace to test vectors, check_PROGRAMS)
mysteriouswolf__vna_fpga_dsp	dirs: ./adc_counter/testbench ./raw_meas_ram/testbench ./testbench; 2 tb/test files
mystorm-org__blackice-ii	tools: iverilog	none: all three found Makefile sim/tb targets (examples/uart_loopback, examples/hello_world, examples/sram) only dump waves.vcd via $dumpvars and $finish - no $display/assert self-check; examples/sram/src/tb.v drives a trivial SRAM stub (DAT=ADR echo) for waveform inspection only
nicocavallu__rf-dds-lo	dirs: ./sim;2 tb/test files;tools: iverilog
nicocavallu__rf-sdr-frontend	dirs: ./sim ./modules/rf-dds-lo/sim;6 tb/test files;tools: iverilog
nklabs__libnklabs-ulx3s	dirs: ./fw/libnklabs/tests;3 tb/test files
nkrackow__singularitysurfer-fpga-lock-in-amplifier	4 tb/test files;tools: iverilog	make -C FPGA/HDL sim (top_tb.vvp, iverilog): top_tb.v - waveform-only ("hallu world" placeholder $display, no PASS/FAIL); make -C FPGA/HDL/filter CICsim (CIC_tb.vvp, iverilog): CIC_tb.v - same placeholder, waveform-only; make -C FPGA/HDL/cordic cordicsim (tb.vvp, iverilog): tb_cordic.v - prints computed angle/sin/cos/error via $display, no assert/PASS-FAIL, waveform+log-only; make -C FPGA/HDL/UI sim (top_UI_tb.vvp, iverilog): top_UI_tb.v - waveform-only
no2fpga__no2bootloader	dirs: ./gateware/ice40/sim ./gateware/ice40-stub/sim;5 tb/test files
noxharmonium__sirc	dirs: ./sirc-vm/toolchain/tests ./sirc-vm/libsirc/tests ./sirc-vm/sirc-vm/tests ./sirc-vm/peripheral-bus/tests ./sirc-vm/peripheral-cpu/tests (Rust unit tests, not HDL testbenches)
nullobject__m68k-ulx3s	tools: verilator	make sim (verilator): sim_main.cpp drives hdl/gpu.v, no dedicated tb file - waveform-only (VCD dump), no PASS/FAIL check
nullobject__riscv-ulx3s	tools: verilator	make sim (verilator): sim_main.cpp drives hdl/top.v, no dedicated tb file - waveform-only (VCD dump), no PASS/FAIL check
nusgreyhats__greybadge25	dirs: ./firmware/ecp5/tests
obijuan__open-fpga-verilog-tutorial	95 tb/test files;tools: iverilog	~95 per-lesson make sim targets (ICE40-HX8K_Breakout_Board, ICESTICK, Alhambra_II Makefiles, e.g. T04-counter/Makefile): iverilog compiles .v+_tb.v, vvp runs it, self-checking via $display ERROR-on-mismatch (spot-checked counter_tb.v), dumps vcd and opens gtkwave (interactive, not required for pass/fail); TinyFpgaBx/Makefile `sim` target is the same pattern, reusing ICESTICK lesson sources.
openconcepts-ar__accel2d	2 tb/test files (false positive: these are demos/micropython/*_test.py demo scripts, not testbenches)
orangecrab-fpga__orangecrab-examples	tools: cocotb	make -C litex/deps/valentyusb/sim (cocotb+icarus): cocotb-tb.v + test-cdc-eptri.py - self-checking (cocotb asserts/TestFailure); dut.v (DUT) is generated at test time by Migen, not a static file in the clone
orbcode__orbtrace	dirs: ./tests;10 tb/test files
osmocom__osmo-e1-hardware	dirs: ./gateware/icE1usb/sim;1 tb/test files
osresearch__up5k	tools: iverilog	none: Makefile.icestorm defines test: $(TEST-y) but TEST-y is never set by the root or usb/ Makefiles that include it - test target is effectively empty (no-op)
ox-computing__real-time-analytics-fpga	dirs: ./verification ./wesad/tb;11 tb/test files;tools: cocotb
p-kraszewski__cs-ulx3s-03	tools: verilator
pavlenkog__ecp5_pcie_analyzer	dirs: ./fpga_logic/sim;3 tb/test files;tools: vunit
pmezydlo__beaglewire	dirs: ./examples/test
pnru__ti99	1 tb/test files
punchthatface__tinydma	dirs: ./tb;5 tb/test files
quigleyj97__nesgate	tools: cocotb
racerxdl__colorlight-picorv32	tools: iverilog
rainbow1128__vhdl-aes-master	dirs: ./sim;tools: vunit
ranzbak__fpga-workshop	11 tb/test files;tools: iverilog	make -C sim (iverilog) in 11 example dirs (03-blink..14-smooth-fade): _tb.v - self-checking ($display SUCCESS + $stop on cycle-count mismatch)
reddocmd__klaus	dirs: ./test
remyciterin__3driscv	dirs: ./UberDDR3/testbench ./simulation;3 tb/test files;tools: verilator,iverilog	none: verilator/simulate targets need Verilog/*.v generated by the Blarney (cabal) build - Verilog/ dir absent from clone; static src/SimTop.v alone is insufficient
remyciterin__adventoffpga	tools: verilator	none: gpu_firmware verilator target forwards to ../3DRiscV, which is an empty unfetched git submodule in this clone - no source to simulate
remyciterin__dooom	dirs: ./simulation;tools: iverilog	none: link/simulate need bsc-generated rtl/*.v (Bluespec, rtl/ empty in clone); ram_simulate’s simulation/test_sdram.v exists but is waveform-only ($finish, no checks) and also needs the missing rtl/mkTop.v
rhobbie__library704	dirs: ./Library704/Testbench;tools: iverilog
riltonf__thermal_camera_ulx3s	dirs: ./src/test;25 tb/test files;tools: verilator,iverilog
rj45__vdp	dirs: ./sim;2 tb/test files;tools: verilator,iverilog	make test (iverilog): rtl/pixel_doubler_tb.sv self-checking (assert+$display PASS), rtl/fp_div_tb.sv waveform-only ($finish); make sim (verilator+SDL): sim/top_test.sv - visual sim only, no PASS/FAIL
rob-ng15__pawsv2	tools: verilator
robinsonb5__eightthirtytwodemos	dirs: ./EightThirtyTwo/vbcc/test;2 tb/test files	none: EightThirtyTwo/test.log runs the VBCC C compiler’s regression suite against the 832 CPU emulator (832emu) - a software toolchain test, not an RTL testbench; no *_tb.v/.sv anywhere in repo
romavis__lwdo-sdr-fw	dirs: ./fpga/test;1 tb/test files;tools: cocotb,verilator,iverilog	fpga/Makefile:$(OUT_TEST_DIR)/test_% (iverilog): fpga/test/test_.v (12 files) - waveform-only per README ("non-asserting", VCD dump, no PASS/FAIL); fpga/3rdparty/verilog-axis/tb//Makefile (cocotb include): cocotb self-checking tests for the vendored verilog-axis AXI-Stream cores only, not LWDO’s own DSP logic
rschlaikjer__fpga-3-softcores	dirs: ./test ./sim;8 tb/test files
rxrbln__picorv32	dirs: ./tests;6 tb/test files;tools: verilator,iverilog	Makefile:test/test_vcd/test_wb/test_wb_vcd/test_ez/test_ez_vcd/test_sp/test_axi/test_synth (iverilog): testbench.v(+_wb/_ez/_synth)+picorv32.v+tests/*.S - self-checking (magic MMIO word, tb checks trap/register state); Makefile:test_verilator (verilator): same via verilated C++; picosoc/Makefile:hx8ksim/icebsim (iverilog): hx8kdemo_tb.v/icebreaker_tb.v+picosoc.v+firmware - self-checking (simpleuart completion); picosoc/Makefile:ulx3sim/ulx3synsim (iverilog): would need picosoc/ulx3s_tb.v, MISSING from this clone - cannot run
sangwoojun__ulx3s_bsv	dirs: ./projects/test
saul-rodriguez__ulx3s	5 tb/test files;tools: verilator,iverilog	make -C picoRV32_rom sim (iverilog): vargen_tb.sv exists - waveform-only ($finish only, no PASS/FAIL check)
schlae__graphics-gremlin	tools: iverilog	verilog/Makefile:%.vcd (iverilog): isavideo_t.v (top-level testbench) + is61_tester.v (SRAM model self-test) - waveform-only (%.vcd: recipe just runs iverilog+vvp to produce a .vcd, no PASS/FAIL check visible in isavideo_t.v/is61_tester.v; described by verilog/README.md as “a sloppy test bench… used to validate and troubleshoot”)
secworks__cryptkey	dirs: ./cores/trng/tb ./cores/uart/tb ./cores/uds/tb ./cores/timer/tb;5 tb/test files;tools: verilator,iverilog
sefbkn__versa-ecp5-demo	dirs: ./sim;1 tb/test files;tools: iverilog
semify-eda__waveform-generator	dirs: ./design/wfg_core/sim ./design/wfg_core/testbench ./design/wfg_subcore/sim ./design/wfg_subcore/testbench ./design/wfg_interconnect/sim;17 tb/test files;tools: cocotb,verilator	make -C design/wfg_{core,subcore,interconnect,top,drive_spi,stim_sine,stim_mem,drive_pat}/sim (cocotb+icarus, default SIM): test_wfg_*.py - self-checking (asserts), all 8 testbenches present
seminlim__bluerv32	dirs: ./tests	make test-directed/test-random/test-differential/test-act4 (sub-make tests/): builds bsim (bsc->mkTop_bsim, full CPU RTL in Bluespec) then runs RISC-V ISA test programs - self-checking (expected pass/trap-cause comparisons)
seminlim__blueyosys	dirs: ./projects/sway_observation/sim;tools: iverilog	build.mk:bsim (iverilog, via bsc -vsim iverilog): bsc-generated Bluesim/iverilog harness - self-checking unknown, not directly inspected; projects/sway_observation/Makefile:sim-runner (iverilog): just packages the bsim output into a runnable vvp wrapper, not the sim itself
seminlim__sway	dirs: ./hw/sim;7 tb/test files;tools: iverilog	hw/Makefile:sim-runner [iverilog] - self-checking (runsim pipes system.log through hw/reference/check_sim.py, which diffs the simulator transcript against exported INT8 hex fixtures)
seth16225__riscv-core-portfolio	tools: cocotb,iverilog	common/make/fpga.mk:test (pytest/cocotb): cached-core/testbench.py, axil-core/testbench.py - self-checking (assertEquals vs register/trace values); carry-lookahead-adder/Makefile:formal (sby): check-cla.sby - self-checking (SAT proof)
smunaut__had2019-playground	dirs: ./cores/misc/sim ./cores/usb/sim;7 tb/test files;tools: iverilog	none: build/core-rules.mk $(BUILD_TMP)/%_tb rule compiles cores//sim/_tb.v and project testbenches with iverilog but never invokes vvp - waveform dump only, same rule as emard__had2019-playground’s fork
smunaut__ice40-playground	dirs: ./projects/riscv_doom/sim ./projects/usb_amr/sim ./projects/riscv_usb/sim ./projects/rgb_panel/sim ./projects/usb_audio/sim;27 tb/test files
smunaut__ice40linux	dirs: ./firmware/test ./gateware/riscv_linux/sim;2 tb/test files
smunaut__mch2022-ice40	dirs: ./projects/riscv_doom/sim ./projects/selftest/sim ./projects/tinygpu_doom/sim ./cores/spi_slave/sim;5 tb/test files
speccery__icy99	1 tb/test files;tools: iverilog
spinalhdl__saxonsoc	dirs: ./test ./software/standalone/test	none: deprecated icestorm/makefile has a %_tb pattern rule but no *_tb.v files exist anywhere in the tree and nothing depends on it by default
splinedrive__kianriscv	1 tb/test files
spritetm__hadbadge2019_fpgasoc	dirs: ./soc/picorv32/tests ./soc/sim;3 tb/test files;tools: verilator,iverilog	make -C soc/qpi_cache {qpimem_iface,interleave,cache}_testbench + make -C soc pcpi_fastmul_dsp_testbench (iverilog): self-checking ($display mismatch+$finish); make -C soc[/video] verilator: full SoC/video SDL sim - visual/waveform only, no PASS/FAIL
stereoninja__stereoninjafpga	tools: verilator
stnolting__neorv32	dirs: ./sim;2 tb/test files;tools: verilator,iverilog,ghdl-sim	make -C rtl/verilog sim (iverilog or verilator): ghdl converts the VHDL core to Verilog then runs neorv32_verilog_tb.v - self-checking (“Simulation successful!” vs timeout $finish)
sylefeb__a5k	tools: verilator	none: simul% -> make -C hardware verilator uses Silice’s auto-generated verilator+SDL harness to play the game - functional/visual sim only, no PASS/FAIL check
sylefeb__silice	dirs: ./python/tests ./tests;tools: verilator,iverilog	tests/, tests/error_checks/, tests/issues/ Makefiles (.DEFAULT: silice-make.py -b verilator): 378 per-test .si regression targets, invoked via test_all.sh not a single make target; self-check unverified per file. Demo Makefiles (fire-v,ice-v,terrain,spiflash,tinygpus) verilator targets are SDL visual sims, not self-checking
sylefeb__tinygpus	tools: verilator	demos/Makefile:simulation (verilator): not ULX3S-related (demo GPU-core simulation harness); self-checking status not inspected further (out of scope, no ULX3S build exists)
tadeoroboticsgroup__axiomacore-328	dirs: ./legacy/scripts/verification ./legacy/testbench ./sim ./sim/tb ./sim/diff/tests;12 tb/test files;tools: cocotb,verilator,iverilog	make sim-alu/sim-sreg/sim-spi/sim-gpio/sim-timer2/sim-twi/sim-spm/… (~40 targets, Makefile) (verilator): sim//tb_.cpp C++ testbenches built and run per-target - self-checking against golden/oracle vectors (e.g. sim-alu -> alu-vectors, tb_alu.cpp); lint/check-tools are lint-only/tool-presence checks, not simulations
tallenintegsys__hdmi-orangecrab	1 tb/test files;tools: iverilog	none: sim target compiles verilog/serializer_tb.sv with iverilog but the recipe never runs it (missing “vvp serializer” step) - simulation never executes; tb is waveform-only ($finish, no checks) anyway
tarik-hamedovic__sdr-hls	dirs: ./3.Testing/1bitADCLattice/Testbench ./5.NewModules/MyCIC/Testbench;2 tb/test files;tools: cocotb,verilator,iverilog	make run/test (cocotb+icarus) in 1.RTLImplementation/2.sim/{CIC,Mixer,Multiplier,NCO,PWM,UartRx,AMDemod,top}, 3.Testing/1bitADCLattice/Testbench, 5.NewModules/{CORDIC/,MyCIC/Testbench/}: self-checking asserts (CIC, ADC verified); CORDIC-Comb2 is waveform/FFT-plot only, no assert; ghdl elsewhere used for synthesis only
td0034__fpga	tools: iverilog	none: ulx3s/icesugar Makefile.inc sim (iverilog compile+vvp of $(SRC)) is a generic template; no example dir (blinky, sdcard, oled_wave, granular-synth-engine, icesugar examples) has a _tb.v file in the clone - just synthesizable RTL
techprototyper__trs80-rev-z	dirs: ./boards/ulx3s/sim ./sim;46 tb/test files;tools: verilator	make -C boards/ulx3s/sim run (verilator; scanner only saw sub-make hex deps): tb_tmds.sv, tb_scan_fb.sv, tb_hid_keys.sv, tb_selftest.sv, tb_dbg_uart.sv, tb_sd_loader.sv, tb_sd_fs.sv, tb_dmk_fetch.sv, tb_cass_sd.sv - all self-checking ($display PASS/FAIL, “ALL CHECKS PASSED”)
thata__td4-ulx3s	tools: iverilog	make test (iverilog): cpu_test.v - waveform/monitor-only, no PASS/FAIL check (source comment says “just $display out”)
thata__ulx3s-playground	tools: iverilog	make -C bram_controller test (iverilog -g2012): bram_controller_test.sv - self-checking (assert(…) else $error, 13 checks, $finish)
theperfectcomputer__learn-clash	dirs: ./tests ./tests/Tests
theperfectcomputer__mannachip	dirs: ./tests;1 tb/test files;tools: iverilog	make sim (bsc Bluesim) / make verilog-sim (bsc verilog+iverilog): bs/Top.bs is mkTop itself (no separate tb) + bdpi/uart_sim_device.c - interactive UART terminal loopback, no PASS/FAIL self-check found
thewbi__ulx3s	1 tb/test files
thezoq2__tinytapeout02	dirs: ./test;tools: cocotb	smolfpga/src/Makefile (cocotb, icarus): tb.v+counter.v+decoder.v - smolfpga/src/test.py self-checking (asserts 7-segment values), but this only tests the smolfpga SUBMODULE, not thezoq2’s own Spade top; no Makefile-based runner found for the top-level test/*.py (those run via swim test, see notes)
thorkn__vexriscv-ulx3s-helloworld	dirs: ./vexriscv/src/test;tools: verilator	none wired to top Makefile (only builds bitstream/elf/openocd); vendored vexriscv/src/test/cpp/{murax,briey} verilator harnesses not self-checking (boot+perf report only); …/regression make run (verilator) is self-checking (PASS/FAIL per test) but needs generated VexRiscv.v not present in clone
tinyfpga__tinyfpga-bootloader	dirs: ./tests;tools: iverilog	make -C tests/ test (iverilog): test.v + common/*.v via ../file_list.txt - self-checking (vtg.ok()/assert inside expect_usb_ack() etc., TAP-style, 29 test dirs e.g. tests/simple_spi_in_test)
tinyvision-ai-inc__pico-ice-sdk	tools: verilator,iverilog	make (iverilog) ice_makefile_iverilog_counter: testbench.sv - waveform-only ($dumpvars,$finish, no check); make (verilator) ice_makefile_verilator_counter: verilator.cpp - also waveform-only, no assert/PASS-FAIL
toasterllc__mdccode	dirs: ./Sim;tools: iverilog
tom7980__ulxws	tools: verilator
tomverbeure__ecp5_jtag	dirs: ./tb;tools: iverilog	make -C tb (all: tb; ./tb) (iverilog): tb/src/tb.v driving Ecp5JtagDemo.v via JTAGG/jtag_tap - waveform-only ($dumpvars, $finish, no PASS/FAIL)
toni3141__rastericer	tools: verilator	none: rtl/top/Verilator/Makefile simulation only builds a Verilator C++ model of top.v (verilator –cc + make -C obj_dir) - no main()/driver referenced, nothing is ever executed
tristanitschner__ulx3s-examples	1 tb/test files;tools: iverilog	none: sound-dds/Makefile sim references missing sound_tb.v (not in clone); sound-wave/Makefile sim compiles top_sound_tb.v+top_sound.v but never calls vvp (compile-only); that tb is waveform-only anyway ($finish, no check)
tucanae47__litex_etpu	tools: cocotb
tucanae47__ulx3s-experiments	1 tb/test files;tools: cocotb,verilator,iverilog	make (cocotb+iverilog, top Makefile): TopSDD.v + test_clock_ssd.py - runs 4000 clk cycles but has no assert (trivially passes); oled1351/Makefile test_coco (cocotb+iverilog) references missing SSD1351.v/oled.v/dump_ospi.v/test_spi.py - not in clone
ulixxe__usb_cdc	tools: verilator,iverilog	make -C examples/{TinyFPGA-BX,Fomu}/OSS_CAD_Suite sim (iverilog %.fst; scanner only saw %.vvp/%.xml): tb_demo.v(+usb_monitor.v) - self-checking (assert_error macros); IP-level tb for TinyFPGA-BX/Fomu boards, not ULX3S-specific
ultraembedded__core_ddr3_controller	dirs: ./tb
ultraembedded__ecpix-5	none found	make -C src/riscv/{top_cache_axi,top_tcm_axi}/tb run (SystemC+Verilator cosim; scanner only saw sub-make): test.x runs isa_sim/images/{basic,linux}.elf - self-checking (sc_assert handler prints “TEST FAILED”, exit code)
ulx3s__anotherworld_fpga	1 tb/test files
ulx3s__apple2fpga	none found	make timing_testbench.vcd / i2c_testbench.vcd (ghdl -a/-e then run - real VHDL sim, not synthesis, corrects the generic ghdl=synth heuristic): timing_testbench.vhd, i2c_testbench.vhd - waveform-only, no assert/report found
ulx3s__blink	tools: verilator
ulx3s__fpga-odysseus	1 tb/test files
ulx3s__hazard3	dirs: ./test ./test/sim ./example_soc/libfpga/test;tools: verilator	test/sim/test.py (python orchestrator over make -C tb_cxxrtl + coremark/riscv-tests/riscv-compliance/dhrystone/embench/hello_multicore/hellow; scanner missed it): yosys write_cxxrtl DUT + tb_cxxrtl/tb.cpp - self-checking (CPU exit-code via tb_memio.cpp, PASS/FAIL summary)
ulx3s__hazard3-doom	dirs: ./tests;2 tb/test files;tools: verilator,iverilog	none: bootloader/mk/core-rules.mk sim pattern only runs iverilog to compile sim/_tb.v (fifo_tb,uart_tb,pdm_tb,uart_irda_tb,usb_tx_tb,usb_ep_buf_tb,usb_tb) into build-tmp/_tb - never invokes vvp, nothing actually runs
ulx3s__tt-support-tools	2 tb/test files;tools: cocotb	testing/src-tpl/Makefile (cocotb, icarus): test_wokwi.v+cells.v - testing/src-tpl/test.py truthTableCompare self-checking (loads a markdown truth table, asserts DUT I/O against it), but this is a TEMPLATE copied into downstream TT/Wokwi projects, not exercised as a test of this repo itself
ulx3s__ulx3s-examples	tools: verilator
uttamcoomar__mac-units-for-various-number-formats	12 tb/test files
uttamcoomar__nn_digits	dirs: ./tests ./tests/sim;2 tb/test files;tools: cocotb,iverilog	tests/sim/infer/Makefile (cocotb include): test_inference.py - self-checking (assert hw==ref / assert abs(count-EXPECTED)<10%, test_inference.py:122,127,160)
vmware-archive__cascade	dirs: ./share/cascade/test ./test;tools: verilator	none found (CMake-based build, not a Makefile flow; test/ has C++ unit tests likely run via ctest, not detected by the Makefile-only scanner)
volnirr__verilog-uart	dirs: ./tb;2 tb/test files
voltcyclone__hurra-fpga	dirs: ./firmware/ch32h417/test ./firmware/mcxn947/test ./tests;31 tb/test files	Makefile:test (pytest): tests/*.py - self-checking (amaranth.sim.Simulator assertions across 24 files, e.g. test_enumerator.py, test_control.py, test_device_control.py, test_host.py)
voltcyclone__hurricanefpga	dirs: ./HDL/hardware/testbenches;11 tb/test files;tools: iverilog	HDL/hardware/testbenches/Makefile:test_token,test_transaction,test_sof,test_reset,test_descriptor,test_arbiter (iverilog+vvp): tb_usb_*.v - not self-checking (only $display trace output, no pass/fail assert)
vyges__fast-fourier-transform-ip	dirs: ./test ./tb ./simulation;18 tb/test files;tools: cocotb,verilator,iverilog	Makefile.test:test-memory-interface/test-twiddle-rom (iverilog): rtl/memory_interface.sv,twiddle_rom.sv - do not exist (stale names, actual files are fft_memory_interface.sv/fft_twiddle_rom.sv), target fails; tb/cocotb/Makefile (cocotb): VERILOG_SOURCES rtl/fft_top.sv,fft_engine.sv - same stale-name failure; tb/sv_tb/Makefile test_basic/test_rescaling (verilator/iverilog, glob rtl/*.sv): tb_simple.sv/tb_fft_top.sv - self-checking (+test= args), unaffected by the rename
w531t4__fpga_led_display	dirs: ./src/testbenches;39 tb/test files;tools: verilator	make simulation (or make all; scanner only saw lint): mk/verilator.mk builds+runs 39 tb_*.sv in src/testbenches/ via verilator –binary –trace-fst - self-checking (assert/$error/$fatal in all 39 files)
whitequark__yumewatari	dirs: ./yumewatari/test ./yumewatari/testbench;4 tb/test files
wifiboy__ok-ice40pro	tools: iverilog	none: ok-nes-vga-src/Makefile has %_tb/%_tb.vcd/%_syntb pattern rules (iverilog) but no *_tb.v file exists anywhere under ok-nes-vga-src/ in the clone
williamsharkey__pruned-sha256-miner	5 tb/test files
wren6991__hazard3	dirs: ./test ./test/sim;tools: verilator	identical to ulx3s__hazard3 (byte-identical test.py/coremark Makefile/tb_cxxrtl/tb.cpp): test/sim/test.py orchestrator, yosys write_cxxrtl + tb_cxxrtl/tb.cpp - self-checking (CPU exit-code, PASS/FAIL)
wren6991__hazard3-swd-soc	dirs: ./lib/libfpga/test ./lib/opendap/test	make -C lib/opendap/test/{dp,dap}/testcase (all: run.%; ./$<, cxxrtl via yosys write_cxxrtl of opendap_sw_dp.v; scanner only saw sub-make): 24 dp + 5 dap *.cpp test cases - self-checking (tb_assert macro)
wren6991__riscboy	dirs: ./hdl/hazard5/test ./hdl/libfpga/test ./test ./test/ppu/tb ./test/system_cxxrtl/tb;2 tb/test files	test/system_cxxrtl/tb/Makefile (yosys write_cxxrtl + clang++): tb.cpp against riscboy_core.v - self-checking (CPU writes an exit code via MMIO, tb.cpp --cpuret returns it, non-zero = fail); hdl/hazard5/test/coremark/Makefile:tb, hdl/hazard5/test/common/src_only_app.mk:tb (sub-make, tool unresolved from this clone - scripts submodule providing sim.mk not fetched); test/execution/riscv_compliance/Makefile:test, test/system/Makefile:test (sub-make into $(SCRIPTS)/sim.mk): none: cannot run - scripts submodule (fpgascripts, holds sim.mk) not fetched, and test/execution/riscv_compliance/riscv-compliance submodule also not fetched
wuxx__colorlight-fpga-projects	tools: verilator,iverilog	none: src/i5/vga_pong/main.mk has %_tb/%_tb.vcd/%_syntb pattern rules (iverilog) but no *_tb.v file present in vga_pong/ in the clone
wuxx__icesugar	tools: verilator,iverilog	make -C src/advanced/picorv32 test/test_vcd/test_wb/test_wb_vcd/test_ez/test_ez_vcd/test_sp/test_axi/test_synth/test_verilator (iverilog/verilator): testbench.v(+_wb/_ez)+picorv32.v+firmware - self-checking (“ALL TESTS PASSED”); test_rvf needs missing rvfimon.v; icicle syntax is -t null syntax-check only, not sim
wuxx__icesugar-pro	tools: verilator
x653__xv6-riscv-fpga	1 tb/test files;tools: iverilog	fpga/Makefile:soc_tb.vcd [iverilog]: soc_tb.v drives UART+SOC for a fixed cycle count and dumps soc_tb.vcd for gtkwave - waveform-only (no assertions/$display PASS-FAIL, just $dumpvars + $finish)
xtrinch__fpga-bitcoin-miner	dirs: ./testbenches;1 tb/test files;tools: iverilog	Makefile:test-miner (iverilog): testbenches/test_fpgaminer_top.v - not self-checking (prints found nonce via $display, no PASS/FAIL assert, compare manually to genesis_block.txt); Makefile:test-uart (iverilog): testbenches/test_uart_comm.v - self-checking ($display PASS/FAIL + $finish); Makefile:test-top (iverilog): testbenches/test_top.v - self-checking ($display PASS/FAIL + $finish)
yope__cpuv2	1 tb/test files
yosyshq__picorv32	dirs: ./tests;6 tb/test files;tools: verilator,iverilog	Makefile:test/test_vcd/test_wb/test_wb_vcd/test_ez/test_ez_vcd/test_sp/test_axi/test_synth (iverilog): testbench.v(+_wb/_ez/_synth)+picorv32.v+tests/*.S - self-checking (writes to a magic MMIO word, testbench checks resulting register/trap state); Makefile:test_verilator (verilator): testbench.v via verilated C++ - self-checking (same mechanism); picosoc/Makefile:hx8ksim/icebsim/hx8ksynsim/icebsynsim (iverilog): hx8kdemo_tb.v/icebreaker_tb.v + picosoc.v+firmware - self-checking (firmware prints/traps via simpleuart, tb watches for completion); picosoc/Makefile:spiflash_tb (iverilog): spiflash_tb.v - waveform/console only, no fatal check seen
zeldin__icegdrom	dirs: ./test	none found: test/GNUmakefile tests target builds Dreamcast GD-ROM disc test images (BENCHMARK.GI0, DMATEST.GI0, CDDATEST.GI0 via test/source/benchmark.c, dmatest.c, cddatest.c) meant to run on real Dreamcast hardware from an SD card - not an RTL simulation/testbench
zipcpu__dblclockfft	1 tb/test files;tools: verilator	bench/formal/Makefile:*/PASS (sby, formal): bimpy/longbimpy/fftstage_s2-s6/hwbfly_one-three/butterfly_ck1/ck2_r0 .sby proofs - self-checking (PASS/FAIL, +11 more targets); bench/cpp/Makefile (via top Makefile “bench-test”, g++): fft_tb.cpp/ifft_tb.cpp/butterfly_tb.cpp etc. compared against bench/cpp/fft_tb.m Octave golden vectors - self-checking; bench/rtl/Makefile: ifft_tb.v - not confirmed self-checking
zipcpu__icozip	dirs: ./sim;tools: verilator	none: top Makefile’s check-verilator only checks the verilator binary exists (not a test run); make sim builds sim/verilated/-main_tb via verilator but the executable is never invoked by make (run manually against a compiled firmware image); bench/formal/.sby formal proofs run via sby, not make
zipcpu__sdr	dirs: ./sim;tools: verilator	none: Makefile:check-verilator (top-level Makefile:68-79) only checks that the verilator binary is installed, it does not run a sim; sim/Makefile builds an interactive Verilator model of toplevel.v (main_tb.cpp) with no automated pass/fail check - README says it ‘isn’t very useful at present’ unless you add -d for a VCD trace
zipcpu__sdspi	5 tb/test files;tools: verilator,iverilog	bench/formal/Makefile: ~60 _prf/_prfa/_prfc/_cvr/_cvra targets (sby): formal proofs/cover for llsdspi/sdspi/spicmd/sdspitx/sdio/sdckgen/etc - self-checking (SymbiYosys PASS/FAIL); bench/verilog/Makefile test_ckgen/test_txframe (iverilog): tb_sdckgen.v/tb_txframe.v run then perl sim_run.pl+gen_report.pl - self-checking; bench/cpp/Makefile test (verilator, C++ tb_sdspi.cpp+sdspisim.cpp): drives sdcard.img - self-checking C++ testbench
zipotron__ulx3s_sdram8	tools: iverilog	none: ulx3s.mk sim: tb; ./tb (scanner only saw tb) references tb.v and test68.v, neither present in clone
zipotron__ziposoc	4 tb/test files;tools: iverilog	make sim / make cpu_sim (iverilog+vvp+gtkwave): ziposoc_tb.v, zipocpu_tb.v - waveform-only, $finish on addr==MEM_END, no PASS/FAIL/assert
zyedidia__riscinator	dirs: ./tests ./src/test
zyp__katsuo-pcie	dirs: ./tests;4 tb/test files

Functions and reusable blocks

Per repo: function tags, where the ULX3S build lives, the constraint file, reusable cores, tests, and notes.

abhinavputhran__ttysky-raycast-test

• Functions: video-vga, retro-arcade
• ULX3S build: none present in this clone: no .lpf/.pcf/.xdc and no board build script anywhere; src/top_bare.sv is a generic bare (non-tt_um) wrapper not wired to any board’s pins (LPF: none (no board-specific top/constraints in this clone))
• Reuse: src/{wall_tracer,row_renderer,recip,pov_ctrl,map,vga}.sv: DDA raycasting maze renderer + reciprocal unit + VGA timing, portable SV, no vendor primitives, board-agnostic (top_bare.sv exposes plain clk/reset/buttons/rgb).
• Tests: dirs: ./test;tools: cocotb
• Notes: Last commit 2026-05-01. README’s ‘Running on FPGA (ULX3S)’ section shows only a photo (fpga.PNG, not present in this clone) and no ULX3S build files exist anywhere in the repo (no lpf/pcf, no build script): claimed, not demonstrated in this clone.

acairncross__clash-ulx3s-examples

• Functions: hdl-language, video-dvi, examples, education, board-hw, constraints
• ULX3S build: root (Makefile, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/RAM.hs, src/DVI.hs, src/StackMachine.hs, src/UART.hs – reusable Clash building blocks
• Tests: none found
• Notes: Five separate top modules built as separate bitstreams (stackMachine, counter, ram, dvi, snake)

acairncross__euphrates

• Functions: uart, hdl-language, NEW:graph-algorithm
• ULX3S build: root ulx3s_v20.lpf; Verilog generated via cabal run clash -- Euphrates.Top --verilog (LPF: ulx3s_v20.lpf)
• Reuse: src/Euphrates/Core.hs (max-flow accelerator core), src/Euphrates/UART.hs
• Tests: dirs: ./test
• Notes: No Makefile/build script wires up nextpnr/ecppack in-repo; academic accelerator with minimal board glue (bin/Serial.hs host side).

adrmcintyre__vixen

• Functions: soc-cpu, video-dvi, examples, hdl-language
• ULX3S build: ulx3s/ (cells_bb.v, ulx3s.lpf) + root Makefile (LPF: ulx3s/ulx3s.lpf)
• Reuse: video/vga2dvid.v, video/tmds_encoder.v (DVI output core), lang/ (standalone custom-language compiler, C)
• Tests: dirs: ./lang/tests;tools: verilator,iverilog
• Notes: “My first FPGA 16-bit computer”; also ships lang/, a standalone custom programming-language compiler/interpreter in C, only loosely tied to the FPGA design.

advikbahadur__ulx3s-superresolution-cnn

• Functions: camera, video-input, sdram, ml-accelerator, uart
• ULX3S build: constraint/ulx3s_v20.lpf + Makefile (trellis_main_ghdl.mk); prebuilt ulx3s_85f_CSI.bit/.svf/.config at root (LPF: constraint/ulx3s_v20.lpf)
• Reuse: CNN/camera pipeline under src/ (no single reusable core stands out)
• Tests: none found
• Notes: Also bundles a cc65-compiled 6502 SBC firmware (unrelated retro subproject); log.txt suggests build issues; lots of copy-pasted Diamond .xcf flashing scripts.

agamez__whisperice

• Functions: radio-tx, dsp-sdr, dsp, uart
• ULX3S build: src/top.vhd, constraints/icebreaker.pcf, Makefile (build target) (LPF: iCEBreaker (iCE40UP5K SG48, not ULX3S; constraints/icebreaker.pcf sourced from icebreaker-fpga/icebreaker-examples per file header))
• Reuse: src/nco/nco.vhd: phase-accumulator NCO for the 4-FSK WSPR tone offsets, portable (no vendor primitives); src/wspr/{wspr_fec,wspr_interleave,wspr_message,wspr_symbols,wspr_modulator}.vhd: self-contained WSPR protocol codec (conv. FEC, sync-vector interleave, 162-symbol 4-FSK modulator), pure VHDL, portable; src/gps/*.vhd: NMEA RMC parser + 1PPS clock_calibration, portable.
• Tests: dirs: ./sim; 13 tb/test files
• Notes: Very active (last commit 2026-09-28, tag v0.9.0). 12 MHz iCEBreaker osc, TX gated on GPS/1PPS calibration. No submodules. README claims make sim passes 13/13 tb and make build produces build/top.bin; not independently re-run here (read-only review).

ahamidi87__simpleblinky

• Functions: examples, board-hw
• ULX3S build: root (Makefile, blinky.ys, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: blinky.v (trivial LED counter)
• Tests: none found
• Notes: Smallest possible template project; a prebuilt ulx3s.bit is committed.

alangarf__apple-one

• Functions: retro-computer, uart, video-vga, ps2, usb-host, multi-board, board-hw
• ULX3S build: boards/icepi_zero/yosys/ (Makefile, icepi-zero.lpf) is the only ECP5 target; also boards/upduino, ice40hx8k-b-evn, terasic_de0/de0cv, spartan3e_starterkit, tang_primer_25k (Gowin), blackice2, icoboard, tinyfpga_b2 (LPF: Multi-board (not ULX3S): iCE40HX8K-B-EVN, Upduino, Icepi Zero (ECP5 25F), Terasic DE0/DE0CV, Spartan-3E Starter Kit, Tang Primer 25K (Gowin), Blackice II, icoBoard, Olimex iCE40HX8K, TinyFPGA B2)
• Reuse: rtl/cpu/arlet/{cpu.v,ALU.v} (portable Arlet 6502 core), rtl/uart/{uart.v,async_tx_rx.v}, rtl/vga/{vga.v,vram.v,font_rom.v}, rtl/ps2keyboard/ps2keyboard.v - technology-independent, per-board glue isolated in rtl/boards//
• Tests: 3 tb/test files;tools: verilator,iverilog
• Notes: Verified Apache-2.0. Only boards/icepi_zero targets ECP5 (25F/CABGA256, open yosys+nextpnr-ecp5+ecppack, 50 MHz osc vs ULX3S 25 MHz). Upstream of lawrie/apple-one: that fork adds boards/{ulx3s,ulx4m,blackicemx} and drops icepi_zero/ice40updevboard/tang_primer_25k/terasic_de0cv present here

alberto-grl__1bitsdr

• Functions: dsp-sdr, radio-rx, dsp
• ULX3S build: not ULX3S; top.v, FPGASDR.lpf, FPGASDR.ldf (Lattice Diamond project, no Makefile) (LPF: custom 1bitSDR board (not ULX3S); FPGASDR.lpf)
• Reuse: CIC.v (parametrized Hogenauer CIC decimator, portable); NCO.v/NCOAdder.v (phase-accumulator NCO with sin/cos LUT, portable); Mixer.v (1-bit RF mixer); AMDemod.v (sqrt(I^2+Q^2) AM demodulator, portable)
• Tests: 3 tb/test files
• Notes: Last commit 2020-05-21. Upstream of jamesrosssharp__1_bit_am (already catalogued, ULX3S 85F port) and a sibling design idea to emard__flearadio. top.v uses OSCH (133MHz internal osc) and GSR MachXO2 primitives, must be swapped for ECP5. README.md is a stray unrelated Nios II "Hello World" template file, not a real project description (verified by reading it). No submodules.

alhusseingamal__r2sdf-fft

• Functions: dsp, NEW:fft
• ULX3S build: NOT ULX3S; rtl/top_level.v (top), fpga/LatticeiCE40HX8K.pcf, fpga/Makefile (also top-level Makefile for verilator sim) (LPF: iCE40 HX8K breakout, CT256 (fpga/LatticeiCE40HX8K.pcf); not ULX3S)
• Reuse: rtl/top_level.v + sdf_stage.v/sdf_stage_d1.v/sdf_stage_d2.v/sdf_stage_d4.v (parametric radix-2 DIF SDF pipeline, N up to 512 checked in as a prebuilt bitstream under fpga/512-point-bitstream/, W=16 F=14 Q1.14); rtl/butterfly.v, complex_adder.v/complex_subtractor.v/complex_multiplier.v, twiddle_rom.v, circular_buffer.v - plain Verilog, no vendor primitives seen, portable to ECP5
• Tests: dirs: ./tb;1 tb/test files;tools: cocotb,verilator,iverilog
• Notes: Last commit 2026-09-22 (git log). tb/tb_fft_top.v is self-checking against data/golden/expected_output.txt (prints SQNR, no hard assert - see make_tests). fpga/Makefile also defines a cocotb sim target (COCOTB_TEST_MODULES=testbench) but PYTHONPATH=tests/testbench.py is absent from this clone.

alpin3__ulx3s

• Functions: toolchain
• ULX3S build: root (Dockerfile) (LPF: n/a)
• Reuse: Dockerfile static builds, debianize.sh
• Tests: none found
• Notes: last 2020-10

amin005__skywave_sdr

• Functions: dsp-sdr, radio-rx, adc
• ULX3S build: not ULX3S; fpga/skywave_usb_hs_adc_top.v, fpga/usb_adc_hs.lpf, fpga/build_usb_hs_adc.sh (yosys+nextpnr-ecp5+ecppack script, no Makefile) (LPF: custom ECP5-25F board with AD9226 ADC + USB3300 ULPI PHY (not ULX3S); usb_adc_hs.lpf)
• Reuse: fpga/cic_decim.v: parametrized Hogenauer CIC decimator (WIDTH/STAGES/R), portable, self-checking testbench (tb_cic.v: PASS/FAIL on in-band vs out-of-band rejection); fpga/adc_capture.v: AD9226 12-bit offset-binary->signed16 IOB capture, portable; fpga/async_fifo.v+fifo_deep.v CDC/depth FIFOs; own ulpi_/usb_ modules implement a full ULPI USB-HS device stack from scratch
• Tests: 2 tb/test files
• Notes: Last commit 2026-07-17 (active). No transceiver/DDC/NCO yet: raw capture+decimate+USB streaming stage only; tuning and I/Q explicitly listed as future work in README. tb_adc_stream.v is also self-checking (errs counter, PASS/FAIL prints). No submodules.

andreaspirklbauer__oberon-extended

• Functions: os-software, education
• ULX3S build: NO ULX3S (software) (LPF: none)
• Reuse: OS image for emard__oberon
• Tests: none found
• Notes: very active 2026-09-25; software companion only

andrewcapon__spinaltemplatesbtulx3s

• Functions: examples, hdl-language, toolchain
• ULX3S build: root (Makefile, hardware.ys, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/main/scala (SpinalHDL template component)
• Tests: none found
• Notes: Template/starter project for a SpinalHDL dev workflow with VS Code, not a functional design beyond blinky-level.

angelojacobo__ulx3s_fpga_camera_streaming

• Functions: camera, video-input, board-hw, constraints, examples, education
• ULX3S build: whole repo is ULX3S-only: constraint/ulx3s_v20.lpf, OV7670_ULX3S.ice, icestudio_blocks/ (LPF: ulx3s_v20.lpf)
• Reuse: icestudio_blocks/ OV7670 capture + VGA-out blocks reusable in other Icestudio ULX3S projects
• Tests: none found
• Notes: single small student-style project (Icestudio visual blocks + generated Verilog), not a general-purpose library

angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670

• Functions: camera, video-input, board-hw, constraints, examples, education
• ULX3S build: whole repo is ULX3S-only: constraint/ulx3s_v20.lpf, ULX3S_SOBEL.ice, icestudio_blocks/ (LPF: ulx3s_v20.lpf)
• Reuse: icestudio_blocks/ Sobel-filter block reusable in other camera/DSP Icestudio ULX3S projects
• Tests: none found
• Notes: near-duplicate structure to the same author’s camera_streaming repo; small student-style demo

anmho__ulx3_bsv

• Functions: soc-cpu, uart, sdram, ml-accelerator, video-input
• ULX3S build: src/ulx3s_bsv.lpf; per-project Makefiles (e.g. projects/rv32i/Makefile) run apio init -b ulx3s-85f (LPF: src/ulx3s_bsv.lpf)
• Reuse: src/{Uart,PLL,Sdram,Mult18x18D,SimpleFloat}.bsv: reusable Bluespec peripheral wrappers around ECP5 primitives (pll_fastclk.v/mult18x18d.v/sdram.v in src/verilog/); projects/rv32i/Top.bsv: RV32I core in Bluespec; projects/nn_fc*/NnFc.bsv: fully-connected NN accelerator with ZFP (de)compression.
• Tests: dirs: ./projects/test
• Notes: Last commit 2024-03-25. tools/replacetoken rewrites bsc-generated Verilog inout tokens for yosys compatibility – bsc output is not directly yosys-synthesizable without this post-processing step.

antoinevg__cynthion-tutorials

• Functions: soc-cpu, usb-device, audio-i2s, ethernet, wishbone-bus, bus-fabric, led-matrix, uart, timer
• ULX3S build: examples/soc/top.py + Makefile (VexRiscv SoC, Rust firmware in examples/soc/firmware); examples/i2s/step-3.py, examples/rgmii/step-1.py, examples/uac/step-1.py, examples/wishbone/step-.py, examples/ws2812/step-.py; src/gateware/platform/cynthion.py + ecpix5.py + ecpix5_luna.py (LPF: Cynthion (src/gateware/platform/cynthion.py, unfinished/buggy) + ECPIX-5 45F/85F (src/gateware/platform/ecpix5.py, ecpix5_luna.py))
• Reuse: src/gateware/interface/{i2s.py,rgmii.py,ws2812.py} (portable Amaranth interface cores); src/gateware/soc/ (own small Wishbone SoC: sram.py, timer.py, uart.py, usb/*.py, cpu/{vexriscv.py,ic.py} + bundled VexRiscv Verilog, generate.py); src/gateware/bridge/{stream.py,wishbone.py} (host<->FPGA bridges).
• Tests: 1 tb/test files
• Notes: Verified from source. Last commit 2025-01-13. src/gateware/platform/cynthion.py I2SResource() has a live bug: references undefined clk_dir instead of its own clkdir parameter (NameError if hit) - unfinished/draft code. examples/soc bundles a full Rust firmware+PAC+HAL stack. No submodules.

antoinevg__hello-ethernet

• Functions: ethernet
• ULX3S build: gateware/top.py, gateware/car.py (Makefile make top) (LPF: amaranth_boards ULX3S_85F_Platform + custom rmii/mdio/phy GPIO resources (pins 9-13 on gpio conn 0))
• Reuse: gateware/car.py: EHXPLL Amaranth wrapper (computes EHXPLLL parameters from i_freq/o_freq), directly reusable on other ECP5 boards; gateware/top.py: RMII/MDIO pin-mapping pattern for wiring an LAN8720 breakout to ULX3S GPIO headers.
• Tests: none found
• Notes: Last commit 2023-02-19. Design depends on the external daqnet package (daqnet.ethernet.mac.MAC, daqnet.ethernet.ip.IPStack, daqnet.user.User), which is NOT vendored in this repo and not installed by the Makefile/README: the actual MAC/IP-stack functionality is an unresolved external dependency and not reviewable here. No tests.

antonblanchard__chiselwatt

• Functions: soc-cpu, jtag, board-hw, constraints
• ULX3S build: Makefile (ECP5_BOARD=ulx3s target), constraints/ecp5-ulx3s.lpf, openocd/ecp5-ulx3s.cfg (LPF: ecp5-ulx3s.lpf)
• Reuse: the Chisel POWER core itself is the reusable, board-agnostic IP
• Tests: dirs: ./tests ./src/test;1 tb/test files;tools: verilator
• Notes: unusual CC-BY-4.0 license for source code; needs a Docker-based OpenOCD/toolchain flow

apfaudio__eurorack-pmod

• Functions: audio-i2s, dsp, i2c, constraints
• ULX3S build: not ULX3S; gateware/boards/ecpix5/ (Makefile, pinmap.lpf, sysmgr.v); gateware/Makefile dispatches to gateware/mk/ecp5.mk (yosys/nextpnr-ecp5/ecppack) (LPF: ECPIX-5 (LambdaConcept, ECP5-5G); also Colorlight i5/i9 and Tiliqua r5 (ECP5); iCEBreaker/iCESugar/Pico-Ice (iCE40 UP5K); GateMate eval board (Cologne Chip, not Lattice))
• Reuse: gateware/drivers/ak4619.sv (AK4619 codec I2C config + I2S stream driver, portable SV); gateware/cores/{vca,vco,pitch_shift,digital_echo,filter,bitcrush,sampler,mirror}.sv (small DSP building blocks, portable); gateware/external/no2misc/rtl/{uart_tx.v,i2c_master.v} (no2fpga, fetched submodule, portable)
• Tests: dirs: ./gateware/sim;tools: cocotb,verilator
• Notes: Last commit 2026-01-29 (active; 239 GitHub stars per survey). Clock 100MHz per gateware/boards/ecpix5/pinmap.lpf. Hardware revisions R3.1-R3.5 selectable via HW_REV define. Submodule gateware/external/no2misc fetched; hardware/libs/AudioJacks NOT fetched (hardware KiCad lib, not gateware).

apfaudio__guh

• Functions: usb-host, dma
• ULX3S build: examples/keyboard_host.py, midi_host.py, msc_host.py (LUNA_PLATFORM=... pdm run python3 examples/<x>.py --upload); guh/platform/tiliqua.py is the bundled platform (Tiliqua primary; Cynthion via the external cynthion package’s platform) (LPF: Tiliqua R4/R5 (guh/platform/tiliqua.py, bundled) + Cynthion (via the external cynthion package’s CynthionPlatformRev1D4, per README))
• Reuse: guh/usbh/{sie.py,enumerator.py,descriptor.py,reset.py} (USBSIE token/SOF/transfer engine + USBHostEnumerator, portable Amaranth over LUNA’s UTMITranslator, no ECP5 primitives); guh/engines/{keyboard.py,midi.py,msc.py} (class-specific host engines: HID keyboard, MIDI, mass-storage); guh/periph/{dma.py,msc.py} (DMA + MSC peripheral cores, paired with rs/guh-dma and rs/guh-usb-msc Rust firmware - mention only).
• Tests: dirs: ./tests;6 tb/test files
• Notes: Verified from source. Last commit 2026-09-07 (clone @9aa0fd3511). Primary hardware target is Tiliqua (its own ECP5 SoM), with Cynthion documented as a secondary target (README build command, with a noted quirk: “On Cynthion for some reason I often get ‘bitstream provides data past the device’s SRAM array’”). No submodules. rs/guh-dma and rs/guh-usb-msc are host/firmware-side Rust crates, mention only.

aravindrajeshkanna__vernier-rv32

• Functions: soc-cpu, linux, wishbone-bus, sdram, uart, sdcard, video-dvi, gpio, timer, jtag, NEW:mmu
• ULX3S build: fpga/{ulx3s_top.v,ulx3s_sdram.v,sdram_clk_out.v,underclock_pll.v,video_out.v,video_pll.v}, fpga/constraints/{ulx3s.lpf,ulx3s_sdram.lpf,ulx3s_diag.lpf}, fpga/synth/synth_ecp5.sh (LPF: ULX3S (fpga/constraints/ulx3s.lpf, "every pin placed, no –lpf-allow-unconstrained" per fpga/README.md))
• Reuse: fpga/underclock_pll.v: EHXPLLL-based clock divider (5 MHz from 25 MHz), ECP5-specific; rtl/soc/* Wishbone SoC (CLINT/PLIC/UART/GPIO/SPI) largely portable Verilog, no vendor primitives outside the fpga/ board-wrapper files
• Tests: dirs: ./sim ./tests;65 tb/test files;tools: verilator,iverilog
• Notes: last commit 2026-09-28, very active. Exceptionally well-documented, hardware-verified: fpga/README.md logs SOC-TEST: PASS, Linux boot to userspace, full 32MB SDRAM retention test on real ULX3S/LFE5U-85F silicon; Fmax margin thin (23.18-25.92 MHz vs 25 MHz target, 4/6 seeds close); SD card (>32GB SDXC) and video scan-out on a monitor not yet proven on hardware.

arisotura__spi_flash

• Functions: flash-spi, sdram, uart, flash-emulator
• ULX3S build: root (spi_flash.ldf) (LPF: ulx3s_v20.lpf)
• Reuse: spi_flash/source/ SPI flash emulation
• Tests: none found
• Notes: USB-CDC not working; active 2025

asinghani__advent-of-hardcaml-2024

• Functions: uart, board-hw, education
• ULX3S build: fpga/src/{ulx3s.ml,ulx3s_top.ml,constraints.lpf}, fpga/bin/build.ml (LPF: fpga/src/constraints.lpf)
• Reuse: fpga/src/{uart.ml,loadable_pseudo_dual_port_ram.ml,structural_inst.ml}: reusable Hardcaml board-support primitives (UART, loadable BRAM) shared across the day01-22 designs
• Tests: dirs: ./fpga/test
• Notes: Last commit 2025-02-25. Listed in group C (multi-board) but this clone shows ULX3S as the only target - likely grouped with its 2025 sibling repo, which adds a second (Zynq) target.

asinghani__advent-of-hardcaml-2025

• Functions: uart, board-hw, education
• ULX3S build: infra/src/{ulx3s_top.ml,build_ulx3s.ml,constraints.lpf} (LPF: infra/src/constraints.lpf)
• Reuse: infra/src/{uart.ml,control_codes_protocol.ml,test_harness.ml}: shared UART/control-protocol/test-harness infra reused across the day0N solutions
• Tests: dirs: ./day07/test ./day06/test ./day01/test ./day02/test ./day12/test
• Notes: Last commit 2026-01-01 (active, ongoing Dec-2025/Jan-2026 challenge). No LICENSE file in this clone.

asinghani__pifive-cpu

• Functions: soc-cpu, uart, examples, hdl-language, hyperram, i2c
• ULX3S build: fpga/ulx3s/ (top_ulx3s.sv, constraints.lpf, Makefile) (LPF: fpga/ulx3s/constraints.lpf)
• Reuse: cpu/ core (Wishbone I/D busses), soc/ Migen SoC generator reusable for other boards, software/ blinky+servo+tone+temperature demo apps; soc/third_party/hyperram/hyper_xface.v + hyper_dword.v (HyperRAM DWORD interface, portable, CERN-OHL-1.2 claimed); soc/third_party/verilog-i2c/rtl/i2c_master.v + i2c_slave.v (I2C cores, portable, MIT)
• Tests: dirs: ./cpu/rtl/test ./cpu/tests ./software/tests ./scripts/tests ./soc/tb;11 tb/test files;tools: verilator,iverilog
• Notes: soc/ generator targets “any board” - ULX3S is just the packaged example target under fpga/ulx3s/. Submodules fetched 2026-09-27: soc/third_party/hyperram@70b4648 (no repo LICENSE, CERN-OHL-1.2 claimed in-file only), soc/third_party/verilog-i2c@b6ebb7d (MIT).

asinghani__ulx3s-vga-example

• Functions: examples, education, NEW:video-vga
• ULX3S build: root (top.sv, constraints.lpf, build.sh) (LPF: constraints.lpf)
• Reuse: top.sv (whole example: VGA-over-PMOD timing generator)
• Tests: none found
• Notes: Written for CMU 18-224 course; single-file minimal example, no SDRAM/etc.

assured__ct-key

• Functions: soc-cpu, crypto, sdram, oled-lcd, bus-fabric, wishbone-bus, spi, linux
• ULX3S build: ctkey_package/src/ctkey/targets/ctkey_ulx3s.py (LiteX BaseSoC for litex_boards.platforms.radiona_ulx3s) (LPF: litex_boards radiona_ulx3s platform, revision default “2.0” (ctkey_ulx3s.py _CRG/SoC args))
• Reuse: ctkey_package/src/ctkey/cores/aes.py + cores/aes/src/rtl/*.v (secworks AES, BSD-2-Clause, submodule fetched 2026-09-28): CSR-wrapped AES-128/256 core (Instance(“aes”,…) over an 8-bit addr/data CSR bus), directly reusable; ctkey_package/src/ctkey/cores/timer.py: small CSR timer core.
• Tests: tools: verilator,iverilog
• Notes: Last commit 2025-05-17. README says hardware target is ‘still in development … on what hardware to use’ between ULX3S and OrangeCrab, but ctkey_ulx3s.py is a real, complete LiteX target that does call self.aes = aes.aes(platform) (line 99): the AES-on-ULX3S claim is backed by working target code, not just prose. linux-on-litex-vexriscv (framework) is referenced but NOT fetched per submodules.tsv policy; secworks/aes IS fetched.

badgeteam__mch2022-firmware-ice40

• Functions: board-hw, soc-cpu, oled-lcd, education, retro-computer, examples
• ULX3S build: projects/Hello-World/ (Makefile, rtl/hello_world.v); projects/_common/data/mch2022-prod.pcf; shared build/project-rules.mk (no2build submodule, not fetched) (LPF: MCH2022 badge FPGA (iCE40 UP5K), proto4/prod PCB revisions (mch2022-proto4.pcf, mch2022-prod.pcf) (not ULX3S))
• Reuse: cores/lcd/rtl/lcd_phy.v (parallel LCD PHY, mostly protocol logic); cores/spi_slave/rtl/spi_dev_*.v (SPI-slave-to-Wishbone bridge, portable Verilog, used to receive bitstream/data from host MCU)
• Tests: dirs: ./projects/riscv_doom/sim ./projects/spi-to-rgb/sim ./projects/selftest/sim ./cores/spi_slave/sim;5 tb/test files
• Notes: Verified LICENSE statement + doc/LICENSE-*.txt. cores/no2ice40, no2misc, no2qpimem, no2memcache and build (no2build) submodules unfetched here; same no2fpga cores catalogued under smunaut__ice40-playground/cores/. 12 MHz osc vs ULX3S 25 MHz; UP5K-SG48 pin-specific PCFs, no ECP5 port

basman74__next186

• Functions: retro-computer, soc-cpu
• ULX3S build: NO ULX3S (LPF: none)
• Reuse: use emard copy
• Tests: none found
• Notes: archive only

basman74__oberon_sdram

• Functions: soc-cpu, retro-computer, sdram, ps2, spi, uart
• ULX3S build: NO ULX3S — targets FleaFPGA Ohm/2v4, not ULX3S; entire repo is one zip Oberon_SDRAM_Diamond_Project.zip containing FleaFPGA_2v4_top.v/.lpf/.ccl, Flea_Ohm_revision_A3.lpf/.ccl, Oberon_Ohm_SDRAM.ldf (Diamond project file) (LPF: FleaFPGA_2v4_top.lpf/.ccl, Flea_Ohm_revision_A3.lpf/.ccl (both not ULX3S))
• Reuse: Oberon_SDRAM/sdram.v (6305B) + cache_controller.v (10211B): the SDRAM controller/cache later reworked into emard__oberon’s hdl/sdram.v + hdl/cache_controller.v (see that repo’s fork_of note and the emard-oberon-sdram-cache core record); also RISC5.v (Project Oberon RISC5 CPU, Wirth), vqueue.v, dcm.v (Diamond-generated PLL/DCM IP wrapper, ECP5-specific, not portable source)
• Tests: none found
• Notes: last commit 2018-03-12 (dormant ~8y); entire content is a single zip archive (275 files listed, 4.68MB uncompressed) — a full Lattice Diamond project incl. synthesis/PAR logs and a committed .bit bitstream; no top-level README/LICENSE; confirmed upstream of emard__oberon

bhouvana__aegis-x86-processor

• Functions: soc-cpu, NEW:x86, bus-fabric
• ULX3S build: FPGA/flow/Makefile, FPGA/ulx3s.lpf (LPF: ULX3S (LFE5U-85F CABGA381))
• Reuse: RTL/fpga/{clk_rst.sv,bram_tdp.sv,host_bridge.sv,uart_rx.sv,uart_tx.sv}: ECP5 bring-up wrapper (EHXPLLL PLL, DP16KD/PDPW16KD BRAM, UART host load/run/readback protocol), fairly portable; RTL/core/* is the huge tightly-coupled OoO core, not a drop-in block
• Tests: dirs: ./Decoder/tests ./Differential-Testing/tests ./RTL/tb ./Verification ./Emulator/tests;206 tb/test files;tools: cocotb,verilator
• Notes: Last commit 2026-09-10. Massive WIP research project (76 documented generations). FPGA bring-up (GEN12) verified in cocotb sim (UART load/run/readback vs aegis_emu, 3/3 pass) and elaborates cleanly against real ECP5 primitives; bram_tdp alone synthesizes to 64 DP16KD. Full-core synth_ecp5 reported still very slow/incomplete as of 2026-08-31 report, no routed .bit yet – real target, not yet a working bitstream on hardware.

bit-hack__icesid

• Functions: audio-dac, synth-audio, usb-device
• ULX3S build: reDIP-SID/ (Makefile.mk, redip-sid.pcf) and icesugar/ (Makefile.mk, icesugar.pcf); top Makefile selects BOARD=reDIP-SID by default (LPF: reDIP-SID board + iCESugar board (not ULX3S, iCE40 UP5K))
• Reuse: icesid/.v (dac.v, sid.v, env.v, voice.v, filter.v, clip.v, pot.v, mult.v, output.v): technology-independent Verilog SID core, no SB_ primitives, portable to ECP5/ULX3S with a suitable DAC/I2S output
• Tests: none found
• Notes: Core icesid/*.v has no iCE40 primitives and is portable. Board wrappers (top.v, sysmgr_hfosc.v) use iCE40 HFOSC/PLL and need ECP5 replacement; clock is 24 MHz (reDIP-SID) or 12 MHz (icesugar) vs ULX3S 25 MHz. CMake+Verilator sim exists for the core.

bjonnh__ulx3s-synth

• Functions: audio-i2s, synth-audio, uart, board-hw, constraints
• ULX3S build: root (Makefile, top.v, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: i2s.v, MidiProcessor.v/MidiByteReader.v, hdl/sv/ecp5pll.sv
• Tests: none found
• Notes: No README content; small experimental/WIP project, python scripts generate lookup tables (sine.mem, MidiNoteNumberToSampleTicks.v)

blazra__tdr

• Functions: NEW:serdes-pcie-sata, dac
• ULX3S build: not ULX3S; gateware/versa_ecp5-litex/versa_ecp5.py (top SoC), tdr/serdes_ecp5.py (SERDES core), tdr/daq.py (sampler); no Makefile/.pcf, built via LiteX Builder (python versa_ecp5.py) (LPF: Lattice ECP5 Versa board (litex_boards.platforms.versa_ecp5) + custom TDR daughter PCB (boards/TDR/, KiCad, FT2232H USB link, DAC))
• Reuse: gateware/versa_ecp5-litex/tdr/serdes_ecp5.py – SerDesECP5PLL/SerDesECP5 DCUA wrapper copied from liteiclink and repurposed for pulse sampling (data_width=20, no PCS/8b10b used); daq.py – Wishbone/CSR sample-and-store RX FSM, small and reusable as a generic SERDES bit-capture buffer
• Tests: none found
• Notes: last commit 2020-08-01 (git log -1); 1-line README, unverified working status per serdes_survey.md; no submodules

bnossum__midgetv

• Functions: soc-cpu, education, constraints
• ULX3S build: work/hwtst/icebreaker/ (Makefile, icebreaker.pcf) and work/hwtst/max_upduino2/ (up5k.pcf); core: work/midgetv.v / work/code/m_midgetv_core.v (LPF: iCEBreaker v1.0 + UPduino v2 (not ULX3S, iCE40 UP5K); also iCEBlink40-HX1K board (iCE40 HX1K, not UP5K))
• Reuse: work/midgetv.v (single-file monolithic core generated by work/util/make_monolithic.c from work/code/.v), work/util/midgetv_bin2ebr.c (bin-to-EBR-init converter) - core logic is plain Verilog but memory (work/code/m_ram.v) uses SB_SPRAM256KA/SB_LUT4 directly (iCE40-only)
• Tests: tools: verilator
• Notes: Verified Apache-2.0. m_ram.v/m_ram_a16.v/m_ram_a17.v instantiate SB_SPRAM256KA and SB_LUT4 directly (not abstracted) - ECP5 port needs a DP16KD-based memory rewrite; ALU/decode has no SB_ primitives. work/cold_store/ holds abandoned experiments; RV32IMC compliance suite included.

bonfireprocessor__bonfire-basic-soc

• Functions: soc-cpu, sdram, uart, flash-spi, sdcard, esp32, adc
• ULX3S build: ulx3s/, sdram/ (LPF: ulx3s_v20.lpf)
• Reuse: sdram/SDRAM_Controller.vhd (Mike Field, ECP5), wbs_sdram_interface.vhd
• Tests: dirs: ./tb;3 tb/test files
• Notes: needs other bonfire FuseSoC cores

bonfireprocessor__bonfire-core

• Functions: soc-cpu, jtag, uart, debug-bridge, bus-fabric
• ULX3S build: fusesoc-cores/bonfire-core-soc.core (targets: ulx3s, ulx3s_jtagg, ulx3s_extended_jtagg), fpga/ulx3s/board.lpf, fpga/ulx3s/ulx3s_top.vhdl (LPF: ULX3S LFE5U-85F/CABGA381 (fpga/ulx3s/board.lpf))
• Reuse: rtl/uncore/uart: portable UART peripheral; debug module connects to the ECP5’s own internal JTAGG (see sibling bonfireprocessor__bonfire-ecp5-jtagg-led-demo for the standalone bridge); rtl/cache: configurable cache, MyHDL/VHDL, portable
• Tests: dirs: ./fusesoc-cores/tb ./tests ./docs/tests ./tb;32 tb/test files
• Notes: Last commit 2026-09-16. Real, measured ULX3S PnR results recorded in docs/timing/ (e.g. 3-stage pipeline 81.39 MHz Fmax, 3060 LUT4 on ECP5-85K/CABGA381, Yosys 0.67).

bonfireprocessor__bonfire-ecp5-jtagg-led-demo

• Functions: jtag, board-hw, hdl-language
• ULX3S build: fusesoc/bonfire-ecp5-jtagg-led-demo.core (target ulx3s), fusesoc/fpga/ulx3s/board.lpf, fusesoc/fpga/ulx3s/ulx3s_jtagg_led_top.vhdl (LPF: ULX3S LFE5U-85F-6BG381C; Ice Pi Zero LFE5U-25F-6MG256C)
• Reuse: fusesoc/vhdl/ecp5_jtagg_bridge.vhd: static VHDL wrapper directly instantiating the JTAGG primitive (jtagg_inst: JTAGG), ECP5-only; src/bonfire_ecp5_jtagg_led_demo/{led_demo.py,jtagg_interface.py}: portable board-agnostic MyHDL logic
• Tests: dirs: ./tests;3 tb/test files
• Notes: Last commit 2026-07-20. CI via .github/workflows/ci.yml. pytest tests genuinely self-checking (MyHDL behavioral sim asserts LED register matches expected shift pattern), not wired to a Makefile.

bornabiro__fpga_epaper

• Functions: eink, board-hw, constraints
• ULX3S build: epaper/ (epaperDriver.v, topModule.v, epaper.lpf — real ULX3S v2.0/v2.1 pinout despite a generic filename) (LPF: epaper/epaper.lpf (header comment: “ULX3S v2.0 and v2.1”))
• Reuse: epaperDriver.v e-paper drive-waveform generator
• Tests: none found
• Notes: README: “still under heavy development… use only for educational purposes”, can only refresh/clean the panel; LPF has no “ulx3s” in its filename (would be missed by a naive filename-only search) but its header/pinout confirm a real ULX3S v2.0/2.1 target

bqqbarbhg__blipv1

• Functions: board-hw, video-dvi, sdram, hdl-language
• ULX3S build: blip/rtl/ecp5/ + blip/rtl/dvi/ (nmigen_boards.ulx3s.ULX3S_85F_Platform referenced in code; no .lpf, board file comes from nmigen-boards package) (LPF: none (no .lpf; platform pins come from external nmigen_boards.ulx3s package, not vendored))
• Reuse: blip/rtl/sdram.py, blip/rtl/dvi/tmds.py, blip/rtl/pll.py, blip/rtl/ecp5/{pll,io}.py — reusable SDRAM ctrl + TMDS/DVI encoder + PLL wrapper modules
• Tests: dirs: ./blip/test
• Notes: Library/framework style repo (task-runner ‘blip check’ harness) rather than a flashable demo; ULX3S targeting is real (via nmigen-boards) but depends on an external, unvendored board-definition package.

brunolevy__learn-fpga

• Functions: video-dvi, sdram, soc-cpu, examples, education, hdl-language
• ULX3S build: Basic/ULX3S/{ULX3S_hdmi,ULX3S_SDRAM_hdmi}; FemtoRV/BOARDS/ulx3s.{lpf,mk}; FemtoRV/TUTORIALS/ULX3S.md; LiteX/boards/radiona_ulx3s_ex.py (LPF: ulx3s.lpf (FemtoRV, v20-style pins))
• Reuse: FemtoRV/RTL PLL+CONFIGS RISC-V SoC core; Basic/ULX3S HDMI+SDRAM demos as reference designs
• Tests: dirs: ./FemtoRV/SIM;tools: verilator,iverilog
• Notes: huge multi-tutorial monorepo (many boards incl ECP5 Evaluation Board, ICE40); ULX3S is one of several targets

brunolevy__tordboyau

• Functions: soc-cpu, board-hw, constraints
• ULX3S build: BOARDS/{ulx3s.lpf,run_ulx3s.sh}, PLL/pll_ulx3s.v (LPF: ulx3s.lpf)
• Reuse: pipelined RISC-V core + tinyraytracer demo firmware
• Tests: tools: verilator
• Notes: README’s primary instructions target a Xilinx Arty A35T (Vivado project included); ULX3S is the secondary open-toolchain path

businessmanraduc__doggo-v6

• Functions: soc-cpu, sdram, uart, bootloader
• ULX3S build: synth/Makefile (target ULX3S 85K), synth/ulx3s_v20.lpf (LPF: ULX3S 85K (synth/ulx3s_v20.lpf))
• Reuse: rtl/core/*: six-stage RV32IMC pipeline with Gshare predictor, portable SV, no vendor primitives – but license is all-rights-reserved so reuse is legally blocked; rtl/soc/periph/{uart.sv,clint.sv}
• Tests: dirs: ./tests;1 tb/test files;tools: verilator
• Notes: Last commit 2026-07-12. README’s own status: sim-complete/52-of-52 compliance tests pass, Yosys synth clean, but on-board bring-up explicitly NOT done yet (‘waiting on the board itself’) – real build files, unverified on hardware. .gitmodules declares current-ver/riscv-tests (path riscv-tests) but that submodule directory is absent from this clone, so run_compliance.sh (the real self-checking compliance harness, parses Result: hex vs sub-test PASS/FAIL) cannot run here.

c-elegans__single_sdr

• Functions: dsp-sdr, NEW:fft
• ULX3S build: NOT ULX3S; src/main/scala/singlesdr/Top.scala (SpinalHDL top, elaborates to Top.v), Makefile (Top.json/Top_out.config via yosys+nextpnr-ecp5) (LPF: unknown/generic ECP5-45F dev board (CABGA381, same package as ULX3S 45F, but no ULX3S pin constraints or board name found); not confirmed ULX3S)
• Reuse: src/main/scala/singlesdr/FFT.scala (fftmain BlackBox generated via -f 256 -1 -n 12 -x 0 -c 0 -m 18 -p 30 -u: 256-pt, 12-bit in, 18-bit multiply, 30-bit precision); rtl/mult18x18_{0,1,2,3}c.v (pipelined MULT18X18D wrappers, 0-3 cycle latency) - ECP5-specific, no porting needed on ECP5
• Tests: dirs: ./sim (contains only a Lattice MULT18X18D primitive simulation model, not a testbench)
• Notes: Last commit 2019-04-23 (git log). .gitmodules declares submodule dblclockfft (url git@github.com:C-Elegans/dblclockfft.git, a fork of ZipCPU/dblclockfft) at path dblclockfft; git submodule status shows it unfetched (“-709e8e6…”), and fft-core/ (fftmain.v, fftstage.v, qtrstage.v, laststage.v, bitreverse.v, convround.v, hwbfly.v) does not exist in this clone - the design cannot be elaborated as checked out.

c-elegans__ulx3s_sdram

• Functions: sdram, jtag, examples
• ULX3S build: repo root: ulx3s_top.v, ulx3s_v20.lpf, synth.sh (LPF: ulx3s_v20.lpf)
• Reuse: sdram_controller3.v + IS42S16160.v SDRAM driver/model, directly reusable in other ULX3S SDRAM projects
• Tests: 1 tb/test files;tools: iverilog
• Notes: Small, single-purpose repo (22 files); README documents comparative programming speeds (USB/FT231 vs JTAG/OpenOCD) which is generically useful ULX3S operational info

callummcduff-droid__cpu

• Functions: soc-cpu, education
• ULX3S build: fpga/fpga_top.sv, fpga/ulx3s.lpf (present but not invoked by the Makefile – no yosys/nextpnr/ecppack target exists) (LPF: fpga/ulx3s.lpf)
• Reuse: rtl/{alu,decoder,cu,pc,registers,data_mem,inst_mem,sign_ext,if_id,id_ex,ex_mem,mem_wb,forwarding_unit,hazard_unit,cpu_pipeline}.sv: complete 5-stage pipelined 16-bit CPU with hazard/forwarding units, portable SV, no vendor primitives, each module independently testable via its own tb.
• Tests: dirs: ./reference_model/tests ./tb;11 tb/test files;tools: verilator
• Notes: Last commit 2026-09-19 (newest repo in this batch). fpga/fpga_top.sv + fpga/ulx3s.lpf exist and are real, but the Makefile only ever calls $(VERILATOR) for simulation (alu/decoder/cu/pc/registers/data_mem/inst_mem/cpu_pipeline targets) plus a C assembler/regression flow; there is no yosys/nextpnr/ecppack target anywhere, so a ULX3S bitstream is not demonstrated as buildable in this clone.

cariboulabs__cariboulite

• Functions: dsp-sdr, radio-rx, radio-tx, spi
• ULX3S build: firmware/top.v, firmware/io.pcf, firmware/Makefile - not ULX3S, no ECP5 support (LPF: CaribouLite R2/R2.5 HAT for Raspberry Pi 40-pin boards (not RPi5: SMI interface removed; not ULX3S))
• Reuse: firmware/complex_fifo.v: parametrised dual-clock-domain (wr/rd) complex I+Q FIFO, portable, no vendor primitives; firmware/smi_ctrl.v + firmware/io_ctrl.v: RPi SMI-bus streaming bridge/control FSM, portable logic but timing tuned to RPi SMI; firmware/lvds_rx.v/lvds_tx.v: LVDS I/Q (de)serialiser using SB_IO #(IO_STANDARD=”SB_LVDS_INPUT”) differential and SB_LVCMOS primitives (top.v:242-342), iCE40-specific, needs porting (e.g. ECP5 DELAYG/IDDRX1F or true LVDS buffers) for reuse.
• Tests: dirs: ./software/libcariboulite/test; 1 tb/test files
• Notes: Very active (last commit 2025-07-24, 1335 stars per rf/dsp survey). All actual RF mixing/demodulation happens in the AT86RF215-class front-end chips, not the FPGA; the FPGA is a thin LVDS<->SMI bridge plus a small complex FIFO. Submodule software/libcariboulite/src/iir (berndporr/iir1) is a software IIR filter library used by the host driver, not gateware - correctly not fetched (absent from submodules.tsv).

carlosedp__chisel-fpga-pinfinder

• Functions: uart, debug-bridge, board-hw
• ULX3S build: constraints/ecp5-ulx3s.lpf, src/main/scala/Toplevel.scala (frequency=25000000 for ULX3S per README), Fusesoc-based build (pinfinder.core) (LPF: constraints/ecp5-ulx3s.lpf)
• Reuse: src/main/scala/Toplevel.scala PinFinder module - small, self-contained, portable Chisel pin-probing core (one instance per pin, drives a UART-style serial print); board-agnostic besides the constraints file and clock frequency
• Tests: dirs: ./src/test
• Notes: Last commit 2024-09-24. No submodules. Small utility tool, not a full SoC.

carlosedp__chiselv

• Functions: soc-cpu, jtag, board-hw, constraints
• ULX3S build: constraints/ecp5-ulx3s.lpf; chiselv/resources/pll_ulx3s.v; proginfo/ulx3s-template.txt; README FuseSoC target ‘ULX3S 85k version’ (LPF: ecp5-ulx3s.lpf)
• Reuse: chiselv/ RV32I Chisel core reusable across boards; pll_ulx3s.v ECP5 PLL wrapper
• Tests: dirs: ./chiselv/test ./gcc/test;tools: verilator
• Notes: FuseSoC-based flow (core file drives the build, no plain top-level Makefile)

carlraymond__ulx3s-container

• Functions: board-hw, esp32, led-matrix, oled-lcd, constraints
• ULX3S build: src/fpga-blinker/ (blinker.v + blinker.lpf + committed blinker_routed.config) (LPF: src/fpga-blinker/blinker.lpf)
• Reuse: none (only a trivial LED blinker so far)
• Tests: none found
• Notes: Ambitious documented project (ProjectIdea.md: 4x 800x320 nixie-tube LCD clock with WWVB receiver) but actual FPGA content is only a starter LED blinker; most of the repo is Docker/devcontainer/WSL2-USB plumbing, not gateware; explicitly a Claude-Code collaboration project per its own docs.

cbalint13__e-verest

• Functions: board-hw, soc-cpu, uart, flash-spi, jtag
• ULX3S build: utils/test-firmware/{Makefile, rtl/top.v, rtl/firmsoc.v, brd/everest.lpf} (LPF: e-VEREST v1.5 USB stick, own board (not ULX3S; hardware/everest_v1.5))
• Reuse: rtl/pll.v: EHXPLLL wrapper 32MHz->49.7778MHz, ECP5-native primitive, drop-in on other ECP5 boards; rtl/{picorv32.v,simpleuart.v}: portable RISC-V core + UART, no vendor primitives
• Tests: dirs: ./utils/test-firmware/sim;2 tb/test files;tools: iverilog
• Notes: Last commit 2023-04-12. Board specs (85k LUT, 1GB DDR3 x16, USB3 FT601 FIFO, FT2232H JTAG/UART) per README, but test-firmware in utils/ only exercises UART echo (README boot banner shows single “[e] Echo UART” action). 32MHz onboard osc (clkin_32mhz), not 25MHz. No submodules.

cgarryza__advent-of-camel-2025

• Functions: education, uart, NEW:advent-of-code
• ULX3S build: fpga/src/{ulx3s_top.ml,ulx3s.ml,constraints.lpf,build.ml} (build.ml drives yosys/nextpnr-ecp5/ecppack directly; fpga/Makefile itself only runs dune/OCaml) (LPF: constraints.lpf (revision unspecified))
• Reuse: fpga/src/uart.ml: Hardcaml UART implementation, portable (no vendor primitives seen); day-specific solvers are puzzle-only
• Tests: dirs: ./fpga/test
• Notes: last commit 2026-01-19. Single-board project (ULX3S only; despite appearing in the multi-board survey group, no second FPGA/board target found in this clone). Day12’s design "uses a large RAM configuration intended for simulation rather than synthesis" per README.

cheyao__icepi-zero

• Functions: video-dvi, uart, ps2, sdcard, sdram, usb-device, flash-spi, jtag, board-hw
• ULX3S build: gateware/ (top-level Makefile, icepi-zero.lpf) with per-example subdirs, e.g. gateware/dvi/ (Makefile, icepi-zero.lpf, sim/); versioned LPFs in gateware/v1.0-v1.4/ (LPF: Icepi Zero v1.0-v1.4, Raspberry Pi Zero form-factor ECP5-25F board (not ULX3S, but README states it “was inspired by the ulx3s”))
• Reuse: gateware/dvi/dvi_out.sv + hdl/ (SystemVerilog DVI/TMDS core, sim/ testbench); gateware/uart/uart.sv (+ uart_tx.sv/uart_rx.sv); gateware/ps2/ (PS/2 host); gateware/sdram/memtest (SDRAM training, needs new LPF); gateware/third-party/jtag, dvi_osd (vendored, check own licenses)
• Tests: dirs: ./gateware/dvi/sim;tools: verilator,iverilog
• Notes: Verified from source (gateware/Makefile, README, LICENSE files). OSHWA-certified (FR000026), actively developed. Per-version LPFs (v1.0-v1.4) show pin churn, match board rev before reuse. 50MHz oscillator (not ULX3S 25MHz), PLL constants need adjusting when porting.

cheyao__nes_ecp5

• Functions: retro-console, video-dvi, sdcard, esp32, flash-spi, usb-host, audio-dac, ulx4m
• ULX3S build: top.v, nes.v, ulx3s_v20.lpf (root) (LPF: ulx3s_v20.lpf, ulx4m_v002.lpf, icepi-zero.lpf)
• Reuse: mappers/ (MMC1-5, VRC, Namco, Sunsoft, JYCompany, Sachen), t65/ (6502-compatible core)
• Tests: none found
• Notes: multi-board (ULX3S/ULX4M/icepi-zero); most complete/feature-rich of the nes_ecp5 forks in this batch

cheyao__oberon

• Functions: retro-computer, linux, video-dvi, ps2, usb-host, sdcard, multi-board, toolchain
• ULX3S build: constraints/ulx3s_v20.lpf, ulx3s_v20_segpdi.lpf, ulx3s_v31.lpf + proj/lattice/ulx3s/ulx3s-v20/ and proj_pnru/lattice/ulx3s/ulx3s-v20/ (Makefiles); hdl/top/ulx3s_v20_top.v, ulx3s_v31_top.v (LPF: 6 .lpf files across constraints/ (ulx3s_v20, ulx3s_v20_segpdi, ulx3s_v31, plus non-ULX3S Flea_Ohm and FFM-LFE5U boards))
• Reuse: proj/lattice/{ulx3s,fleafpga-ohm,ffm}/ + scripts/{trellis,diamond}_main.mk dual-toolchain build-glue pattern reusable across many Lattice boards
• Tests: tools: verilator
• Notes: Multi-board repo (ULX3S is the historical origin per README credit to emard/oberon, but actively targets Icepi Zero and other boards too); dual open+Diamond toolchain support is notable and reusable

cheyao__sega-sms

• Functions: retro-console, video-dvi, sdcard, esp32, usb-host, audio-dac
• ULX3S build: NO ULX3S (LPF: icepi-zero/icepi-zero.lpf (not ULX3S))
• Reuse: src/Z80/ (tv80 Z80 core), src/sn76489.v (PSG), src/osd/
• Tests: tools: verilator
• Notes: survey evidence ‘fork, pushed 25 d after fork’ is misleading: repo has since drifted to target only icepi-zero; danodus__ulx3s_sms is the better copy for an actual ULX3S build of this SMS core

chipdesign-bv__cdriscv-32s-20

• Functions: soc-cpu, jtag, bootloader, crypto, NEW:functional-safety
• ULX3S build: fpga/ulx3s/ (firmware_smoke.hex, itcm_init.hex only; NO .lpf, NO top-level wrapper); make fpga-synth just checks resource fit (LPF: none (no .lpf in repo))
• Reuse: rtl/core/ (RV32 pipeline+CSR+decompress), rtl/boot/cdriscv_32s_20_qspi_boot.sv (QSPI flash loader), rtl/bus/ (APB bridge, TCM)
• Tests: dirs: ./verif ./tb;34 tb/test files;tools: verilator,iverilog
• Notes: primarily an ASIC (IHP SG13G2) safety CPU; ULX3S support is docs+synth-fit only (nextpnr-ecp5 ‘not installed’), no real bitstream yet

chipflow__example-socs

• Functions: soc-cpu, board-hw
• ULX3S build: my_design/steps/board.py (ULX3S_85F_Platform from the amaranth_boards pip package, not vendored in this clone); Makefile targets board-build/board-load-ulx3s/board-load-software-ulx3s (LPF: unknown (constraint file is inside the external amaranth_boards pip package, not in this clone))
• Reuse: my_design/design.py (MySoC) - small example Amaranth SoC; my_design/steps/board.py - pattern for wiring an Amaranth design to amaranth_boards’ ULX3S_85F_Platform, reusable for any Amaranth ULX3S project
• Tests: dirs: ./my_design/sim ./tests;3 tb/test files
• Notes: Last commit 2024-07-26. Real, working ULX3S build path (make board-build / make board-load-ulx3s), but board pin constraints live in the external amaranth_boards package, not vendored here.

chiplet__acorechip-ulx3s

• Functions: board-hw, soc-cpu, jtag, constraints, bus-fabric
• ULX3S build: rtl/ (top.v wraps ACoreChip.v + AsyncResetSyncBB.v) + constr/constr.lpf (LPF: constr/constr.lpf (+ constr/constr_original.lpf))
• Reuse: rtl/top.v (JTAG+blinky ULX3S wrapper around ACoreChip); ACoreChip/src/main/scala/acorechip/acorechip.scala (Chisel bus-generation top, needs sbt+Chisel to elaborate to Verilog) - core CPU (ACoreBase) and ProgMem/JTAG/amba submodules still unfetched, not usable standalone yet
• Tests: dirs: ./ACoreChip/src/test;tools: cocotb
• Notes: ACoreChip (Chisel SoC generator, GitLab a-core project) is now fetched, but its own nested submodules ACoreBase (actual RV32IM CPU core), ProgMem, JTAG, amba are still unfetched/empty, so the real core RTL remains not inspectable; ACoreChip.v is generated by build, not checked in. sw/riscv-c-tests submodule still unfetched. Submodules fetched 2026-09-27: ACoreChip@ee96327.

chiplet__ulx3s-blinky

• Functions: board-hw, examples, constraints
• ULX3S build: rtl/blinky.v + constr/blinky.lpf (LPF: constr/blinky.lpf (+ constr/ulx3s_v20.lpf reference copy))
• Reuse: none (trivial blinky)
• Tests: none found
• Notes: Extremely minimal: empty README, single blinky.v; likely the project-template basis chiplet__acorechip-ulx3s was built from given the identical Makefile structure.

chriscamacho__yazsof

• Functions: soc-cpu, retro-computer, video-dvi, uart, bootloader
• ULX3S build: root (Z80.v), video/, asm/ (LPF: ulx3s_v20.lpf)
• Reuse: tv80 core, video/ (vga2dvid, charrom, videoram), uart.v
• Tests: none found
• Notes: known reset bug

chrislikescisco__nes-fpga

• Functions: retro-console, education
• ULX3S build: none present in the clone (LPF: none in-repo (README-claimed ULX3S 85K / Colorlight i5))
• Reuse: rgb_converter.sv: small fully portable combinational 6-bit NES-color to 24-bit-RGB LUT, no vendor primitives; ppu.sv is only a register-file/startup-timing skeleton, author’s own comment admits I/O functionality is unmodified/incomplete
• Tests: 1 tb/test files
• Notes: Last commit 2026-04-14. University of Florida course project. README repeatedly claims ULX3S 85K + Colorlight i5 targets (‘Flash the FPGA using ULX3S USB-Blaster’) but there is no top module, .lpf/.pcf, or Makefile anywhere in the repo – ULX3S support is CLAIMED ONLY, not real. ppu_tb.sv IS a genuinely self-checking SV testbench (assert/$error on register-reset values and an exact startup-wait cycle count) despite the missing board integration.

chrismoos__m6502

• Functions: soc-cpu, uart, examples
• ULX3S build: targets/ulx3s (LPF: ulx3s_v20.lpf)
• Reuse: rtl/cpu_6502*.sv (passes Klaus Dormann test), uart/timer/gpio/sk6812
• Tests: dirs: ./test;10 tb/test files;tools: cocotb,verilator
• Notes: 2026; ULX3S is demo target only

circuit-killer__fpga-usbhid-host

• Functions: usb-host, board-hw, constraints, oled-lcd
• ULX3S build: proj/{ulx3s-saitek,ulx3s-dragonrise-oled}/ (+ulx3s.lpf,project.ldf); proj/lattice/ulx3s/ulx3s-v20-85f-{saitek-joy,logitech-mouse,dragonrise-joy}/; proj/lattice/constraints/ulx3s_v20.lpf (LPF: ulx3s.lpf / ulx3s_v20.lpf / ulx3s_v17patch.lpf (multiple revisions across variants))
• Reuse: usbhid_host.vhd + usb_req_gen_func_pack.vhd (CRC5/CRC16 helpers) are a directly reusable minimal USB-HID host core
• Tests: none found
• Notes: not proper USB enumeration (replays constant packets); ulx3s-dragonrise-oled variant adds an OLED; many near-duplicate project dirs (also targets fleafpga_ohm)

circuit-killer__fpga-usbserial

• Functions: usb-device, uart, programmer-tool, multi-board
• ULX3S build: proj/lattice/ulx3s/ (ulx3s_v20_12f_serial, ulx3s_v17p_45f_serial, ulx3s_v20_85f_serial) + lattice/ulx3s/top/ulx3s_usbserial.vhd (LPF: ulx3s_v20_se.lpf, ulx3s_v20_dif.lpf, ulx3s_v17patch.lpf, ulx3s_v20_segpdi.lpf)
• Reuse: usb_serial/usb_serial.vhd (core state machine), usb11_phy_vhdl/ (USB1.1 PHY), ulpi_wrapper/ulpi_wrapper.v
• Tests: none found
• Notes: targets multiple boards/vendors (also Xilinx ffm-a7100); openocd .ocd configs included for JTAG programming

ckdur__riscvconsole

• Functions: soc-cpu, linux, video-dvi
• ULX3S build: fpga/ULX3S/{Makefile,README.md,scripts/{ulx3s_v20.lpf,yosys.tcl}} - the SoC RTL itself is generated by the hardware/chipyard submodule (Chisel), not present in this clone (LPF: fpga/ULX3S/scripts/ulx3s_v20.lpf)
• Reuse: fpga/ULX3S/scripts/{ulx3s_v20.lpf,yosys.tcl}: board constraint + synthesis script; the actual SoC RTL is chipyard-generated (submodule hardware/chipyard, not fetched) and absent from this clone
• Tests: tools: verilator
• Notes: Last commit 2026-09-25. Per brief, cataloguing the ULX3S-relevant part only. Submodules hardware/chipyard, hardware/fpga-shells, software/RISCVConsoleCode, software/riscv-isa-sim, software/riscv-tests are NOT fetched: the SoC Chisel source and most software are absent; only fpga/ build scripts and top-level docs are present.

cliffordwolf__icotools

• Functions: soc-cpu, gpio, uart, spi, retro-arcade, examples, programmer-tool, jtag
• ULX3S build: examples/blinky/{example.v,icoboard.pcf,Makefile}; examples/icezero/{icezero.v,icezero.pcf,Makefile}; icosoc/icosoc.py generates per-example icosoc.mk+pcf from icosoc.cfg (board icoboard); no ULX3S support (LPF: IcoBoard (iCE40 HX8K CT256 + Raspberry Pi header, not ULX3S))
• Reuse: icosoc/common/picorv32.v: vendored PicoRV32 RISC-V core (portable, no iCE40 primitives); icosoc/mod_{gpio,rs232,pwm,spi,ledpanel,extirq}/: small bus peripherals wired via icosoc.py board-pin tables, reusable once re-targeted; examples/icezero relies on yosys synth_ice40 default SB_IO/SB_RAM mapping
• Tests: tools: iverilog
• Notes: Last commit 2019-11-10; icosoc/examples/{hanoi,scales,sdcard,iconoid,ledpanel,memtest,timer,ioshim} demonstrate the SoC on real peripherals; icetime run at 20-25MHz depending on example; no submodules

cronokirby__ck-snes

• Functions: uart, examples
• ULX3S build: platform/ulx3s/ (Top.vhd, ulx3s_v20_min.lpf) (LPF: ulx3s_v20_min.lpf)
• Reuse: hdl/src/Uart.vhd
• Tests: dirs: ./hdl/test;1 tb/test files;tools: cocotb
• Notes: WIP (“I’m trying to write an SNES emulator”); Rust asm/tools are an assembler/toolchain, not SNES CPU/PPU cores yet.

cube1us__ibm1410fpga

• Functions: retro-computer, ethernet, uart
• ULX3S build: no ULX3S/ECP5 build; no board/constraint file (LPF/XDC/UCF) found anywhere in the clone; IntegrationTest_fpga.vhdl top-level testbenches instantiate library UNISIM (Xilinx), and VHDL/udp/EthernetVerilogTest.xpr is a Xilinx Vivado project (LPF: Unspecified Xilinx dev board, not ULX3S (IntegrationTest5_fpga.vhdl ports: CLK, SW(15:0), LED(15:0), RGB1_Red/Green/Blue, RGB2_ match a Digilent Nexys/Basys-style board, but no XDC to confirm))
• Reuse: VHDL/ALD_*.vhdl: hundreds of small, individually-testbenched gate-level primitives (flip-flops, gates, decoders) faithfully modelling IBM SMS cards; portable logic but extremely fine-grained, not a drop-in reusable block; VHDL/udp/udp_fpga_core.v: UDP/Ethernet test core, Xilinx-oriented, unverified portability
• Tests: 8 tb/test files
• Notes: Last commit 2026-08-21 (active). scan_tests.sh only finds 8 tb/test files because it matches *_tb.v(hd) not *_tb.vhdl; the repo actually has 438 *_tb.vhdl testbenches (verified by find), one per ALD module - record here since the field is a fixed heuristic. dbModel/IBM1410SMSModel.mwb is a MySQL Workbench model, not gateware. No submodules.

daglem__redip-sid

• Functions: audio-dac, synth-audio, audio-i2s, usb-device
• ULX3S build: gateware/ (Makefile, redip_sid.pcf, redip_sid.sv top) (LPF: reDIP SID board (DIP-28, iCE40UP5K-SG48I) (not ULX3S))
• Reuse: sid_voice.sv, sid_waveform.sv, sid_envelope.sv, sid_filter.sv, sid_dac.sv, sid_api.sv (technology-independent SID DSP core, no SB_* primitives, portable to ECP5)
• Tests: tools: verilator
• Notes: Verified CERN-OHL-S-2.0. ice40_init.sv uses SB_WARMBOOT/SB_PLL40_2F_CORE (board bring-up only, iCE40-specific); core SID DSP files are primitive-free. 24 MHz sys_clk (pcf) vs ULX3S 25 MHz; flashed via dfu-util/no2fpga Nitro Bootloader, not ULX3S tooling

damdoy__ice40_ultraplus_examples

• Functions: board-hw, soc-cpu, flash-spi, dsp, spram
• ULX3S build: NO ULX3S (LPF: Lattice iCE40UP5K Breakout Board (not ULX3S, iCE40))
• Reuse: spi/spi_host and spi_hw/spi_host (SPI-slave-to-host bridge, portable Verilog); riscv/simple_riscv_cpu/simple_cpu/{alu,register_file} (Submodule fetched 2026-09-27: riscv/simple_riscv_cpu@bde76c9, portable rv32i pieces, GPL/LGPL)
• Tests: dirs: ./riscv/simple_riscv_cpu/simulation;tools: verilator
• Notes: 12MHz ext clock (PLL example shows 48MHz internal, per README). SB_SPRAM256KA/SB_PLL40/SB_MAC16 (spram/pll/dsp examples) are iCE40-only, need EBR/EHXPLLL/MULT18X18D rewrites for ECP5. No prebuilt bitstreams; riscv example marked WIP in its README

dan-rodrigues__icestation-32

• Functions: video-dvi, gpu, retro-arcade, soc-cpu, examples
• ULX3S build: hardware/ulx3s/ (ics32_top_ulx3s.v, ulx3s_v20.lpf, gamepad/PLL/HDMI helpers) (LPF: ulx3s_v20.lpf)
• Reuse: hardware/ tile/sprite VDP-like core; firmware/ CPU-independent game-engine API
• Tests: 1 tb/test files;tools: verilator
• Notes: primary target is iCE40 UP5K (iCEBreaker); ULX3S uses the onboard GPDI port for video output

dan-rodrigues__ics-adpcm

• Functions: audio-dac, board-hw, constraints
• ULX3S build: demo/{Makefile,ulx3s_v20.lpf} (LPF: ulx3s_v20.lpf)
• Reuse: the ADPCM decoder/mixer top-level module is the reusable IP, also sized for the low-resource iCE40 UP5K
• Tests: dirs: ./sim ./sim/test;tools: verilator
• Notes: small focused audio IP core with CI (verilator + symbiyosys formal tests); demo/ is just one integration target

dan-rodrigues__mobile-fpga-bluetooth-demo

• Functions: esp32, board-hw, constraints
• ULX3S build: rtl/ (Makefile, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: rtl/ SPI-from-ESP32 LED-state receiver is a minimal reusable ESP32<->FPGA link example
• Tests: none found
• Notes: FPGA logic is intentionally minimal (LED state machine only); most of the interesting work is ESP32 BLE + iOS app, outside HDL scope

dan-rodrigues__ulx3s-bluetooth-gamepad

• Functions: esp32, uart, board-hw, examples
• ULX3S build: repo root: bluetooth_pad_demo_top.v, esp32_spi_gamepad.v, ulx3s_v20.lpf, Makefile (LPF: ulx3s_v20.lpf)
• Reuse: esp32_spi_gamepad.v SPI-gamepad-state receiver module reusable in other ESP32+FPGA gamepad projects
• Tests: none found
• Notes: Prerequisites include full Espressif IDF4 toolchain for ESP32 side; flash_all.sh needs manual variable edits before use

dangerousprototypes__buspirateultrahdl

• Functions: spi, uart, adc, gpio, debug-bridge, NEW:logic-analyzer-buffer
• ULX3S build: hdl/Makefile, hdl/buspirate.v (top module top), hdl/buspirate.pcf / buspirate_development.pcf (LPF: Bus Pirate Ultra / NextGen (Dangerous Prototypes) (not ULX3S))
• Reuse: hdl/spimaster.v, hdl/sio.v (SPI master, header credits ‘for buspirate NextGen Ultra’), hdl/adc.v, hdl/pwm.v, hdl/fifo.v, hdl/registers.v - plain Verilog, portable; hdl/pll.v wraps SB_PLL40_CORE (iCE40-only, needs ECP5 PLL) and hdl/buspirate.v instantiates SB_IO x5 for tristate/registered IO (lines 499-539; also components/mcutest/buspirate.v:91) - iCE40-only.
• Tests: 7 tb/test files
• Notes: Last commit 2019-12-03 (git log), inactive since. components/ holds standalone sub-block testbenches (clkdivider, freqcnt, pwm, spi, uart) not wired into hdl/Makefile. No submodules.

danielh186__6502-tapeout

• Functions: cpu-retro, gpio
• ULX3S build: fpga-test/Makefile, fpga-test/top.v, fpga-test/ulx3s_v20.lpf (LPF: Radiona ULX3S (fpga-test/ulx3s_v20.lpf, 85F/CABGA381))
• Reuse: cpu.v: self-contained 6502-compatible core, legal opcodes only, deterministic per-opcode cycle counts, several pins (SO/SYNC/RDY/HALT/NMI/IRQ) removed to save die area – not fully 6502-compatible; cocotb-testbench/test_cpu.py: reusable opcode-level reference-model comparator (verify_attr/verify_memory)
• Tests: 1 tb/test files;tools: cocotb,verilator
• Notes: Last commit 2025-04-15. Submitted to the April-2025 SG13G2 tapeout (IHP-GmbH/TO_Apr2025); silicon result not recorded in this repo. FPGA RAM synthesized from flip-flops (only 4096B window fits, shrink-memory.sh strips the test binary). Uses gated clocks (README admits this is not FPGA best practice). fpga-test/Makefile also has a separate Verilator waveform-only ‘test’ target for top.v, distinct from the cocotb opcode-comparison harness.

danodus__ecp5_hdmi_audio_video

• Functions: video-dvi, audio-i2s, board-hw, multi-board
• ULX3S build: boards/ulx3s/ (Makefile, ulx3s_top.v, ulx3s_v316.lpf, hdmi_pll*.v) (LPF: Targets ULX3S directly (PCB v3.1.7, ulx3s_v316.lpf, 25 MHz, CABGA381 85F) AND IcePi Zero rev 1.2 (50 MHz) - this repo DOES build for ULX3S, unlike the rest of this batch)
• Reuse: rtl/*.v (hdmi.v, hdmi_tmds_channel.v, hdmi_serializer_ecp5.v, packet/info-frame modules) - portable HDMI TX stack, already wired up for ULX3S in boards/ulx3s/
• Tests: none found
• Notes: Verified via README+LICENSE+Makefiles; VIC 0/4/34 builds use –timing-allow-fail with a random seed; README HDMI-licensing note: dev/education use, HDMI Adopter license needed for commercial products

danodus__msx_fpga

• Functions: video-dvi, ps2, retro-computer
• ULX3S build: ulx3s/ (Makefile, pll.v, hdmi.v, ulx3s.lpf) (LPF: ulx3s.lpf)
• Reuse: src/Z80/tv80_core.v (T80 Z80 CPU core), src/video.v, src/keyboard.v (PS2 keyboard)
• Tests: none found
• Notes: ships copyrighted ROM images in roms/ (msx.mem = MSX BIOS, bomberman.mem = commercial game ROM) despite MIT code license

danodus__onramp-fpga

• Functions: soc-cpu, uart, video-dvi, ps2, sdcard, sdram, gpio
• ULX3S build: boards/ulx3s/{Makefile,top.v,pll.v,pll_video.v,ulx3s.lpf,bios.hex} (LPF: ulx3s.lpf (revision unspecified); boards/icepi-zero/icepi-zero.lpf)
• Reuse: rtl/{or32.v,sdram.v,cache_controller.v,soc.v,bram32bit.v,bram_true2p_2clk.v,timer.v,div.v}: board-agnostic 32-bit CPU/SoC RTL shared by both boards, no vendor primitives at this level (PLL wrappers are per-board)
• Tests: dirs: ./sim;tools: verilator
• Notes: last commit 2026-05-17, active. Both supported boards are ECP5 (no non-ECP5 target); SD card image built via scripts/mkimg.sh.

danodus__ulx3s_68k

• Functions: retro-computer, soc-cpu, ps2, uart, sdram, audio-dac, esp32
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s/ulx3s_v20.lpf)
• Reuse: src/fx68k.sv (68000-compatible core), src/jt89/ (AY-3-8910-like PSG), src/osd/
• Tests: none found
• Notes: identical git commit hash to lawrie__ulx3s_68k already in sources.tsv; this slug adds no independent history, lawrie’s is the canonical copy

danodus__ulx3s_sms

• Functions: retro-console, video-dvi, sdcard, esp32, audio-dac, ulx4m
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf); also ulx4m/ (ulx4m.mk, ulx4m_v002.lpf) (LPF: ulx3s/ulx3s_v20.lpf, ulx4m/ulx4m_v002.lpf)
• Reuse: src/Z80/tv80 core, src/sn76489.v, src/osd/ (SPI OSD)
• Tests: none found
• Notes: unlike cheyao__sega-sms (drifted to icepi-zero only), this ships working ulx3s/ AND ulx4m/ builds - best copy of this core; identical commit hash to lawrie__ulx3s_sms already cataloged

danodus__xgsoc

• Functions: soc-cpu, video-dvi, sdram, ps2, usb-host, sdcard, gpu, uart
• ULX3S build: rtl/ulx3s/ (ulx3s_v31.lpf, ulx3s_v31_top.sv, Makefile) (LPF: rtl/ulx3s/ulx3s_v31.lpf (v31 board revision; also icepi-zero.lpf for the 25k alt target))
• Reuse: external/graphite/rtl/graphite.sv + reciprocal.sv + div.sv (2D/3D graphics accelerator core, portable SystemVerilog, MIT); RISC-V firmware/toolchain (hello, test_video, test_usb, bench_coremark/bench_dhrystone benchmarks) all reusable
• Tests: dirs: ./rtl/sim;tools: verilator,iverilog
• Notes: Actively maintained (README dated with 2026 builds tested on macOS oss-cad-suite); targets ULX3S v3.1 specifically, not older board revisions. Submodules fetched 2026-09-27: external/graphite@a721810 (MIT, matches top-level license).

darklife__darkriscv

• Functions: soc-cpu, uart, board-hw, constraints
• ULX3S build: boards/ulx3s/ (Makefile, darksocv.lpf) (LPF: darksocv.lpf (custom, not stock ulx3s_v20.lpf))
• Reuse: rtl/darkriscv.v core + darkuart/darkram/darkbridge/darkpll are portable across many boards/
• Tests: dirs: ./sim;tools: verilator,iverilog
• Notes: multi-board repo (DE10-Nano, Colorlight, Xilinx, etc); ULX3S is a thin SoC wrapper only

datanoisetv__colorlight-i9-aes67

• Functions: ethernet, audio-i2s, soc-cpu, constraints
• ULX3S build: Makefile (constraints/colorlight_i9_v7.2.lpf, rtl/aes67_top_standalone.v top); litex/soc.py builds a VexRiscv LiteX SoC variant (LPF: Colorlight i9 v7.2 (LFE5U-45F-6BG381C) (not ULX3S))
• Reuse: rtl/ptp/ptp_top.v + ptp_clock.v + ptp_servo.v (hardware IEEE1588 PTP clock/servo/filter, portable Verilog), rtl/eth/eth_mac.v + rgmii_rx.v/rgmii_tx.v (RGMII Gigabit MAC), rtl/rtp/rtp_engine.v + jitter_buffer.v (RTP TX/RX + BRAM jitter buffer), rtl/pll_25_to_125.v uses ECP5 EHXPLLL (25->125MHz), needs porting
• Tests: dirs: ./sim;1 tb/test files;tools: verilator,iverilog
• Notes: Last commit 2026-04-06 (git log). Single-author project, no submodules (litex/soc.py is a script, not vendored LiteX). README documents RFC-cited PTP compliance in detail; ambitious feature set for a solo repo, worth checking maturity before reuse.

daveshah1__pmods

• Functions: oled-lcd, video-vga, examples
• ULX3S build: no ULX3S/ECP5 build; lcd_test/{Makefile,lcd_test.pcf} and lcd_test_icebreaker/{Makefile,icebreaker.pcf} (LPF: Generic iCE40 HX8K breakout-style board (lcd_test) and iCEBreaker (lcd_test_icebreaker, iCE40 UP5K), not ULX3S)
• Reuse: lcd_test/{video.v,lcd_pll.v}: small parallel-RGB LCD panel driver + PLL; lcd_pll.v instantiates SB_PLL40_CORE (icepll-generated, 100->19.2MHz), iCE40-only, needs porting to EHXPLLL for ECP5/ULX3S
• Tests: none found
• Notes: Last commit 2019-09-19 (stale, 6+ years). Most of the repo (csi/, dacpmod/, pmod_lcd35/) is PCB/schematic design files for PMOD daughterboards, not gateware; only lcd_test and lcd_test_icebreaker contain HDL. No submodules.

daveshah1__prjtrellis-dvi

• Functions: video-dvi, board-hw, constraints, programmer-tool
• ULX3S build: constraints/ulx3s_v20segpdi.lpf; scripts/{ulx3s_trellis.mk,ulx3s_diamond.mk,project.ldf,ulx3s_sram.xcf,ulx3s_flash*.xcf} (LPF: ulx3s_v20_segpdi.lpf)
• Reuse: DVI/TMDS serializer core (fake-differential DDR/SDR) reusable on any ECP5 board
• Tests: none found
• Notes: 2019-era proof-of-concept for early prjtrellis; README says it needs a ‘specific branch of yosys’ (likely stale/unbuildable with current toolchains)

daveshah1__ulx3s

• Functions: soc-cpu, linux, sdram, uart, jtag, bootloader
• ULX3S build: ulx3s.core (FuseSoC CAPI2 file, target ‘synth’: default_tool trellis, nextpnr_options –45k) + rtl/verilog/orpsoc_top.v (LPF: NO LPF FILE IN THIS SHALLOW CLONE (constraints likely supplied by an external FuseSoC-managed board dependency, not vendored here))
• Reuse: orpsoc_top.v top-level + wb_intercon.v Wishbone interconnect generator, reusable FuseSoC-style SoC skeleton
• Tests: 1 tb/test files
• Notes: No LPF/constraints file present in repo tree; utils/boot_linux.sh suggests OpenRISC Linux boot was a goal; toolchain build depends on FuseSoC resolving external core libraries not in this shallow clone

daveshah1__up5k-demos

• Functions: retro-computer, video-vga, audio-dac
• ULX3S build: nes/ (Makefile, up5k.pcf) is buildable; gameboy/ has no Makefile/pcf, only leftover Altera Quartus gb.qsf/gb.qpf from the unrelated original MiST DE core (LPF: UPduino (up5k.pcf custom pin names); not ULX3S)
• Reuse: nes/up_spram.v (UP5K SPRAM wrapper, pattern only, not ECP5), nes/sigma_delta_dac.v (simple sigma-delta DAC, plain Verilog, portable)
• Tests: none found
• Notes: nes/ builds with open arachne-pnr toolchain, targets UP5K only, uses SB_SPRAM via up_spram.v (no ECP5 equivalent); gameboy/ is unbuildable source dump; porting needs BRAM instead of SPRAM and VGA pin remap

detegr__ulx3s-projects

• Functions: video-dvi, board-hw, constraints, examples
• ULX3S build: box/ (top.v, ulx3s_v20.lpf, Makefile: yosys synth_ecp5 + nextpnr-ecp5 –25k + ecppack) (LPF: box/ulx3s_v20.lpf)
• Reuse: digital_video/*.v (datachannel.v, video_sync.v, tsdm.v) — video-signal building blocks
• Tests: tools: iverilog
• Notes: no README at all; tiny personal-experiment repo; digital_video/ subfolder has no LPF/Makefile of its own (source-only, presumably meant to be wired into box/top.v)

dfiantworks__interactive-sim

• Functions: examples, NEW:simulation-framework
• ULX3S build: NO ULX3S (ulx3s_demo/ is an Icarus Verilog simulation of a ULX3S board photo GUI panel; no .lpf, no yosys/nextpnr, no bitstream) (LPF: none)
• Reuse: sv/interactive_ctrl.sv / v/interactive_ctrl.v / vhdl/interactive_ctrl.vhdl (viewer-driven control component, reusable in any HDL sim)
• Tests: dirs: ./tests;3 tb/test files;tools: verilator,iverilog
• Notes: not real ULX3S gateware; the ‘ULX3S board’ is only a simulated GUI panel image via the companion fpga-isv viewer tool

dibyx__flux

• Functions: gpu, video-vga, dsp-sdr, NEW:shader-core
• ULX3S build: hw-tools/fpga/{Makefile,synth.ys,ulx3s.lpf,ulx3s_prog.cfg}; RTL in rtl/src/{gpu_top.sv,gpu_graphics_top.sv,shader_core/,video/,raster/} (LPF: ulx3s.lpf (revision unspecified))
• Reuse: rtl/src/shader_core/{instruction_decoder.sv,simd_alu.sv,register_file.sv,shader_core.sv}: self-contained SIMD shader core, no vendor primitives; rtl/src/video/{vga_timing_generator.sv,vga_controller.sv,framebuffer.sv}: portable VGA output stack
• Tests: dirs: ./rtl/test ./sw-toolchain/sim;2 tb/test files;tools: cocotb
• Notes: last commit 2026-02-09. README claims "100% Roadmap Complete" and "Ready for ASIC tape-out" but the OpenLane ASIC Makefile is a template needing external OPENLANE_DIR/PDK_ROOT, not run in this clone; the ULX3S build files (Makefile+synth.ys+lpf) are real.

dicethrow__amaram

• Functions: sdram, NEW:async-fifo
• ULX3S build: amaram/sdram_n_fifo_interface/interface_fifo_build/{build_top.sh,top.ys,top.lpf,top.debug.v} - generated single-fifo test build (LPF: ULX3S (auto-generated top.lpf, LEDs + esp32_spi pins; revision unspecified))
• Reuse: amaram/sdram_n_fifo_interface/{interface_fifo.py,interface_n_fifo.py,controller_refresh.py,controller_readwrite.py,model_sdram.py}: portable Amaranth SDRAM refresh/read-write/FIFO controllers + sim model; no vendor primitives (pure Amaranth, portable)
• Tests: none found
• Notes: last commit 2022-04-09, stale. README logs a hardware test: "On a ULX3S board: test failed: too slow. Achieved 57 MHz but require 143 MHz" - real ULX3S build exists but did not meet its own timing target on hardware.

dicethrow__amtest

• Functions: examples, education, usb-device, spi, gpio, logic-analyzer
• ULX3S build: tests1jan2022/*/**/build_top.sh + top.lpf (Amaranth-generated, e.g. tests1_jan2022/test_sdram_n_fifo_interface_IS42S16160G/test5…_build/top.lpf) (LPF: ULX3S 85K (esp32_spi pins in generated .lpf))
• Reuse: tests2_feb2022/test3_fast_fifo_ila_gui.py + amtest_build/build.py: on-FPGA logic-analyser-over-wifi pattern (ESP32 UART passthrough + MicroPython GUI client), reusable debug harness idea rather than a single core; test_formal_verification.py: formal (SymbiYosys-style) timer proofs in Amaranth
• Tests: 7 tb/test files
• Notes: Last commit 2022-03-11. Author’s own status note: ‘set up started 23feb2022. Not yet fully functional.’ A grab-bag of dated per-topic test scripts (tests1_jan2022/, tests2_feb2022/), several with prebuilt top.debug.v/top.lpf/top.tim artifacts checked in.

diegob94__ulx3s_blink

• Functions: board-hw, examples
• ULX3S build: repo root (blinky.v, blinky.ys, ulx3s_v20.lpf, Makefile) (LPF: ulx3s_v20.lpf)
• Reuse: blinky.v (trivial LED counter, template starting point)
• Tests: none found
• Notes: tiny single-file template, no further functionality

dlobato__cps1-musicbox

• Functions: soc-cpu, synth-audio, sdram, uart
• ULX3S build: gateware/rtl/ulx3s-misc/ + radiona_ulx3s.py (LiteX board target definition, no separate .lpf - LiteX generates constraints internally) (LPF: no standalone .lpf found (LiteX generates board constraints from radiona_ulx3s.py programmatically))
• Reuse: radiona_ulx3s.py LiteX board-support target and gateware/rtl/ulx3s-misc/ glue reusable for other LiteX-on-ULX3S SoCs; gateware/rtl/jt51/hdl/ (jotego YM2151 FM core, via gateware/jt51/jt51.py) and gateware/rtl/jt6295/hdl/ (jotego MSM6295 ADPCM core) are the actual CPS1 sound cores, reusable standalone
• Tests: tools: verilator,iverilog
• Notes: Emulates specific CPS1 (Street Fighter II-era arcade) sound chips playing .vgm/.vgz music files; needs VGM files (not ROMs) supplied by the user; LiteX BIOS boot log shown in README confirms it runs. Submodules fetched 2026-09-27: gateware/rtl/jt51@b6d90af, gateware/rtl/jt6295@44be9a8

dlobato__tfmicro-on-litex-vexriscv

• Functions: ml-accelerator, soc-cpu, sdram
• ULX3S build: no ULX3S-specific files in this clone; SoC is built externally via $(LITEX_DIR)/litex-boards/litex_boards/targets/ulx3s.py --device LFE5U-85F ... (README.md:4-9) - litex-boards is an external dependency, not vendored/fetched here (LPF: unknown (no .lpf in this clone; generated by the external litex-boards ulx3s.py target))
• Reuse: firmware/tfmicro/ - TensorFlow Lite Micro ported to a bare-metal LiteX/VexRiscv firmware image; board-agnostic C/C++ firmware, reusable on any LiteX SoC
• Tests: none found
• Notes: Last commit 2021-04-26. No RTL in this repo - the SoC itself comes entirely from the external litex-boards package (not fetched as a submodule); only the tfmicro firmware and sim.py are original to this repo.

dman2021__blink

• Functions: board-hw, examples
• ULX3S build: repo root (clk_blink.v, clk_blink.lpf, Makefile, prebuilt clk_blink.bit) (LPF: clk_blink.lpf)
• Reuse: clk_blink.v (clock-divider LED blink)
• Tests: none found
• Notes: no README; ships a prebuilt .bit; trivial single-file test

dman2021__fpga_count

• Functions: board-hw, examples
• ULX3S build: repo root (top.v, top.lpf); build commands documented in README only, no Makefile (LPF: top.lpf)
• Reuse: top.v (LED counter)
• Tests: none found
• Notes: no Makefile, just README shell commands; trivial single-file example

dman2021__uart_echo

• Functions: uart, examples
• ULX3S build: repo root (uart_echo.v, uart_tx.v, uart_rx.v, uart_echo.lpf, Makefile) (LPF: uart_echo.lpf)
• Reuse: uart_tx.v, uart_rx.v (small reusable UART tx/rx blocks)
• Tests: none found
• Notes: small clean 3-file UART example, no README beyond build commands

doctorwkt__ulx3s-blinky

• Functions: examples, education, uart, video-dvi
• ULX3S build: root, Echo/, TestPattern/ (LPF: ulx3s_v20.lpf)
• Reuse: rxuartlite/txuartlite, llhdmi.v, TMDS_encoder.v
• Tests: tools: verilator
• Notes: simulation-first; updated 2026

doctorwkt__verilog_tic-tac-toe

• Functions: retro-console, uart, video-dvi, education
• ULX3S build: root, HDMI/ (LPF: ulx3s_v20.lpf, HDMI/ulx3s_v20_segpdi.lpf)
• Reuse: HDMI/DVI_3x3.v, TMDS_encoder.v
• Tests: tools: verilator
• Notes: preferred copy; 2026

dok3r__ulx3s-build

• Functions: toolchain
• ULX3S build: root (LPF: n/a)
• Reuse: Diamond-in-docker pattern
• Tests: none found
• Notes: needs own Diamond license

dok3r__ulx3s-saxonsoc

• Functions: soc-cpu, linux, sdram, bootloader, toolchain
• ULX3S build: scripts/buildsmp.sh (LPF: SaxonSoc radiona/ulx3s BSP)
• Reuse: buildsmp.sh SMP recipe
• Tests: none found
• Notes: stale 2020; likely no longer builds

dpks2003__dice_crap_game

• Functions: logic-analyzer, examples
• ULX3S build: NO ULX3S (LPF: NO ULX3S (no .lpf file in repo at all))
• Reuse: none
• Tests: none found
• Notes: Broken/WIP: crap_top.v has invalid Verilog syntax (missing commas in port list ‘output reg [6:0] seg1,seg2;’ and in module instantiations), seven_seg_decoder.v is an empty file, and there is no LPF/constraints file anywhere — this would not synthesize as-is and has never been targeted at real ULX3S hardware despite living in dpks2003’s ULX3S-repo set.

dpks2003__my_ulx3s_repo

• Functions: board-hw, examples
• ULX3S build: BCD_to_7segment/ (bcd_to_7segment.v + ulx3s_v20.lpf) (LPF: BCD_to_7segment/ulx3s_v20.lpf)
• Reuse: none (single small module)
• Tests: none found
• Notes: Very small personal repo, one example only, no build script committed (just source + LPF); empty placeholder README file inside the example dir too.

dschaefer__fpga-template

• Functions: board-hw, examples, hdl-language
• ULX3S build: repo root (top.sv, ecp5pll.sv, ulx3s_v20.lpf, cmake/hdl.cmake) (LPF: ulx3s_v20.lpf)
• Reuse: cmake/hdl.cmake (hdl_bit/hdl_test CMake functions: reusable yosys/nextpnr/ecppack + verilator/gtest build rules), ecp5pll.sv (PLL wrapper)
• Tests: dirs: ./blinky/test
• Notes: template/scaffolding project, not a functional design beyond blinky

dschaefer__ulx3s-ghdl-adder

• Functions: board-hw, examples, hdl-language
• ULX3S build: repo root (adder.vhdl, adder_ulx3s.vhdl, ulx3s_v20.lpf, CMakeLists.txt) (LPF: ulx3s_v20.lpf)
• Reuse: cmake/ghdl.cmake (ghdl_ecp5/ghdl_test CMake functions: reusable GHDL-plugin yosys/nextpnr/ecppack + ghdl testbench build rules)
• Tests: none found
• Notes: small template project pairing GHDL yosys plugin with CMake; testbench run directly in ghdl

dstrbad__fpga-soc-ml-accelerator

• Functions: soc-cpu, linux, ml-accelerator, sdcard, uart
• ULX3S build: build_soc.py (litex_boards.targets.radiona_ulx3s BaseSoC), buildroot/board/ulx3s/, prebuilt/ulx3s.bit (LPF: n/a (litex_boards radiona_ulx3s platform definition, no in-repo LPF))
• Reuse: ml_accelerator_csr_only.py + dma_matmul_accel.py accelerator cores; build_soc.py SoC integration
• Tests: none found
• Notes: well-documented, actively maintained (pushed 2026-08-04); real verified ULX3S 85F Linux SoC with working Iris/digit-classifier demos

dstrbad__janestreet-advent-fpga

• Functions: ml-accelerator, dsp-sdr, uart, board-hw, constraints
• ULX3S build: synth/ulx3s/ (Makefile, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: rtl/inference_engine.v (generated), training/ (Python model training)
• Tests: dirs: ./test
• Notes: One-off Advent-of-Code contest entry; HDL is generated by OCaml/Hardcaml, not hand-written Verilog

dulatello08__litex-cpu-testing

• Functions: logic-analyzer, soc-cpu, uart
• ULX3S build: repo root (rtl/top.sv via ulx3s_v316.lpf) and scripts/gen_soc.py (LiteX SoC targeting ULX3S board support) (LPF: ulx3s_v316.lpf)
• Reuse: rtl/unified_memory.sv (custom memory controller), scripts/gen_litescope.py + scripts/interactive_control.py (LiteScope UARTBone host tooling)
• Tests: none found
• Notes: two distinct sub-projects in one repo (LiteScope debug design vs LiteX SoC); prebuilt litex_testing.bit/.json committed

dulatello08__neocore-fx

• Functions: soc-cpu, uart, bootloader
• ULX3S build: root (ulx3s-85f-min.lpf, Makefile) (LPF: ulx3s-85f-min.lpf)
• Reuse: rtl/neocorefx_core.sv (CPU pipeline stages), rtl/debug_uart_agent.sv (UART debug/monitor agent)
• Tests: dirs: ./tb;11 tb/test files;tools: iverilog
• Notes: Extensively documented (30 .md docs, filelists for many sim configs); active-development staged pipeline core.

dulatello08__neocorefx-dram

• Functions: sdram, uart
• ULX3S build: repo root (rtl/top_litedram_clean_25.v, ulx3s-85f-min.lpf, Makefile) (LPF: ulx3s-85f-min.lpf)
• Reuse: rtl/sdram_native_controller.v (direct x16 SDR SDRAM controller, CL=3), rtl/litedram_native_bridge_32to16.v, rtl/uart_diag_bist.v
• Tests: dirs: ./sim;5 tb/test files
• Notes: extremely fine-grained sweep of ~20 near-duplicate LiteDRAM .yml timing configs suggests active SDRAM bring-up debugging (WIP)

dulatello08__ulx3s-tests

• Functions: uart, board-hw
• ULX3S build: repo root (uart_helloworld.sv, ulx3s_85f.lpf / ulx3s_85f_min.lpf, Makefile) (LPF: ulx3s_85f.lpf, ulx3s_85f_min.lpf)
• Reuse: uart_helloworld.sv (minimal SV UART test top)
• Tests: none found
• Notes: ships prebuilt uart_helloworld.bit and JetBrains .idea project files; single-file bring-up test, precursor to litex-cpu-testing/neocorefx-dram

dylansebastianheredia__e155_tuner_project

• Functions: dsp, NEW:fft, audio-i2s, spi
• ULX3S build: no Makefile/top .v/.pcf in repo; fpga/fft_src_v2/{fft.sv,fft_master.sv} (current, per README) and older fpga/src/fft_top.sv; Lattice Radiant project not included (LPF: UPduino v3.1 (iCE40 UP5K SG48, README only) + STM32L432KC MCU (mcu/); no constraint file in repo (not ULX3S))
• Reuse: fpga/fft_src_v2/{fft.sv,fft_control.sv,fft_agu.sv,math.sv,memory.sv}: 512-pt radix-2 SDF FFT core (ping-pong dual_RAM + single reused butterfly across M=9 stages), 16-bit fixed twiddle ROM; portable SV, no vendor primitives seen; needs UP5K/Radiant project + pin constraints not included in repo
• Tests: dirs: ./fpga/sim;10 tb/test files
• Notes: Last commit 2025-12-08. No LICENSE file. No .pcf/.lpf/Radiant project files in this clone despite README claiming “Lattice Radiant on Upduino v3.1” - device/pinout unverified from repo alone. Two parallel FFT trees (fpga/src/ older, fpga/fft_src_v2/ current per README).

ecp5-pcie__ecp5-pcie

• Functions: NEW:serdes-pcie-sata, debug-bridge
• ULX3S build: not ULX3S; Gateware/ecp5_pcie/ecp5_phy_x1.py (top PHY), Tests/test_pcie_phy.py (build+capture script), Tests/pcie_adapter.py (board platform); no Makefile/.pcf, built via Amaranth python scripts (LPF: ECP5 Evaluation Board (ECP5-5G EVN, LFE5UM5G-85F) + custom PCIe-Adapter PCB (KiCad, PCIe-Adapter/); host tested: ROCKPro64 (README))
• Reuse: Gateware/ecp5_pcie/ecp5_serdes.py – LatticeECP5PCIeSERDES: Instance(‘DCUA’)+Instance(‘EXTREFB’) wrapper, 1:1/1:2 gearing (1:2 marked broken), based on Yumewatari; Gateware/ecp5_pcie/{ltssm,dll,dllp,tlp,crc,align}.py – PCIe LTSSM/DLL/TLP layers, HDL-agnostic once fed a lane; needs an ECP5 UM/UM5G part
• Tests: dirs: ./Tests;23 tb/test files
• Notes: last commit 2023-05-16 (git log -1); declares submodule Gateware/utils -> https://github.com/ECP5-PCIe/ECP5-Utils.git (.gitmodules) but git ls-files shows no gitlink for it at this commit, so Gateware/utils is ABSENT from the clone (a different, regular tracked dir Gateware/ecp5_pcie/utils/ exists and is unrelated); README: reaches L0 and captures DLLPs, no enumeration/TLP traffic shown

egorxe__openglory

• Functions: gpu, soc-cpu, video-dvi, board-hw
• ULX3S build: hw/litex/radiona_ulx3s.py, run/configs/synth/radiona_ulx3s.json (LPF: n/a (LiteX-generated pinout, no static .lpf checked in))
• Reuse: hw/ VHDL GPU pipeline (rasterizer/texturing) is vendor-independent and the main reusable core; LiteX platform file is a reusable ULX3S board-support template
• Tests: dirs: ./run/configs/sim ./hw/tb;tools: cocotb
• Notes: WIP/undocumented per README (‘most parts are not documented and may not work’); verified mainly on Xilinx Ultrascale+Vivado, ECP5/open path secondary

emard__apple-one

• Functions: retro-computer, video-dvi, ps2, uart
• ULX3S build: boards/ulx3s/yosys/, rtl/boards/ulx3s/ (LPF: ulx3s_v20.lpf)
• Reuse: rtl/boards/ulx3s/vga2dvid.v + tmds_encoder.v + fake_differential.v
• Tests: 3 tb/test files;tools: iverilog
• Notes: multi-board

emard__apple2fpga

• Functions: retro-computer, video-dvi, oled-lcd, usb-host, ps2, esp32, sdcard, audio-dac
• ULX3S build: proj/lattice/ulx3s/, rtl_emard/lattice/top/ulx3s_v20_apple2.vhd, ulx3s_v31_apple2.vhd (LPF: ulx3s_v20_difgpdi.lpf, ulx3s_v31.lpf)
• Reuse: rtl_emard/usb usbhost + usb11_phy_vhdl, rtl_emard/dvi vga2dvid/tmds_encoder, rtl_emard/osd spi_osd (ESP32 OSD), spi_display ST7789
• Tests: none found
• Notes: disks via ESP32 osd.py

emard__cortex

• Functions: retro-computer, sdram, uart, esp32, board-hw, constraints
• ULX3S build: root (ulx3s.lpf, make.sh) (LPF: ulx3s.lpf)
• Reuse: sdram.v, spi_ide.v, tms9902.v/tms99095.v (TMS9900-family CPU core)
• Tests: 1 tb/test files;tools: iverilog
• Notes: make.sh comment mismatch: says “assumes 25F device” while nextpnr flag is –12k, and ecppack –idcode override for 12F is commented out – device targeting is ambiguous/untested

emard__esp32ecp5

• Functions: esp32, jtag, programmer-tool, flash-spi, sdcard, bootloader
• ULX3S build: root (ecp5.py, uftpd.py…), circuitpython/, rbp/ (LPF: n/a)
• Reuse: ecp5.py, uftpd.py, sdraw.py
• Tests: none found
• Notes: standard ESP32 programmer shipped on ULX3S; rbp/ also Artix-7/Cyclone V

emard__fleafpga-jtag

• Functions: jtag, programmer-tool
• ULX3S build: n/a (host tool, no gateware); targets FleaFPGA boards, not ULX3S, over FTDI JTAG (FleaFPGA-JTAG-linux/hardware.c) (LPF: FleaFPGA (not ULX3S))
• Reuse: none recommended: proprietary-EULA’d Lattice ispVM derivative (.vme player), not a permissively-licensed reusable core
• Tests: none found
• Notes: last commit 2019-05-21 (git log); readme.md is a 1-line stub; real usage docs are in FleaFPGA-JTAG-linux/README.md

emard__flearadio

• Functions: dsp-sdr, adc, audio-dac, radio-rx
• ULX3S build: NO ULX3S (ulx2s XP2, fleafpga MachXO2) (LPF: ulx2s.lpf)
• Reuse: rtl/generic/FleaFPGA_FM_Radio.vhd (digital FM demod), simple_PWM.vhd
• Tests: none found
• Notes: no ECP5 port; port candidate

emard__fpga_snake_game

• Functions: video-dvi, video-vga, retro-arcade, examples
• ULX3S build: proj/lattice/ulx3s/{makefile.trellis,makefile.diamond}, top/ulx3s_snake.v (open flow, constraints/ulx3s_v20_segpdi.lpf); proj/lattice/snake_ulx3s_hdmi/{Makefile,snake_hdmi.ldf,top/snake_ulx3s.vhd} (Diamond flow, constraints/ulx3s_v17.lpf, ulx3s_v18.lpf) (LPF: ULX3S v17/v18/v20 (constraints/ulx3s_v17.lpf, ulx3s_v18.lpf, ulx3s_v20_segpdi.lpf); also FFM-A7100 (Artix7), Scarab miniSpartan6-plus, FFM-C5A4-SD-LCSE (Cyclone5) - not ULX3S)
• Reuse: dvi/vga2dvid.vhd+tmds_encoder.vhd+fake_differential.v: emard’s standard VGA->TMDS/DVI encoder, same files as the already-catalogued emard-vga2dvid-tmds core (emard__ulx3s-misc) - duplicate, not re-added; rtl_emard/vga/vga.vhd: VGA timing generator (vga-function alternative slots already full in cores.json); rtl_emard/spdif/spdif_tx.vhd: S/PDIF tx (audio-digital slots already full); snake_v.v/snake.vhd: the game logic itself, small but game-specific
• Tests: none found
• Notes: last commit 2019-05-06 (git log -1). 25 MHz board clock (clk_25mhz). Single repo covers ECP5/Xilinx/Altera boards; no submodules; no LICENSE file at repo root.

emard__galaksija

• Functions: retro-computer, video-dvi, ps2, uart, flash-spi, audio-dac
• ULX3S build: proj/lattice/ulx3s-universal-make/ (LPF: ulx3s_v20_segpdi.lpf)
• Reuse: tv80 Z80 core, rtl_emard/dvi, bram_true2p_2clk.v, ps2.v
• Tests: none found
• Notes: galaksija2024 variant; flash as EEPROM

emard__had2019-playground

• Functions: bootloader, usb-device, soc-cpu, flash-spi, esp32, board-hw, constraints

• ULX3S build: projects/bootloader/ (Makefile MODEL=ulx3s

  ulx4m, BOARD=ulx3s-v20

  v314

  v317, rtl/top-ulx3s.v, data/top-ulx3s-v20.lpf, top_passthru-ulx3s-.lpf, fw/usb_dfu.c) (LPF: ULX3S v2.0/v3.1.4/v3.1.7, ULX4M v0.0.2, HAD2019 badge (data/.lpf))

• Reuse: cores/usb/rtl/usb*.v: USB full-speed device core (EP buffers, CRC, transactions portable; soft PHY usb_phy.v uses ECP5 TRELLIS_IO/IDDRX1F/OFS1P3; LGPL-3.0); projects/bootloader/fw/usb_dfu.c + usb_desc_dfu.c: DFU class firmware; rtl/qspi_phy_ecp5.v (QSPI flash PHY: ECP5 USRMCLK, TRELLIS_IO, IFS1P3/OFS1P3); rtl/esp32_passthru.v; user bitstream at flash 0x200000 (USER_BITSTREAM_ADDR, must match dfu_zones[] in fw/usb_dfu.c)
• Tests: dirs: ./cores/misc/sim ./cores/usb/sim;7 tb/test files;tools: iverilog
• Notes: Last commit 2021-12-24. Source of the recommended ULX3S bootloader shipped as prebuilt images in emard__ulx3s-bin fpga/dfu/ and used by openFPGALoader -b ulx3s_dfu. ecppack –bootaddr 0x200000; multiboot.img = bootloader + passthru. Prebuilt fw_dfu.hex-0x180000/0x200000 in fw/. See docs/DFUs.md. No submodules.

emard__jupiter_ace

• Functions: retro-computer, video-dvi, ps2, audio-dac
• ULX3S build: ulx3s/, src/top/jupiter_ace_ulx3s.v (LPF: ulx3s_ace.lpf (from v20))
• Reuse: src/sys/dvi.v compact HDMI, src/sys/ps2.v
• Tests: none found
• Notes: small, complete, 2020

emard__ledstrip

• Functions: led-drivers, examples
• ULX3S build: none (no ULX3S top-level in this repo); rtl/lattice/ulx2s_toplevel.vhd + rtl/proj/lattice/ulx2s/{makefile,ulx2s.lpf} targets the older ULX2S board; rtl/lattice/FleaFPGA_2v5_toplevel.vhd targets FleaFPGA (LPF: ULX2S (rtl/proj/lattice/ulx2s/ulx2s.lpf) and FleaFPGA 2v5 - neither is ULX3S)
• Reuse: rtl/generic/ws2812b.vhd: small self-contained WS2812B bit-banging driver (clk_Hz/striplen/timing generics, built-in 8-colour ROM sequence), no vendor primitives, portable as-is to ECP5/ULX3S; added as a new led-drivers alternative core (emard-ws2812b-driver) since no WS2812-specific driver existed in cores.json yet (only HUB75/LED-matrix drivers)
• Tests: none found
• Notes: last commit 2016-02-10, oldest of the four group-E2 repos and predates the ULX3S (targets its ULX2S predecessor and FleaFPGA). 25 MHz default clk_Hz.

emard__libxsvf-esp

• Functions: jtag, esp32-osd
• ULX3S build: n/a (ESP32/ESP8266 firmware, no FPGA gateware); drives the target FPGA’s JTAG pins from the ESP32 side, e.g. examples/websvf/websvf.ino, examples/prog/prog.ino (LPF: n/a (ESP32/ESP8266 module + any JTAG target, not a specific board))
• Reuse: src/trunk/{svf.c,xsvf.c,tap.c,scan.c,play.c,libxsvf.h}: portable C (X)SVF/JTAG state-machine player (Clifford Wolf’s libxsvf core), MCU-agnostic; src/LibXSVF.cpp/h: Arduino SPIFFS-buffered wrapper calling xsvftool_esp_*()
• Tests: none found
• Notes: last commit 2018-11-28 (git log); examples/websvf(_sd) add a browser-based SVF upload UI; predates the ULX3S ESP32 OSD firmware but shows the same ESP32-drives-JTAG pattern

emard__minimig_ecs

• Functions: retro-computer, sdram, sdcard, video-dvi, audio-spdif, audio-dac, ps2, usb-host, soc-cpu
• ULX3S build: proj/lattice/ulx3s/universal_make_ps2kbd, _usbjoy (LPF: ulx3s_v20.lpf)
• Reuse: rtl_emard/generic/sdram.vhd, rtl_emard/spdif/spdif_tx.vhd, rtl_emard/usb, vgahdmi
• Tests: none found
• Notes: unzip script needed first; OSD = 4 directions

emard__nes_ecp5

• Functions: retro-console, video-dvi, sdram, flash-spi, sdcard, esp32, usb-host, audio-dac
• ULX3S build: root (top.v), esp32/, osd/, usb/ (LPF: ulx3s_v20.lpf)
• Reuse: usb/usbhost Verilog USB HID host + report decoders, osd/spi_osd.v, sdram.v, ecp5pll.sv
• Tests: none found
• Notes: needs ESP32 osd.py

emard__next186

• Functions: retro-computer, soc-cpu, sdram, sdcard, video-dvi, audio-dac, ps2, usb-host, esp32
• ULX3S build: proj/ulx3s/, emard/top/ulx3s_next186.v (LPF: ulx3s_v20_difgpdi.lpf)
• Reuse: emard/dvi, ddr_186.v SDRAM adaptation
• Tests: none found
• Notes: requires 85F + zip extraction

emard__oberon

• Functions: soc-cpu, retro-computer, sdram, sdcard, video-dvi, ps2, esp32, uart
• ULX3S build: proj/lattice/ulx3s/ulx3s-v20/, esp32ps2/, proj_pnru/ (LPF: ulx3s_v20.lpf, ulx3s_v31.lpf)
• Reuse: hdl/sdram.v + cache_controller.v, hdl/lattice/ecp5pll.sv, RISC5 CPU
• Tests: none found
• Notes: RISC.img at sector 524288; PS/2 via ESP32 from PC

emard__papilio-arcade

• Functions: retro-arcade, video-dvi, audio-dac, audio-spdif, usb-host, ps2
• ULX3S build: pacman_rel004_sp3e_papilio/proj/lattice/ulx3s/, scramble_rel001_papilio/proj/lattice/ulx3s/ (LPF: ulx3s_v20.lpf)
• Reuse: scramble source/: vga2dvid, av_hdmi (HDMI audio), osd, usbhid Saitek, spdif_tx, T80
• Tests: 3 tb/test files
• Notes: 2018; ROMs in-tree

emard__prjtrellis-picorv32

• Functions: soc-cpu, uart, bootloader
• ULX3S build: top.v, attosoc.v, pll.v, simpleuart.v, picorv32.v, makefile (TOP_MODULE=top), scripts/ulx3s_trellis.mk / scripts/ulx3s_diamond.mk, ulx3s_v20_segpdi.lpf (LPF: ULX3S (ulx3s_v20_segpdi.lpf))
• Reuse: picorv32.v/attosoc.v: exact copies of yosyshq/picorv32’s core+demo SoC, already the collection’s best cpu-riscv core (yosyshq-picorv32, yosyshq__picorv32) - duplicate, not re-added; firmware.c: small (<1KB) FPGArduino-compatible HEX bootloader ported from f32c, niche/dated (2019, HEX-only, needs Arduino IDE + FPGArduino board package)
• Tests: none found
• Notes: last commit 2019-01-18. 25 MHz clock, 115200 baud UART bootloader (32K BRAM by default). pll.v hardcodes a fixed 12/50 MHz EHXPLLL (not parametric, lower quality than the collection’s existing ecp5pll core, so not added as an alternative). No submodules; picorv32 vendored directly as files.

emard__rdsfpga

• Functions: radio-tx, dsp-sdr, synth-audio
• ULX3S build: NO ULX3S (ULX2S XP2 + Altera EP4CE6) (LPF: ulx2s.lpf)
• Reuse: rds.vhd (RDS DBPSK), fmgen.vhd (FM gen), genmsg/
• Tests: none found
• Notes: ULX3S port lives in ulx3s-misc

emard__snes_mister_ulx3s

• Functions: video-dvi, sdcard, flash-spi, retro-console, board-hw, esp32, uart
• ULX3S build: ulx3s/ (adds esp32/, osd/, btn_ecp5pll_phase.v vs gatecat’s version) (LPF: ulx3s/top/ulx3s_v20.lpf)
• Reuse: same core as gatecat__snes_mister_ulx3s, plus ulx3s/esp32 OSD loader
• Tests: 1 tb/test files;tools: ghdl-sim
• Notes: last push 2020-10-25, 5 years stale vs gatecat’s 2025 push; gatecat__snes_mister_ulx3s is the more actively maintained copy

emard__st7789py_mpy

• Functions: esp32, oled-lcd
• ULX3S build: no ULX3S-specific (LPF: n/a)
• Reuse: st7789py.py
• Tests: 1 tb/test files
• Notes: generic

emard__synthowheel

• Functions: synth-audio, audio-spdif, audio-dac
• ULX3S build: ulx3s/ (top_ulx3s.vhd, synth.ldf) (LPF: ulx3s_v18.lpf)
• Reuse: synth.vhd, spdif_tx.vhd, sigmadelta.vhd
• Tests: none found
• Notes: early v1.8 era; integrated into f32c

emard__ti99_2

• Functions: retro-computer, video-dvi, ps2, esp32, sdcard
• ULX3S build: root (make_emard.sh), esp32/ (LPF: ulx3s.lpf)
• Reuse: ecp5pll.sv
• Tests: none found
• Notes: needs pnru checkout at ./ti99

emard__tinyfpga-bootloader-ulx3s

• Functions: bootloader, flash-spi, jtag, board-hw, constraints, toolchain
• ULX3S build: boards/ulx3s/ (bootloader_ulx3s.v, constraints/ulx3s_v20.lpf, makefile.trellis, makefile.diamond) (LPF: ulx3s_v20.lpf (also v314, v316 variants in constraints/))
• Reuse: boards/ulx3s/bootloader_ulx3s.v – self-contained USB/SPI-flash bootloader core
• Tests: none found
• Notes: README is a one-liner (“boards subdirectory trying to compile…”); experimental port, unclear if fully working

emard__uk101onfpga

• Functions: retro-computer, video-dvi, audio-spdif, ps2, uart, esp32
• ULX3S build: proj/lattice/orao_ulx3s_dvi, uk101_64x32_ulx3s_hdmi (LPF: ulx3s_v20_segpdi.lpf, ulx3s_v18.lpf)
• Reuse: rtl_emard/spi_ram/spi_ram_slave.vhd (ESP32 SPI RAM), osd, T65
• Tests: none found
• Notes: 2020

emard__ulx2s

• Functions: board-hw
• ULX3S build: n/a; this repo IS the ULX2S predecessor board, no ULX3S/ECP5 content; KiCad project ulx2s.pro, schematic ulx2s.bak, layout ulx2s.kicad_pcb-bak (LPF: ULX2S (predecessor to ULX3S; not ULX3S itself))
• Reuse: footprints/{lattice,micro-hdmi-d,usb_otg,usbserial}: KiCad footprints reusable for other Lattice XP2/USB/HDMI board designs; original_gerbers/: reference layout of the original ULX2S
• Tests: none found
• Notes: last commit 2017-11-21 (git log); README says project is WIP to turn it into a complete KiCad project; linked manual is in Croatian (nxlab.fer.hr), predates ULX3S

emard__ulx3s

• Functions: board-hw, constraints
• ULX3S build: doc/constraints/ (LPF: all (v17patch, v20, v314, v316))
• Reuse: LPF files, MANUAL
• Tests: none found
• Notes: ground truth for pins

emard__ulx3s-bin

• Functions: examples, bootloader, esp32, soc-cpu, linux, retro-computer, sdram, ethernet, usb-host, adc, programmer-tool
• ULX3S build: fpga/* (LPF: v17patch, v18, v20, v314, v317)
• Reuse: self-test, memtest, DFU bootloader images
• Tests: none found
• Notes: see docs/projects/emard__ulx3s-bin.md

emard__ulx3s-emi

• Functions: video-dvi, sdram, adc, board-hw, constraints
• ULX3S build: hdl/ + proj/ (constraints/ulx3s_v20*.lpf, makefile-720x480.{trellis,diamond}) (LPF: ulx3s_v20.lpf, ulx3s_v20_segpdi.lpf, ulx3s_v314.lpf, ulx3s_v316.lpf, ulx3s_v20_extgpdi.lpf, ulx3s_v20_sd4bit.lpf)
• Reuse: hdl/mem_tester.v SDRAM tester, hdl/vga2dvid.vhd DVI encoder, hdl/max1112x_*.vhd ADC reader
• Tests: none found
• Notes: small demo/diagnostic core rather than a full application; real ULX3S build present

emard__ulx3s-jtagthru

• Functions: jtag, programmer-tool, board-hw, constraints
• ULX3S build: jtagthru.v + constraints/ulx3s_v20_segpdi.lpf + makefile.trellis/makefile.diamond (LPF: ulx3s_v20_segpdi.lpf)
• Reuse: jtagthru.v — minimal single-purpose module
• Tests: none found
• Notes: README recommends Diamond over open toolchain because prjtrellis/nextpnr may have bugs with “inout” bidirectional pin declarations; tiny utility repo

emard__ulx3s-misc

• Functions: examples, video-dvi, oled-lcd, audio-dac, audio-i2s, sdram, flash-spi, sdcard, usb-device, usb-host, ps2, uart, jtag, esp32, adc, ethernet, rtc-power, bootloader, dsp-sdr, camera, eink, lvds-display, led-matrix
• ULX3S build: examples//proj/ (makefile.trellis + makefile.diamond), scripts/ (LPF: ulx3s_v20 + variants, v31/v314/v316, v17patch, ulx4m)
• Reuse: ecp5pll (sv/vhd); dvi (vga2dvid, tmds_encoder), dvi_osd, dvi_in; spi_display ST7789/SSD1331/SSD1351; sdram (pnru, mist, 16bit, memtest_mister); qspi; usbhost/usbcdc/usb11_phy; ps2, db9joy; i2s; fm/rds; adc max1112x; eth rmii; ov7670; multiboot
• Tests: dirs: ./examples/audio/testbench;1 tb/test files
• Notes: most complete current ULX3S library; hard-coded tool path /mt/scratch/tmp/openfpga

emard__ulx3s-passthru

• Functions: esp32, uart, oled-lcd, sdcard, bootloader
• ULX3S build: rtl/, proj/universal-make/, proj/scripts/ (LPF: ulx3s_v20.lpf (+v17p))
• Reuse: rtl/ulx3s_v20_passthru_wifi.vhd, proj/scripts/ulx3s_diamond.mk + ulx3s_trellis.mk (emard universal make)
• Tests: none found
• Notes: factory ESP32-flashing bitstream; per-flash-chip xcf

emard__ulx3s_c64

• Functions: retro-computer, video-dvi, audio-spdif, ps2, board-hw, constraints
• ULX3S build: rtl/top_ulx3s_v20_c64.vhd + proj/ (constraints/ulx3s_v20*.lpf, makefilevhdl.{trellis,diamond}) (LPF: ulx3s_v20.lpf, ulx3s_v20_extgpdi.lpf, ulx3s_v31.lpf)
• Reuse: rtl/cpu_6510.vhd 6510 CPU, rtl/video_vicII_656x.vhd VIC-II, rtl/mos6526.v CIA, rtl/spdif_tx.vhd SPDIF audio
• Tests: dirs: ./rtl/test
• Notes: SID8580 doesn’t compile per README (SID6581 works); real working build, boots to READY prompt per author; no SDRAM used (BRAM-based)

emard__ulx3s_galaksija

• Functions: retro-computer, video-dvi, ps2, uart, board-hw, constraints
• ULX3S build: proj/lattice/ulx3s-universal-make/ (top/galaksija_ulx3s.v + constraints) (LPF: ulx3s_v20.lpf, ulx3s_v20_segpdi.lpf)
• Reuse: tv80 Z80 CPU core (tv80n/tv80_alu/tv80_reg/tv80_mcode.v), ps2.v keyboard, uart_rx.v
• Tests: none found
• Notes: emard’s standard universal-make template (both toolchains); verified real ULX3S build present

emard__ulx3s_vic_20

• Functions: retro-computer, video-dvi, ps2, uart, esp32, sdcard
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s/ulx3s_v20.lpf)
• Reuse: src/vic20.v, src/m6522.v (VIA), src/cpu.v (6502-family), src/osd/ (shared SPI OSD stack)
• Tests: none found
• Notes: part of emard’s large family of same-pattern ULX3S retro-computer ports (68k, sms, msx, vic20 all share syncfork.sh/ulx3s.mk/osd structure)

emard__usb_host

• Functions: usb-host, ps2, soc-cpu, uart, board-hw, constraints
• ULX3S build: soc/ (ulx3s_v20.lpf, build.sh) (LPF: ulx3s_v20.lpf)
• Reuse: usb11/ (phy.v, sie.v, regs.v – standalone USB1.1 host PHY/SIE), ucmem/ (BRAM firmware loader)
• Tests: dirs: ./tb;1 tb/test files;tools: iverilog
• Notes: Small embedded RISC-V core loaded into 16K BRAM via ecpbram; firmware built with plan9 riscv-kencc cross-compiler (unusual toolchain choice)

emard__verilog_tic-tac-toe

• Functions: retro-console, video-dvi, uart, education
• ULX3S build: root (LPF: ulx3s_v20_segpdi.lpf)
• Reuse: DVI_3x3.v, TMDS_encoder.v
• Tests: tools: verilator
• Notes: prefer doctorwkt copy

emard__vhdl_c64_c1541_sd

• Functions: retro-computer, sdcard, ps2, video-composite, audio-dac, jtag, multi-board, board-hw, constraints
• ULX3S build: proj/lattice/ulx3s/ (constraints/ulx3s_v18.lpf, top/c64_ulx3s.vhd, ulx3s_sram.xcf, ulx3s_flash.xcf) (LPF: ulx3s_v18.lpf)
• Reuse: rtl_dar/, rtl_emard/ (VIC-II/SID/CPU cores, HDMI/VGA generic video helpers, spdif), t65/ (6502 core)
• Tests: none found
• Notes: README explicitly says “Currently it doesn’t work (no sync on HDMI monitor)… I give up.” – known broken/abandoned for the ULX3S target; other boards (DE0-Nano/DE1/DE2) may fare differently

emard__vhdl_phoenix

• Functions: retro-arcade, video-dvi, audio-spdif, audio-dac, usb-host, ps2
• ULX3S build: proj/lattice/ulx3s (LPF: ulx3s_v20_segpdi.lpf)
• Reuse: rtl_emard/usb (usbhost + 48MHz phy), rtl_emard/vga/hdmi, osd, spdif_tx
• Tests: none found
• Notes: ROMs from MAME zip

emard__wifijtag

• Functions: jtag, programmer-tool
• ULX3S build: no ULX3S-specific (LPF: n/a)
• Reuse: WiFiJTAG.cpp SVF player
• Tests: none found
• Notes: ESP8266, 2017; superseded by esp32ecp5

embeddeddojo__ulx3s_examples

• Functions: board-hw, uart, examples, constraints
• ULX3S build: basic/{btn_led,binary_decoder,pll_counter}/ each with its own ulx3s_v20.lpf (some under constraints/ subdir); pll_counter also has a committed rtl/bin/ulx3s.bit (LPF: basic/btn_led/ulx3s_v20.lpf, basic/binary_decoder/constraints/ulx3s_v20.lpf, basic/pll_counter/constraints/ulx3s_v20.lpf)
• Reuse: basic/pll_counter (PLL generation script + counter, reusable pattern); basic/binary_decoder includes an iverilog testbench (tb/)
• Tests: dirs: ./basic/binary_decoder/tb ./basic/pll_counter/tb;2 tb/test files;tools: iverilog
• Notes: README lists a roadmap (US2 serial, ESP32 WiFi, LiteX SoC, FuseSoc, WB slaves, camera) with only the PLL item checked off; the other items are aspirational/not yet done.

emeb__iceradio

• Functions: dsp-sdr, radio-rx, adc
• ULX3S build: not ULX3S; FPGA/rxadc_2/verilog/rxadc_2/rxadc_2_syn.prj, FPGA/rxadc_2/verilog/src/rxadc_2.v, rxadc.sdc (iCEcube2 project, no Makefile) (LPF: custom STM32F303+iCE5LP4K board (not ULX3S); rxadc.pcf)
• Reuse: FPGA/rxadc_2/verilog/src/{tuner_2.v,ddc_2.v,cic_dec_2.v,cic_dec_3.v,fir8dec.v}: real->complex tuner + CIC decimator + 8x FIR decimator chain, portable parametrized Verilog, no vendor primitives in these blocks; rxadc_2.v top uses SB_GB clock buffer (SiliconBlue iCE5LP4K primitive, port for ECP5)
• Tests: none found
• Notes: Last commit 2017-03-22. First generation of emeb’s DDC lineage: iceRadio(iCE5LP4K,2017) -> rpi_rxadc(UP5K,2020) -> OrangeCrab-Litex-ADC(ECP5,2020); same tuner_2/cic_dec/fir8dec modules recur across all three. No submodules.

emeb__orangecrab-litex-adc

• Functions: dsp-sdr, adc, audio-dac
• ULX3S build: not ULX3S; hw/OrangeCrab-bitstream.py (LiteX target), hw/rtl/sdr.py, hw/vsrc/{ddc_14.v,demods.v,pdm_dac.v} (LPF: OrangeCrab r0.2 Feather + custom ocadc ADC FeatherWing (not ULX3S))
• Reuse: hw/vsrc/{ddc_14.v,demods.v,tuner_2.v,cic_dec_4.v,fir8dec_par.v,pdm_dac.v}: DDC (14-bit IF->16-bit I/Q, decim 2048, 50MSPS->24.414kHz), r2p.v rect->polar demod, sigma-delta PDM DAC; portable Verilog, no ECP5 primitives seen; instantiated from hw/rtl/sdr.py Migen CSR wrapper
• Tests: tools: cocotb
• Notes: Last commit 2020-09-17. LiteX gateware behind the already-catalogued emeb__orangecrab_adc (README links it as the SDR test app for the same AD9203 board). .gitmodules lists hw/deps/{valentyusb,litedram,litex,migen,litex-boards,pythondata-cpu-vexriscv}; only valentyusb@c595e1c is FETCHED (submodules.tsv/verified on disk) - litex/litedram/migen/litex-boards/vexriscv are NOT fetched, so the LiteX build cannot be reproduced from this clone.

emeb__orangecrab_adc

• Functions: adc, audio-dac, dsp-sdr, board-hw
• ULX3S build: gateware/verilog/trellis/Makefile, gateware/verilog/trellis/ocadc.v, gateware/verilog/trellis/ocadc.lpf (nMigen variant: gateware/nmigen/top.py; neither has ULX3S support) (LPF: OrangeCrab r0.2 Feather + custom “ocadc” ADC FeatherWing (not ULX3S))
• Reuse: gateware/verilog/src/ddc_14.v + demods.v + tuner_2.v (digital down-converter/AM-FM demodulator chain, portable Verilog), cic_dec_4.v + fir8dec_par.v (CIC decimator + FIR filter, portable), pdm_dac.v (sigma-delta PDM DAC, portable) - no ECP5 primitives seen in these blocks
• Tests: dirs: ./gateware/nmigen/tests;2 tb/test files;tools: verilator,iverilog
• Notes: Last commit 2020-08-18. No prebuilt bitstream; README status log stops there (preliminary hardware, KiCad+PCB included). icarus/Makefile invokes iverilog via a $(VLOG) variable (scanner misses it): tb_ocadc.v/tb_r2p.v run but have no $display/assert - waveform-only via gtkwave. Companion LiteX project OrangeCrab-Litex-ADC is linked, not cloned here.

emeb__rpi_rxadc

• Functions: dsp-sdr, radio-rx, dsp, adc, audio-i2s
• ULX3S build: gateware/icehat_rxadc/icestorm/icehat_rxadc.v, icehat_rxadc.pcf, icehat_rxadc.sdc, Makefile (LPF: icehat (Raspberry Pi HAT) + rxadc analog front-end board (gateware/icehat_rxadc/icestorm/icehat_rxadc.pcf); not ULX3S)
• Reuse: gateware/icehat_rxadc/src/{tuner_2.v,ddc_14.v,cic_dec_4.v,fir8dec.v}: real->complex NCO tuner feeding a full DDC chain (14-bit IF -> CIC x4 -> 8x FIR decimator -> 16-bit I/Q, decimation 2048, 50MSPS->24.414kSPS), portable Verilog with no SB_* primitives seen in these files; same module lineage (tuner_2/cic_dec/fir8dec/ddc_14) is reused, per the RF/DSP survey, in emeb/iceRadio and emeb/OrangeCrab-Litex-ADC (neither cloned yet)
• Tests: 1 tb/test files;tools: verilator,iverilog
• Notes: Last commit 2020-07-18 (git log -1). icestorm.sdc declares a 50MHz nextpnr clock constraint (ctx.addClock("clk", 50)). Companion Raspberry Pi HAT board (icehat) driven over I2C/SPI/I2S from RPi GPIO via software/ice_tool and software/audio_fulldup. No submodules. Part of E. Brombaugh’s DDC lineage: iceRadio (2017, iCE5LP4K) -> rpi_rxadc (2020, this repo) -> OrangeCrab-Litex-ADC (2020, ECP5).

emeb__ulx3s_6502

• Functions: soc-cpu, uart, examples, education
• ULX3S build: trellis/ (LPF: ulx3s_v20.lpf)
• Reuse: src/acia*.v, ecpbram ROM-patch flow; verilog-6502/cpu.v + verilog-6502/ALU.v (Arlet Ottens’ synchronous-memory 6502 core) is the actual CPU, wired in via trellis/Makefile
• Tests: 1 tb/test files;tools: verilator,iverilog
• Notes: Submodules fetched 2026-09-27: verilog-6502@a116310

emeb__up5k_osc

• Functions: board-hw, adc, synth-audio, audio-dac, flash-spi, uart, bootloader, soc-cpu
• ULX3S build: gateware/icestorm/ (Makefile, up5k_osc_top.pcf, up5k_osc_top.sdc); optional gateware/riscv/icestorm/ for RISC-V variant (LPF: custom up5k_osc Eurorack PCB, iCE40 UltraPlus 5K SG48 (pinout modeled on iCEBreaker bitsy for NO2 bootloader compat) (not ULX3S))
• Reuse: gateware/src/osc2.v (NCO, portable logic), expo_calc.v+expo.hex (exp VCO table), sine.v (sine NCO); pdm.v uses SB_IO/SB_LVCMOS, needs ECP5 IO primitives
• Tests: 2 tb/test files;tools: verilator,iverilog
• Notes: Verified MIT license + open icestorm flow. No prebuilt bitstream. Uses picorv32 (submodule not fetched here; same core catalogued under spritetm__hadbadge2019_fpgasoc). Active hobby/product hardware (KiCad+BOM+schematic). SB_PLL40_2F_PAD/SB_RGBA_DRV/SB_IO need ECP5 equivalents; 12MHz osc not 25MHz.

emeb__up5k_vga

• Functions: soc-cpu, video-vga, uart, ps2, audio-dac, retro-computer, flash-spi
• ULX3S build: icestorm/ (Makefile, up5k_vga.pcf, up5k_vga.sdc) (LPF: custom up5k_usb board rev 0.1/0.2 (iCE40 UltraPlus 5K) (not ULX3S))
• Reuse: src/vga.v (VGA timing, portable), ps2_decode.v/ps2_rx.v/ps2_tx.v (PS/2, portable), acia.v+acia_tx/rx.v (UART, portable), verilog-6502/cpu_65c02.v (CPU, portable); ram_32kb.v/vram_32kb.v use SB_SPRAM256KA
• Tests: 1 tb/test files;tools: verilator,iverilog
• Notes: Verified MIT license + icestorm flow. verilog-6502 fetched as submodule (hoglet67 fork w/ 65C02, per submodules.tsv). README warns 40MHz pixel-clock closure can be flaky, rerun make. No prebuilt bitstream. SB_SPRAM256KA/SB_LEDDA_IP/SB_RGBA_DRV/SB_SPI need ECP5 substitution; 16MHz osc not 25MHz.

enjoy-digital__litedsp

• Functions: dsp, NEW:fft, toolchain
• ULX3S build: no board Makefile/.pcf/.lpf; impl/ecp5.py (out-of-context synth_ecp5+nextpnr-ecp5 –um5g-85k, no full P&R/bitstream); library entry litedsp/analysis/fft.py (LPF: none (LiteX library; ECP5 evidence is impl/ecp5.py out-of-context synth only, no board/lpf); not ULX3S)
• Reuse: litedsp/analysis/fft.py (LiteDSPFFTStage/LiteDSPFFT/LiteDSPFFTFoldedStage/LiteDSPInterleavedFFT) + fft_iter.py/fft_parallel.py/goertzel.py/welch.py/psd.py: Migen/LiteX radix-2 SDF FFT/IFFT (64-pt default, power-of-two N, scaled or block-floating-point, classic/folded architecture) plus Goertzel/Welch-PSD/PFB-channelizer; pure Migen HDL generator, FPGA-vendor-agnostic, ECP5 impl flow verified (LFE5UM5G-85F: 4387 LUT/360 FF/28 DSP at N=64)
• Tests: dirs: ./test ./sim;168 tb/test files
• Notes: Last commit 2026-09-24. BSD-2-Clause. Pure Migen/LiteX library (WIP, 430 .py files), no dedicated board; ECP5 evidence is impl/ecp5.py’s out-of-context yosys+nextpnr-ecp5 resource/Fmax regression (LFE5UM5G-85F, no .lpf/pinout). README claims 186 blocks co-simulated bit-exact/SNR-checked vs NumPy under randomised backpressure in CI.

enjoy-digital__liteiclink

• Functions: serdes-pcie-sata, NEW:serdes
• ULX3S build: bench/serdes/versa_ecp5.py, bench/serdes/ecpix5.py (SERDES/PRBS top for ECP5-5G); bench/serwb/ulx3s.py (ULX3S top using SerWB, not SERDES); liteiclink/serdes/serdes_ecp5.py, liteiclink/serwb/*.py (cores). No LPF here (litex-boards platforms, external). (LPF: Versa ECP5-5G + ECPIX-5 (SERDES benches); ULX3S 12F/25F/45F/85F (SerWB bench, via litex_boards.platforms.radiona_ulx3s, no local .lpf))
• Reuse: liteiclink/serdes/serdes_ecp5.py: SerDesECP5PLL+SerDesECP5 (DCUA wrapper, 8b10b, PRBS), base of LiteSATA’s ECP5 PHY and kazkojima’s SGMII; portable to any LFE5UM/LFE5UM5G part. liteiclink/serwb/{core,genphy}.py: SerWB soft link (bit-banged LVCMOS, no SERDES needed), the only path here to link two plain (no-SERDES) ECP5U boards such as ULX3S.
• Tests: dirs: ./test;7 tb/test files
• Notes: Active (last commit 2026-09-28). serdes_ecp5.py PRBS benches are the working SERDES demo; the ULX3S serwb bench is a soft link demo, not a SERDES demo (ULX3S has no hard SERDES). No submodules. Depends on external litex-boards/litex/migen packages.

enjoy-digital__litesata

• Functions: serdes-pcie-sata, NEW:sata
• ULX3S build: bench/ecpix5.py (top, –device 85F/45F –sata-gen gen2); litesata/phy/ecp5sataphy.py (ECP5 PHY core); test/test_phy.py (unit/sim tests). No LPF in this repo (uses litex-boards’ lambdaconcept_ecpix5 platform, external). (LPF: ECPIX-5 (LambdaConcept, 45F/85F; via litex-boards lambdaconcept_ecpix5 platform, no local .lpf))
• Reuse: litesata/phy/ecp5sataphy.py: ECP5LiteSATAPHY/ECP5LiteSATAPHYCRG/OOB gen+checker on top of liteiclink SerDesECP5 (DCUA); portable to any LFE5UM/LFE5UM5G board with a SATA-wired DCU channel. litesata/core.py + link/transport/command layers are FPGA-agnostic Migen/LiteX, reused as-is across all PHYs.
• Tests: dirs: ./test;14 tb/test files
• Notes: Active (last commit 2026-09-28). Validated with IDENTIFY + 16 MiB write/verify BIST on ECPIX-5 (per LiteX 2026.08 CHANGES, not reproduced locally). No submodules. Depends on external liteiclink (SerDesECP5) and litex-boards (ecpix5 platform) packages, not vendored.

eringr__nmigen_fibonacci

• Functions: education, gpio
• ULX3S build: fib.py (whole design; ends with platform.build(m, do_program=True)) (LPF: nmigen_boards ULX3S_85F_Platform (revision unspecified))
• Reuse: fib.py classes MainMemory/RegisterFile/FibProcessor/InputDebouncer: small self-contained nMigen FSM examples (button debounce, 5-instruction toy ISA), portable, no vendor primitives instantiated directly (relies on nmigen_boards abstractions).
• Tests: none found
• Notes: Last commit 2021-10-13. README states ‘Tested on ULX3S fpga board’ (unverified in this clone – no CI/log evidence – but the design is a trivial LED+button IO circuit, so plausible).

evansm7__arcdvi

• Functions: video-dvi, retro-computer, board-hw
• ULX3S build: platform/ulx3s/ulx3s_v20.lpf + top Makefile (LPF: platform/ulx3s/ulx3s_v20.lpf)
• Reuse: platform/ulx3s/ VIDC-capture-to-DVI signal reconstruction core reusable for other retro-video-passthrough designs
• Tests: dirs: ./tb;2 tb/test files;tools: iverilog
• Notes: README explicitly labels this “**DEPRECATED PROTOTYPE**”; project reached “successful prototype” stage only, with a follow-on consolidated PCB design as next step (not this repo)

evgenymuryshkin__quokkaevaluation

• Functions: toolchain, hdl-language, uart, led-matrix, examples
• ULX3S build: no ULX3S/ECP5 build anywhere in the clone; per-demo FPGA project files: fpga/Quokka.qsf (Cyclone IV E), FPGAConf/arty/Arty-Z7-20-Master.xdc (Zynq), FPGAConf/artyA35/artyA35.xpr (Artix-7) (LPF: Quokka board (Cyclone IV E EP4CE6E22C8, not ULX3S); also Digilent Arty Z7-20 and Arty A7-35 dev boards (not ULX3S))
• Reuse: Drivers/.cs and FunctionalTest/Controllers.cs: portable C# peripheral drivers/testbench-style controllers for the Quokka codegen flow only, not directly reusable as HDL; VHDL/fpu100: vendored floating-point unit (own license unclear)
• Tests: none found
• Notes: Last commit 2026-03-04 (active). NOT ECP5: this is a .NET-based HDL code-generation toolkit for the proprietary Quokka board (Cyclone IV E) with extra Xilinx Arty targets; no board/toolchain evidence points at ECP5 or ULX3S. No submodules.

f32c__arduino

• Functions: toolchain, examples, soc-cpu
• ULX3S build: hardware/fpga/f32c/boards.txt fpga_ulx3s (LPF: v20, v17p)
• Reuse: libraries/ (F32C VGA/video, PCM, SD, PS2, RDS, TTS)
• Tests: none found
• Notes: 2019

f32c__f32c

• Functions: soc-cpu, sdram, video-dvi, video-composite, audio-dac, audio-spdif, audio-i2s, uart, usb-device, ps2, flash-spi, sdcard, esp32, adc, oled-lcd, bootloader, fm-transmitter
• ULX3S build: rtl/proj/lattice/ulx3s/ (17 variants: xram_sdram_{normal,433,lvds,selftest,synth,text,tvfm}, bram, …) (LPF: ulx3s_v20.lpf, v20_segpdi, v17patch (v316 commented))
• Reuse: rtl/cpu f32c_core; rtl/soc sdram*.vhd, vgahdmi/, dvi_fb, cvbs (PAL), usb11_phy, usb_serial, spdif_tx, i2s, synth, fm/ (RDS), ps2, rtc, vector FPU
• Tests: none found
• Notes: the SoC the board was designed for; self-test source

f32c__fpgarduino

• Functions: toolchain, programmer-tool, bootloader, soc-cpu
• ULX3S build: bootloaders.zip bootloaders/ulx3s/ (26 bitstreams) (LPF: v20)
• Reuse: prebuilt f32c bitstreams
• Tests: none found
• Notes: ~500MB binaries; 2019

f32c__tools

• Functions: programmer-tool, jtag, flash-spi, uart
• ULX3S build: ujprog/ujprog.c (ULX3S cable table) (LPF: v1.7, v2.1.2, v3.0.3, v3.0.7)
• Reuse: ujprog.c, f32cup.py
• Tests: none found
• Notes: still active 2026-05

fdarling__orangecrab-usb-cdc-demo

• Functions: usb-device, board-hw, constraints
• ULX3S build: ./ (Makefile, orangecrab_r0.2.pcf, src/usb_serial_test.v top module) (LPF: OrangeCrab r0.2 (not ULX3S))
• Reuse: src/usb_serial_test.v + src/usb_uart_ecp5.v (thin USB-CDC top wrapper, 48MHz clock); tinyfpga_bx_usbserial/usb/*.v (full USB FS device core: usb_fs_pe.v, usb_uart_core.v, usb_uart_bridge_ep.v, usb_serial_ctrl_ep.v - portable Verilog, needs 48MHz clk + USB D+/D- pins)
• Tests: none found
• Notes: Verified: Apache-2.0 LICENSE, Makefile builds OrangeCrab r0.2 only (–25k, CSFBGA285). clk48=48MHz input, not ULX3S’s 25MHz osc. Submodules fetched 2026-09-27: tinyfpga_bx_usbserial@00608c2 (Apache-2.0, matches top license, no conflict).

fedy0__neo

• Functions: soc-cpu, uart, flash-spi, board-hw, constraints
• ULX3S build: top/ (neorv32_ULX3S_BoardTop_MinimalBoot.vhd) + Makefile + ULX3S.lpf (LPF: ULX3S.lpf)
• Reuse: top/neorv32_ULX3S_BoardTop_MinimalBoot.vhd, top/neorv32_ULX3S_xip.vhd (XIP flash-execute variant, Makefile.xip)
• Tests: none found
• Notes: neorv32/ submodule is empty in this clone (git submodule not initialized) – repo cannot build as-is without fetching stnolting/neorv32 separately

fedy0__zta

• Functions: ml-accelerator, soc-cpu, board-hw, constraints
• ULX3S build: top/main.v + constraints/ULX3S.lpf (LPF: constraints/ULX3S.lpf)
• Reuse: components/ecp5pll.sv PLL generator; components/axi-crossbar (also a submodule, not fetched)
• Tests: none found
• Notes: README explicitly says “Still Under construction (a 64-bit memory controller needed)”; components/ztachip submodule directory is EMPTY in this clone so the repo cannot actually build as cloned — genuinely unverified/incomplete

felipesanches__anotherworld_fpga

• Functions: retro-computer, video-dvi
• ULX3S build: root (LPF: ulx3s_v20.lpf)
• Reuse: little
• Tests: none found
• Notes: abandoned WIP, pin map “probably wrong”

flyingoverclouds__flocs-ulx3s-samples

• Functions: board-hw, examples, constraints
• ULX3S build: 6 project dirs, each with its own ulx3s_v20.lpf + .ys + synthetize_bit.cmd/deploy_bit.cmd (LPF: 6x ulx3s_v20.lpf (one per sample dir))
• Reuse: debounce/ (blinky-pushbuttons-debounced/debouncer.v) reusable debounce module; pwm/ (led-pwm/pwm.v) reusable PWM module
• Tests: none found
• Notes: Windows-oriented workflow (.cmd batch files, PowerShell not required) rather than the usual Makefile; otherwise clean, working, well-documented small samples.

fm4dd__pmod-7seg9

• Functions: gpio, NEW:seven-segment-display
• ULX3S build: examples/ulx3s/pmod_7seg91/{pmod_7seg9_1.v,tm1640.v,ulx3s.lpf,Makefile}; examples/ulx3s/pmod_7seg9_2/{ctl_7seg9.v,hexdigit.v,pmod_7seg9_2.v,tm1640.v,ulx3s.lpf,Makefile} (LPF: examples/ulx3s/pmod_7seg9{1,2}/ulx3s.lpf)
• Reuse: examples/ulx3s/pmod_7seg9_2/tm1640.v (+hexdigit.v/ctl_7seg9.v): compact TM1640 2-wire LED driver + hex-digit encoder, small self-contained portable Verilog, reused near-verbatim across the icebreaker/ulx3s examples
• Tests: tools: iverilog
• Notes: Last commit 2026-02-14. PCB/hardware repo (Gerbers in fabfiles/); ULX3S is one of several example targets for the same PMOD, real minimal build present (2 examples with Makefile+lpf).

fm4dd__pmod-charlcd

• Functions: oled-lcd, gpio, NEW:hd44780-lcd
• ULX3S build: examples/ulx3s/display/{Makefile,display.v,debounce.v,lcd_transmit.v,ulx3s.lpf} (LPF: ULX3S (ulx3s.lpf, revision unspecified); IceBreaker v1.0 (not ULX3S); GateMate EVB (not ULX3S))
• Reuse: examples/ulx3s/display/{lcd_transmit.v,debounce.v}: small portable HD44780 4/8-bit transmit + debounce modules, no vendor primitives, reused verbatim across all three board examples
• Tests: tools: iverilog
• Notes: last commit 2024-02-24. Also a real PCB (fabfiles/ Gerbers, kicad/ source), not gateware-only. Candidate reusable core for the oled-lcd/spi-display function (flagged in cores_brief).

fpgawars__flix-v

• Functions: soc-cpu, linux, uart, sdram, flash-spi, board-hw, constraints
• ULX3S build: Hardware/KianV-Apio/ (apio.ini board=ulx3s-12f, ulx3s_v20.lpf, soc-top.v) (LPF: ulx3s_v20.lpf)
• Reuse: Hardware/KianV-Apio/*.v KianV RISC-V core + SDRAM controller + UART, all reusable modules
• Tests: none found
• Notes: Demo/ ships a prebuilt Soc-Kianv-ULX3S-12F.bit; goal is running Linux on a no-MMU RISC-V soft core

fulig__tinyfpga_fft

• Functions: dsp, NEW:fft, adc, spi
• ULX3S build: NOT ULX3S; 8FFT/top.v (top, full 8-pt datapath) and FFT_stage/{fft.v,fft_stage.v} (top, iterative single-stage variant), 8FFT/pins.pcf, 8FFT/apio.ini + FFT_stage/apio.ini (LPF: TinyFPGA BX (iCE40 LP8K); not ULX3S)
• Reuse: FFT_stage/fft_stage.v + bfprocessor.v (one reusable butterfly-processor stage instantiated N/2 times via generate, reloaded per FFT stage - smaller footprint than 8FFT’s fully-unrolled datapath, good template for resource-constrained iCE40 designs); 8FFT/adc-spi.v (simple SPI ADC sampler)
• Tests: 2 tb/test files
• Notes: Last commit 2022-08-29 (git log). Written for the author’s bachelor thesis (README.md). 8FFT/ has a prebuilt hardware.bin/hardware.blif; FFT_stage/ has hardware.bin only. top_tb.v testbenches exist in 8FFT/ but apio has no built-in simulation flow and no Makefile is present.

fusesoc__blinky

• Functions: board-hw, constraints, examples
• ULX3S build: ulx3s/ (ulx3s_v20.lpf, blinky_ulx3s.v); blinky.core defines ulx3s_45 and ulx3s_85 FuseSoC targets (LPF: ulx3s_v20.lpf)
• Reuse: blinky_ulx3s.v trivial single-LED top usable as a minimal FuseSoC+ULX3S starter template
• Tests: 1 tb/test files
• Notes: single-file board port; nothing else present beyond the LED blink demo

fusetim__rusty-soc

• Functions: soc-cpu, spi, sdcard, audio-dac, gpio, hdl-language
• ULX3S build: hardware/Makefile (BOARD = ulx3s default), hardware/src/soc.si (LPF: ULX3S (default BOARD=ulx3s in hardware/Makefile))
• Reuse: hardware/lib/fusetim/spi/SpiMaster.v (+ SpiMasterPeripheral.v): home-made SPI master with its own iverilog testbenches, portable Verilog; hardware/src/audio_viz.v: streaming RMS-energy audio visualizer, portable; silicon-pac/silicon-hal Rust crates: reusable embedded-hal-compatible peripheral access layer
• Tests: tools: verilator,iverilog
• Notes: Last commit 2026-02-08. Ice-V RISC-V core and Silice toolchain are vendored under hardware/lib/silice (plain copy, no .gitmodules).

fywc__ulx3s_rv32i_processor

• Functions: board-hw, soc-cpu, hdl-language
• ULX3S build: rv32i/ (Top.bsv + processor/*.bsv; Makefile drives ‘apio init -b ulx3s-85f’) (LPF: implied via apio ulx3s-85f board profile (no vendored .lpf file in this clone — apio supplies it internally))
• Reuse: processor/ RV32I pipeline stages (RFile, Scoreboard, Decode, Execute) — reusable CPU core modules; sw/ test binaries (microbench, pipesafe/pipeunsafe hazard tests, minisudoku)
• Tests: none found
• Notes: No .lpf committed (relies on apio’s built-in ulx3s-85f board profile, fetched at build time, not vendored) so the exact pin constraints can’t be verified offline; otherwise a substantive, real RV32I core with hazard-test software.

gage1999__fpga-sdr-receiver

• Functions: dsp-sdr, NEW:fft, audio-i2s, sdram
• ULX3S build: NOT ULX3S; icesugar_pro/src/top.sv (top), icesugar_pro/top.lpf, icesugar_pro/Makefile (LPF: iCESugar Pro (LFE5U-25F-6BG256C); not ULX3S)
• Reuse: icesugar_pro/src/fft256.sv + butterfly.sv + twiddle_rom.sv (iterative in-place radix-2 FFT, ping-pong BRAM banks, bit-reversed output, 128-entry inline cos/sin LUT, 16-bit I/Q in, 8-bit log-magnitude+index bins out); spectrum_zoom_decimator.sv/spectrum_bin_ram.sv (bin buffering for the waterfall)
• Tests: dirs: ./icesugar_pro/sim ./icesugar_pro/tests ./icesugar_pro/tb ./plutosky/tests ./tests;23 tb/test files;tools: verilator,iverilog
• Notes: Last commit 2026-09-08 (git log). plutosky/src/maia-sdr submodule NOT fetched (git submodule status shows it unchecked-out, “-c96c496a…”); the plutosky/ host code that references it is present but the submodule tree is empty.

gatecat__snes_mister_ulx3s

• Functions: video-dvi, sdcard, flash-spi, retro-console, board-hw, uart
• ULX3S build: ulx3s/ (top/, pll/, mem/, video/, scripts/build.sh) (LPF: ulx3s/top/ulx3s_v20.lpf)
• Reuse: ulx3s/top/ulx3s_top.v, ulx3s/video/vga2dvid.v+tmds_encoder.v, ulx3s/mem/ dpram/spram wrappers
• Tests: 1 tb/test files;tools: ghdl-sim
• Notes: README: audio distorted, DSP enhancement chip broken, DSP/SA1 games unsupported; actively maintained (2025 push) vs emard’s fork’s 2020

gatecat__trellisboard

• Functions: board-hw, constraints, jtag, toolchain, examples
• ULX3S build: gateware/simple/{demo.v,led_ctrl.v,trellisboard.lpf,Makefile} (nextpnr-ecp5 –um5g-85k); gateware/litex/trellisboard.py (LiteX Platform); openocd cfg gateware/misc/trellisboard.cfg (LPF: TrellisBoard “ecp5_mainboard” rev 1.0 prototype (not ULX3S; hardware/ecp5_mainboard, README))
• Reuse: gateware/simple/led_ctrl.v: small self-contained 12-LED PWM-blend multiplexer, plain Verilog, no vendor primitives - portable as-is; gateware/litex/trellisboard.py: full LiteX IO map for LFE5UM5G-85F CABGA756 (DDR3 x32, GbE RGMII, HDMI TFP410, USB ULPI, QSPI flash, uSD, dual PMOD) - reusable as a LiteX ECP5 target, needs pin remap for ULX3S
• Tests: none found
• Notes: Last commit 2019-07-04 (git log -1). README says “WIP - Rev 1.0 prototypes currently under test”. Repo is >95% KiCad PCB design (hardware/); gateware/ is a tiny LED demo + LiteX SoC platform stub. Onboard 12 MHz osc (clk_12); LVDS clk100 also defined in LiteX platform. Submodule hardware/pkl (pretty-kicad-libs, PCB footprint lib) not fetched - correctly excluded as non-gateware.

gergoerdi__advent-of-clash-2025

• Functions: education, uart, NEW:advent-of-code
• ULX3S build: target/ulx3s/src-hdl/{Top.v,ulx3s_v20_segpdi.lpf}; Shakefile.hs targets "ulx3s-45f"/"ulx3s-85f" via ECP5.ecp5 (LPF: ulx3s_v20_segpdi.lpf (v2.0, segmented-PDI variant))
• Reuse: none identified as a standalone portable block (puzzle-specific circuits); the Clash.Shake.ECP5 build glue is an external dependency, not vendored code
• Tests: none found
• Notes: last commit 2026-01-13. mk/ is empty in this shallow clone (no local synth scripts; the flow comes from the clash-shake Hackage package). Only days 3 and 7 implemented so far.

ghaworth__ulx3s-bldc-foc

• Functions: board-hw, constraints, toolchain
• ULX3S build: NO ULX3S (gateware/rtl, gateware/constraints, gateware/sim, hardware/kicad, hardware/sim, hardware/bom, hardware/fab, model/, docs/design-notes/ are ALL empty, containing only a .gitkeep placeholder each) (LPF: NO ULX3S (gateware/constraints/ulx3s.lpf referenced by Makefile does not exist))
• Reuse: none (repo is entirely design docs + empty directory skeleton)
• Tests: dirs: ./hardware/sim ./gateware/sim
• Notes: Survey evidence unverified and turned out to be pure vapor at this stage: README describes an ambitious two-track FOC + driver-board project with a full directory layout, correct licensing (Apache-2.0/CERN-OHL-P-2.0 split) and a working-looking Makefile, but literally every content directory is empty (.gitkeep only) — ‘Status: Early… Nothing here is fabricated or silicon-validated yet’ is accurate; there is no code at all yet.

ghaworth__ulx3s-tinyai

• Functions: sdram, ml-accelerator
• ULX3S build: NO ULX3S (no top-level ULX3S integration, no LPF, sdram_init.v is a standalone unintegrated module) (LPF: NO ULX3S)
• Reuse: projects/sdram_controller/rtl/sdram_init.v — standalone SDRAM init FSM, reusable as a starting point
• Tests: none found
• Notes: Repo name implies an ML/AI accelerator project but contains only one unintegrated SDRAM-init module and no ULX3S top/LPF/build files; also the LICENSE file is a broken GitHub 404 page (likely a failed curl/download that got committed by mistake), not actual license text.

gildobjanschi__riscv_processor

• Functions: soc-cpu, sdram, flash-spi, uart, timer, gpio, NEW:psram
• ULX3S build: hdl/{risc_p.sv,ulx3s.lpf,fpga.sh -u} (LPF: ULX3S (ulx3s.lpf, revision unspecified); Blue Whale (blue_whale.lpf, not ULX3S))
• Reuse: hdl/ecp5pll.sv: parametric ECP5 PLL wrapper (EHXPLLL), directly portable to other ULX3S designs; hdl/{uart_tx.sv,uart_rx.sv,divider.sv,multiplier.sv,timer.sv}: portable peripherals, no vendor primitives outside ecp5pll.sv
• Tests: tools: iverilog
• Notes: last commit 2024-09-06. Board choice (-u/-w flag) selects RAM_FILE (sdram.sv vs psram.sv) and LPF at build time from the same RTL tree.

glasgowembedded__glasgow

• Functions: usb-device, jtag, spi, i2c, uart, ps2, debug-bridge, logic-analyzer, programmer-tool, flash-spi, adc, oled-lcd, video-vga, led-matrix, floppy, gpio, hdl-language
• ULX3S build: software/glasgow/hardware/platform/rev_c.py (iCE40HX8K BG121, reviewed target), rev_ab.py (UP5K), rev_d.py (ECP5 LFE5U-25F); gateware in software/glasgow/gateware/, applets in software/glasgow/applet/*/; built via glasgow build/pdm (amaranth.build), no Makefile (LPF: Glasgow Interface Explorer revC (iCE40 HX8K BG121, hardware/boards/glasgow/revC0-3); repo also holds revA/B (UP5K) and revD (ECP5 LFE5U-25F) hardware)
• Reuse: software/glasgow/gateware/pll/{ice40.py,ecp5.py}: portable PLL parameter solver + primitive wrapper - ECP5 (EHXPLLL) version already exists, directly reusable for ULX3S, no porting needed; software/glasgow/gateware/{uart.py,spi.py,i2c.py,qspi.py,crc.py,lfsr.py,cobs.py,mdio.py,swd.py}: pure-Amaranth protocol cores with no SB_* primitives, portable to ECP5 as-is; software/glasgow/gateware/jtag/{tap.py,probe.py}: portable JTAG TAP/probe cores. iCE40-only: hardware/platform/ice40.py (amaranth.vendor.LatticeICE40Platform, SB_IO-based) needs the ecp5.py counterpart (already present) when porting a board
• Tests: dirs: ./software/glasgow/simulation ./software/tests;23 tb/test files
• Notes: Very active: last commit 2026-09-25 (git log -1). clk_if/clk_fx = 48 MHz (rev_c.py Resource Clock(48e6)) vs ULX3S 25 MHz. FX2 firmware (firmware/fx2, C for Cypress FX2LP) is explicitly NOT gateware and needs vendor/libfx2 (submodule declared in .gitmodules, not fetched - empty dir, per brief). docs/archive submodule also not fetched (docs only, irrelevant to gateware)

gmejiamtz__ulx3s-components

• Functions: board-hw, toolchain, constraints, examples
• ULX3S build: synth/trellis_ulx3s/ (ulx3s.v, nextpnr_ecp5.lpf, yosys.tcl, nextpnr.py) — ULX3S-specific synthesis target within the generic template (LPF: synth/trellis_ulx3s/nextpnr_ecp5.lpf)
• Reuse: Makefile build flow (lint/sim/gls/trellis_ulx3s_gls/trellis_ulx3s_program targets) — reusable as a project template/skeleton
• Tests: 1 tb/test files;tools: verilator
• Notes: Despite the ‘ulx3s-components’ name this is explicitly a generic template repo (README: ‘A template repo for ECP5 FPGAs with OSS CAD Suite’); the only actual logic is a 1-bit XOR register demo; third_party/basejump_stl submodule not fetched in this shallow clone.

gojimmypi__nextpnr-issue235

• Functions: board-hw, examples, toolchain
• ULX3S build: repo root (blinky.v, blinky.ys, ulx3s_v20.lpf, Makefile, demo.sh) (LPF: ulx3s_v20.lpf)
• Reuse: demo.sh (repro harness for the CRLF/LF nextpnr LPF bug, reusable as a regression test)
• Tests: tools: verilator
• Notes: purpose-built bug-repro project, not a functional design; documents a real (at the time) nextpnr defect

gojimmypi__ttgf-uart-fsm-trng-lab

• Functions: uart, jtag, board-hw, toolchain, NEW:asic-prototyping
• ULX3S build: ulx3s/ (top_ulx3s.v pin-mapping wrapper, ulx3s_build.sh, ulx3s_flash.sh, 4 .lpf variants) (LPF: ulx3s_v314.lpf, ulx3s_v20.lpf, ulx3s_v17patch.lpf, ulx3s_v316.lpf)
• Reuse: src/TRNG/trng_lab_core.v, src/JTAG/jtag_core.v, src/SPI/spi_slave.v, src/PINS/pin_id_core.v (all reusable TT pin/JTAG/SPI/TRNG blocks)
• Tests: dirs: ./test;8 tb/test files;tools: cocotb,verilator,iverilog
• Notes: primary target is a Tiny Tapeout ASIC shuttle; ULX3S is a companion FPGA dev/test board, not the final target

gojimmypi__ttgf0p3-analog-uart-fsm-trng-lab

• Functions: uart, jtag, esp32, crypto
• ULX3S build: ulx3s/ (top_ulx3s.v, Makefile, ulx3s_v20/v314/v316/v17patch.lpf) (LPF: ulx3s_v20.lpf / ulx3s_v314.lpf / ulx3s_v316.lpf / ulx3s_v17patch.lpf, selectable via ULX3S_BOARD_VERSION)
• Reuse: ulx3s/top_ulx3s.v (ULX3S pin wrapper for the TT UART/SPI/FSM/TRNG digital logic), test-hw/ (UART TRNG NIST test scripts)
• Tests: dirs: ./test;8 tb/test files;tools: cocotb,verilator,iverilog
• Notes: Primary target is a Tiny Tapeout GF180 analog ASIC shuttle, not standalone ULX3S gateware; the FPGA build only exercises the digital UART/SPI/FSM/TRNG-monitor portion.

gojimmypi__ttgf0p3-uart-fsm-trng-lab

• Functions: uart, jtag, board-hw, toolchain, NEW:asic-prototyping
• ULX3S build: ulx3s/ (top_ulx3s.v, ulx3s_build.sh, ulx3s_flash.sh, 4 .lpf variants) (LPF: ulx3s_v314.lpf, ulx3s_v20.lpf, ulx3s_v17patch.lpf, ulx3s_v316.lpf)
• Reuse: src/TRNG/trng_lab_core.v, src/JTAG/jtag_core.v, src/SPI/spi_slave.v (same reusable blocks as sibling ttgf repo)
• Tests: dirs: ./test;8 tb/test files;tools: cocotb,verilator,iverilog
• Notes: near-duplicate of ttgf-uart-fsm-trng-lab; keep ttgf-uart-fsm-trng-lab as the primary copy, this is an experimental shuttle fork

gojimmypi__ttsky-uart-fsm-trng-lab

• Functions: uart, jtag, board-hw, toolchain, NEW:asic-prototyping
• ULX3S build: ulx3s/ (top_ulx3s.v, ulx3s_build.sh, ulx3s_flash.sh, 4 .lpf variants) (LPF: ulx3s_v314.lpf, ulx3s_v20.lpf, ulx3s_v17patch.lpf, ulx3s_v316.lpf)
• Reuse: src/UART/uart_trng_ascii_core.v + uart_rx_min.v/uart_tx_min.v (dedicated UART core, not present in ttgf), test-hw/*.py (hardware-in-loop test scripts over UART)
• Tests: dirs: ./test;8 tb/test files;tools: cocotb,verilator,iverilog
• Notes: best copy of the three gojimmypi TT labs: has extra UART core, STATUS.md, and test-hw/ hardware test scripts the ttgf variants lack

gojimmypi__ulx3s-adda

• Functions: adc, audio-dac, dsp-sdr, adapter-board
• ULX3S build: root, doc/ (LPF: ulx3s_v20.lpf (+J2_AD/DA names))
• Reuse: J2 AD/DA pin map, doc/
• Tests: none found
• Notes: tiny test; value is docs

gojimmypi__ulx3s-examples

• Functions: examples, education, jtag, esp32, programmer-tool, board-hw, constraints
• ULX3S build: blinky/{OpenSource,Diamond}/, passthru/{OpenSource,Diamond,DiamondVerilog}/ (each w/ ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf (multiple copies across subprojects))
• Reuse: blinky/OpenSource minimal open-toolchain template; passthru/OpenSource ESP32<->FPGA UART passthru
• Tests: tools: verilator
• Notes: large doc-heavy tutorial repo (34MB, many images/PDFs); real ULX3S builds present in multiple toolchain flavors

gojimmypi__z80386-ulx3s-doom

• Functions: board-hw, soc-cpu, retro-computer, jtag, constraints, vga, ide, floppy, sdram, ps2, synth-audio, uart, dma
• ULX3S build: rtl/z386_synth_probe.sv (ULX3S top level) + constraints/ulx3s_v303_probe.lpf (LPF: constraints/ulx3s_v303_probe.lpf)
• Reuse: rtl/z386_synth_probe.sv top-level (reset sequencing, ready/valid harness, LED diagnostics); scripts/ build automation; third_party/z386_MiSTer/src/soc/{vga.v,ide.v,floppy.v,sound/,ps2.v,pit.v,pic.v,dma.v} + src/memory/sdram.v are a full ao486-derived PC-SoC peripheral set, NOT yet wired into the ULX3S probe top (CPU-only today)
• Tests: tools: verilator
• Notes: Well-documented, hardware-validated milestone (known-good config, seed, max frequency) - most mature repo in this batch - but scope is CPU-regression-only; ‘Doom’ in the name is aspirational. Correction: z386_MiSTer is fetched but is only the ao486-derived SoC/peripheral wrapper - the real z386 CPU lives in its own nested unfetched submodule src/z386, still not inspectable. Submodules fetched 2026-09-27: third_party/z386_MiSTer@5a11fe8

gonsolo__borg

• Functions: soc-cpu, gpu, video-dvi, sdram, uart
• ULX3S build: fpga/ulx3s/{soc/src/ULX3S.scala,debug/.lpf,sdram_test/sdram_test.lpf,pmod_test/pmod_test.lpf}, fpga/ulx3s/Makefile (make load/flash/tio) (LPF: fpga/ulx3s/.lpf)
• Reuse: fpga/ulx3s/soc/src/ULX3S.scala (44.6K): full Chisel SoC top incl. HdmiScanoutFp16/Tiled/Gpu, CpuSdramHdmiTest - large reusable HDMI+SDRAM+shader scanout logic, but tightly coupled to the Hutt/Chisel build; vendor primitives not verified by grep
• Tests: dirs: ./hardware/borg/test ./hardware/memory/test ./hardware/peri/test ./hardware/hutt/test ./hardware/soc/test;7 tb/test files;tools: cocotb,verilator,iverilog
• Notes: Last commit 2026-09-28 (active). Per brief, cataloguing the ULX3S-relevant part only; submodules (PeakRDL-chisel, Vulkan-Tools, mesa, +more) not fetched - these support the Vulkan/software side, not the ULX3S FPGA build.

google__cfu-playground

• Functions: soc-cpu, ml-accelerator, toolchain
• ULX3S build: no ULX3S-specific files in this clone; board picked by name via LiteX (soc/common_soc.py imports litex_boards.targets. dynamically); proj/vexriscv/board_specific_workflows/ only has digilent_arty.py, none for ulx3s (LPF: unknown (board file supplied by litex_boards submodule, not fetched))
• Reuse: proj/*/ - CFU accelerator examples (e.g. mnv2_first, hps_accel) attached over the CFU bus to VexRiscv via LiteX; portable to any LiteX/ECP5 target incl. ULX3S but generic, no ULX3S-specific optimizations seen
• Tests: dirs: ./common/_sim/sim;14 tb/test files;tools: verilator
• Notes: Last commit 2026-02-26. Big framework repo (46 MB): per brief, cataloguing the ULX3S-relevant part only. ~20 submodules (litex, litex_boards, migen, amaranth, VexRiscv-related third_party/python/*) not fetched, so the ULX3S claim (README.md:30 ‘tested on … ULX3S’) can’t be verified beyond the generic litex_boards target mechanism.

goran-mahovlic__gpdi_mirror

• Functions: video-dvi, video-input
• ULX3S build: root (GPDI_mirror.v) (LPF: ulx3s_v20_segpdi.lpf)
• Reuse: GPDI_mirror.v
• Tests: none found
• Notes: 2 commits 2020

goran-mahovlic__odysseus_sprites

• Functions: video-dvi, board-hw
• ULX3S build: repo root (top/top.v, ulx3s_v20.lpf, scripts/*.mk) (LPF: ulx3s_v20.lpf)
• Reuse: src/vga2dvid.v, src/tmds_encoder.v, src/hdmi_video.v (TMDS/DVI video pipeline), src/sprite_rom.v (sprite ROM engine)
• Tests: none found
• Notes: shared build-script family (trellis/diamond *.mk) reused across several goran-mahovlic ULX3S repos; device size not confirmed from files inspected

goran-mahovlic__prjtrellis-led64x64

• Functions: examples, led-matrix
• ULX3S build: root (LPF: ulx3s_v20_segpdi.lpf)
• Reuse: emard/ledscan.vhd, sprite_rom.v
• Tests: none found
• Notes: submodule empty

goran-mahovlic__ulx3s-pmod

• Functions: board-hw, pmod-hardware
• ULX3S build: no gateware (LPF: n/a)
• Reuse: GPDI_ULX3S HDMI PMOD, OV7670, USB, ENC28J60, I2S_MIC
• Tests: none found
• Notes: hardware counterpart to gpdi_mirror / dvi_in

gornjas__dvi_test

• Functions: video-dvi, constraints
• ULX3S build: root (ulx3s_fer.lpf, ulx3s_dvi_test.ldf) (LPF: ulx3s_fer.lpf (custom “fer” pin variant))
• Reuse: vga2dvid.vhd, tmds_encoder.vhd, dv_syncgen.vhd (reusable DVI/TMDS VHDL core)
• Tests: none found
• Notes: “Playground for ULX3S video”; no README; “fer” board_rev suggests a university (FER Zagreb) board variant.

greatscottgadgets__amalthea

• Functions: dsp-sdr, radio-rx, dsp, usb-device
• ULX3S build: amalthea/gateware/{radio,demod,fft,device,stream}.py - not ULX3S; the ECP5 board/platform class itself is NOT in this repo, see notes (LPF: Amalthea rev0 (ECP5 + AT86RF215 + USB3343, hardware/rev0/*; designed for use with LUNA per README))
• Reuse: amalthea/gateware/demod.py: CORDICDemod (CORDIC I/Q->amplitude/frequency/phase demodulator), pure Amaranth, portable; amalthea/gateware/fft.py: FFT/Butterfly/AddressGenerator/TwiddleFactors (radix-2 fixed-point FFT, bit-reversed addressing), pure Amaranth, portable; amalthea/gateware/types/{complex,fixed_point}.py: Q fixed-point + Complex types, portable. radio.py IQReceiver uses ECP5-only DELAYG/IDDRX1F primitives - needs re-targeting elsewhere.
• Tests: dirs: ./tests; 3 tb/test files
• Notes: Stale: last commit 2023-02-07 (45 stars per .claude data/pages rf/dsp survey, 2026-09-28). No board/platform file in this repo: it calls luna.gateware.platform.get_appropriate_platform(); grepping the already-cloned greatscottgadgets__luna clone for ‘amalthea’ found no dedicated Amalthea platform class, so LUNA’s generic platform selection is used. CI runs ‘poetry run pytest’ (.github/workflows/test.yml).

greatscottgadgets__cynthion

• Functions: usb-device, NEW:usb-analyzer, soc-cpu, hyperram, flash-spi, uart, gpio, wishbone-bus, jtag
• ULX3S build: cynthion/python/Makefile (targets: analyzer, facedancer, selftest -> python -m cynthion.gateware.<name>.top --output build/<name>.bit); platform: cynthion/python/src/gateware/platform/cynthion_r1_4.py (current rev; Amaranth Resource pins, no .lpf) (LPF: Cynthion r0.1..r1.4 (Amaranth classes CynthionPlatformRev0D1..Rev1D4 in cynthion_r0_1.py..cynthion_r1_4.py; pins as Amaranth Resource()s, no .lpf file))
• Reuse: gateware/analyzer/ (USB analyzer used by Packetry: analyzer.py USBAnalyzer capture engine + event_detection.py + speed_detection.py + fifo.py, portable Amaranth/LUNA, no ECP5 primitives of its own); gateware/facedancer/ (Moondancer SoC: VexRiscv CPU from luna_soc + HyperRAM/flash/UART/timer/USB2 peripherals via luna_soc.gateware.core, wishbone/CSR fabric via amaranth_soc); gateware/selftest/gateware.py (drives luna.gateware.interface.psram.HyperRAMPHY/Interface + JTAGRegisterInterface + ULPIRegisterWindow - reuses LUNA’s HyperRAM/JTAG cores, no own controller); gateware/platform/cynthion_r*.py (13 board-rev Amaranth platform classes, the reference pinout for any Cynthion design).
• Tests: dirs: ./firmware/moondancer/test ./cynthion/python/tests;7 tb/test files
• Notes: Verified from source. Last commit 2026-05-22. 60MHz oscillator on all board revs (clk_60MHz). No git submodules. Repo also ships extensive host-side Python (commands/, interfaces/gpio.py+led.py) and Rust MCU firmware (moondancer, smolusb, libgreat, ladybug) - out of scope per brief, mention only. selftest gateware exercises JTAG (luna JTAGRegisterInterface) and HyperRAM (luna HyperRAMPHY/Interface) but implements neither controller itself.

greatscottgadgets__cynthion-uac

• Functions: usb-device, dsp, synth-audio
• ULX3S build: uac/top.py (python -m uac.top, per README); no local platform/lpf, relies on the installed cynthion package (LPF: Cynthion (depends on the external cynthion package for the platform; none bundled))
• Reuse: uac/uac2.py (full USBAudioClass2Device, portable Amaranth); uac/nco.py + dsp.py (NCO/sine-LUT synth); uac/dac.py (adapted from the Glasgow Interface Explorer audio applet, ISC-style notice, not BSD-3); uac/clockgen.py (USB feedback-endpoint clock recovery).
• Tests: none found
• Notes: Verified from source. Last commit 2025-07-15. Clock domains fast=240/sync=120/usb=60 MHz (uac/top.py). Talk slides bundled (slides/) - not gateware. Purely internal audio synth (NCO sine LUT) streamed as UAC2; no I2S/external DAC pins are driven despite the audio-digital function assignment.

greatscottgadgets__hackrf

• Functions: dsp-sdr, radio-rx, radio-tx, dsp, adc
• ULX3S build: firmware/fpga/board.py (PralinePlatform), firmware/fpga/build.py, firmware/fpga/top/{standard,half_precision,ext_precision_rx,ext_precision_tx}.py (LPF: HackRF Pro / ‘Praline’ custom board (firmware/fpga/board.py); not ULX3S)
• Reuse: firmware/fpga/dsp/{nco.py,mixer.py,cic.py,fir.py,fir_mac16.py,dc_block.py,quarter_shift.py}: Amaranth CICInterpolator/Decimator, HalfBandDecimator/Interpolator FIR (plain and SB_MAC16-accelerated), 1/8-wave-LUT NCO, complex ComplexMultiplier mixer, DC blocker; unit-tested (firmware/fpga/test/test_{cic,fir,fir_mac16,mixer,fixed}.py, self-checking numpy reference models); dsp/fir_mac16.py + dsp/sb_mac16.py instantiate the iCE40 SB_MAC16 DSP primitive directly - needs porting to ECP5 MULT18X18D to reuse on ULX3S
• Tests: dirs: ./hardware/test ./firmware/fpga/test;10 tb/test files
• Notes: Last commit 2026-09-17 (git log -1, repo-wide and for firmware/fpga). MAX586x ADC/DAC AFE clocked at 40MHz (board.py Clock(40e6) on afe_clk); receive chain is DC-block -> quarter-shift -> 5 cascaded half-band FIR decimators (top/standard.py). Submodules firmware/libopencm3 and hardware/gsg-kicad-lib NOT fetched (MCU firmware / hardware only, out of scope per task).

greatscottgadgets__luna

• Functions: usb-device, usb-host, NEW:usb-analyzer, spi, i2c, jtag, uart, flash-spi
• ULX3S build: examples/blinky_verilog/Makefile, blinky.v, blinky.lpf (generic ECP5 sanity example); real board pin defs live in the separate greatscottgadgets/luna-boards repo (not in this clone), selected via LUNA_PLATFORM env var (examples/blinky/blinky.py: top_level_cli) (LPF: platform-agnostic Amaranth framework; concrete boards (e.g. Cynthion LFE5U-12F) defined externally in greatscottgadgets/luna-boards (not ULX3S); examples/blinky_verilog targets a generic ECP5-25F/CABGA256 board (not ULX3S))
• Reuse: luna/gateware/usb/usb2/ (USB2 device stack: control/descriptor/device/endpoint/packet/request/reset/transfer.py, PHY-agnostic via ULPI/UTMI); usb/usb3/ (USB3 SuperSpeed link/protocol/physical, PIPE-based); interface/ulpi.py+utmi.py (PHY cores); interface/gateware_phy/+serdes_phy/ (soft USB3 PIPE PHY on FPGA SERDES, vendor-specific e.g. ECP5 DCU); interface/psram.py, spi.py, i2c.py, jtag.py, flash.py, uart.py (portable)
• Tests: dirs: ./luna/gateware/test ./tests;28 tb/test files;tools: cocotb
• Notes: Verified from source. Last commit 2026-08-19. No board LPF/pin defs bundled (see luna-boards, not cloned here). CI (simulate.yml, Jenkinsfile) runs the Amaranth-sim unittest suite via pdm run test = python -m unittest discover -t . -s tests -v (pyproject.toml), not a Makefile, so make_tests is empty per brief (scanner: none found). scan_tests.sh’s cocotb hit is a false positive (docstring in vendored test/contrib/usb_packet.py); real harness is amaranth.sim.Simulator (test/utils.py).

greatscottgadgets__luna-soc

• Functions: soc-cpu, usb-device, flash-spi, uart, timer, wishbone-bus, bus-fabric
• ULX3S build: examples/hello-c/top.py + Makefile (python top.py --dry-run --output top.bit; also has an unused load-ulx3s target: openFPGALoader --board ulx3s); examples/hello-rust/ mirrors it in Rust (LPF: Cynthion (via provider/cynthion.py + the external cynthion package’s platform, not bundled here); framework is otherwise board-agnostic)
• Reuse: luna_soc/gateware/cpu/{ic.py,minerva.py,vexriscv.py} (Amaranth wrappers for InterruptController/Minerva/VexRiscv CPUs); cpu/verilog/vexriscv/*.v (SpinalHDL-generated VexRiscv variants incl. vexriscv_cynthion.v, vexriscv_cynthion+jtag.v - generic Verilog, no ECP5 primitives); core/{uart,timer,blockram,spiflash,usb2}/ (Wishbone/CSR peripheral cores); provider/cynthion.py (GPIOProvider + Cynthion-specific SoC wiring).
• Tests: none found
• Notes: Verified from source. Last commit 2025-05-19. 60MHz sync domain in examples (CLOCK_FREQUENCIES_MHZ). No submodules. examples/hello-c/Makefile has an unused load-ulx3s target (openFPGALoader –board ulx3s) though no ULX3S LUNA_PLATFORM is bundled anywhere in this repo - likely dead/aspirational.

gregdavill__luna-usb-serial-acm

• Functions: usb-device, soc-cpu
• ULX3S build: ./ (build_verilog.py -> verilog/LunaUSBSerialDevice.v; USBSerialDevice.py migen/LiteX stream wrapper) (LPF: no board-specific constraints; only board reference is idProduct string “ButterStick r1.0 ACM” in build_verilog.py (not ULX3S))
• Reuse: verilog/LunaUSBSerialDevice.v (self-contained generated Amaranth/LUNA ACM core) + USBSerialDevice.py (migen/LiteX stream wrapper) - portable to any LiteX SoC with a ULPI USB PHY, e.g. a ULX3S+ULPI daughterboard
• Tests: none found
• Notes: Verified: BSD-2-Clause LICENSE and file headers. No LPF/constraints, no nextpnr/ecppack step - pure IP-core generator (Amaranth->Verilog) meant for LiteX SoC integration elsewhere, not a standalone FPGA project. verilog/LunaUSBSerialDevice.v is machine-generated, not hand-written RTL.

gtjennings1__hyperbus

• Functions: psram, soc-cpu, uart, flash-spi, board-hw, pcb
• ULX3S build: icestorm/hyperram.sh (+ riscv32/hardware/pinout.pcf) builds the RISC-V+HyperRAM SoC; standalone/hbc.v + hbc_io.v is the bare controller; sim/hbc_tb.v testbench (LPF: UPduino (not ULX3S))
• Reuse: standalone/hbc.v + standalone/hbc_io.v: self-contained HyperRAM/HyperBus controller in plain Verilog, no iCE40 primitives observed, most reusable piece here
• Tests: dirs: ./sim;1 tb/test files
• Notes: bitstreams/ ships prebuilt hardware.bin/firmware.bin; PLL is Radiant-generated (radiant/pll/, iCE40-specific), so the RISC-V SoC top is not portable as-is; riscv32/hardware/zpicorv32.v is a vendored copy of picorv32 (ISC, C. Wolf), not a submodule

guztech__ulx3s-nmigen-examples

• Functions: video-dvi, oled-lcd, examples, hdl-language
• ULX3S build: dvi/top_vgatest.py, oled/top_oled_vga.py (uses nmigen_boards ULX3S_*F_Platform classes) (LPF: n/a (no LPF in-repo; pin defs come from nmigen-boards package))
• Reuse: top_vgatest.py DVI/TMDS encoder, oled_vga.py OLED+VGA combo example
• Tests: none found
• Notes: no LPF/bitstream committed (relies on external nmigen-boards package for board def); small but genuine example repo

hanseo03__ulx3s-custom-riscv-cpu

• Functions: soc-cpu, uart, esp32
• ULX3S build: top/top_custom.v (+ top/top_led_test.v) with src/soc.v, src/cpu_pipe.v etc., ulx3s_12k.lpf (LPF: ulx3s_12k.lpf (Korean-commented, custom ESP32 wifi_gpio0/wifi_en pin overrides vs. stock ULX3S lpf))
• Reuse: src/cpu_pipe.v + src/forward.v + src/hazard.v (5-stage pipelined RV32I with forwarding/hazard unit), firmware/os_kernel.c (minimal cooperative multitask kernel)
• Tests: dirs: ./test ./tb;2 tb/test files;tools: iverilog
• Notes: Windows-only .bat build scripts (no Linux Makefile for the FPGA flow); README/LICENSE absent; ships prebuilt .bit/.config/.json and simulation .vcd dumps

hanseo03__ulx3s-vexriscv-soc

• Functions: soc-cpu, uart, esp32
• ULX3S build: repo root (top_vex.v, attosoc_vex.v, VexRiscv.v, ulx3s_12k.lpf) (LPF: ulx3s_12k.lpf)
• Reuse: attosoc_vex.v (AttoSoC-style wrapper around VexRiscv), GenMyVexRiscv.scala (SpinalHDL VexRiscv config generator)
• Tests: none found
• Notes: Windows-only .bat build scripts; VexRiscv.v itself is generated/vendored, not authored here; no README/LICENSE

hariharan6307-coder__verilog-goertzel-audio-visualizer

• Functions: dsp, NEW:goertzel
• ULX3S build: no Makefile/.pcf/.lpf; apio.ini (board=Soan-Papdi, top-module=main); top-level is visualiser_core.v (LPF: unknown/none (apio.ini board=”Soan-Papdi” is fictitious; not ULX3S))
• Reuse: goertzel.v/spectrum.v/peak_hold.v/bar_scaler.v: 8-band parallel Goertzel IIR detector (100 Hz-12.8 kHz bands), Q2.14 coefficients, log2 bar scaler; plain Verilog, no vendor primitives, portable to any FPGA including ECP5
• Tests: 5 tb/test files
• Notes: Last commit 2026-07-31. apio.ini board=”Soan-Papdi” is not a real apio board and no .pcf/.lpf is present, so the iCE40/UP5K target guessed by the survey is unverified from this clone; the design itself is plain portable Verilog. No LICENSE.

harrowm__mackerel_030f

• Functions: cpu-retro, sdram, uart, spi
• ULX3S build: pld/mackerel-030f/Makefile, pld/mackerel-030f/ulx3s_v20.lpf, pld/mackerel-030f/mackerel_030f.v (LPF: ULX3S-85F (pld/mackerel-030f/ulx3s_v20.lpf))
• Reuse: pld/mackerel-030f/{sdram_adapter.v,uart.v,spi.v}: own glue/peripherals, portable Verilog; the actual MC68030 core (MH030) and FPU (mh882) are separate GitHub repos (harrowm/MH030, harrowm/mh882), fetched by cores/get_cores.sh – NOT present in this collection, so no core files can be cited here
• Tests: dirs: ./pld/mackerel-030f/sim;1 tb/test files
• Notes: Last commit 2026-09-23. cores/get_cores.sh fetches MH030/MH882/uart16550 by sparse git clone; NONE of them are present in this clone (only the script itself exists under cores/), so the build as committed cannot be reproduced from this repo alone. plan.md documents two real synthesis-flow issues found and fixed, and a benign RTL-level combinational loop diagnosed during ULX3S bring-up.

hassan2203__system-on-chip-soc-design-and-verification

• Functions: soc-cpu, education
• ULX3S build: constraints_ulx3s_onboard.lpf + build_wishbone_ulx3s.sh/.bat (reuses the same top.v/*.v sources as the Colorlight i5 build) (LPF: constraints_ulx3s_onboard.lpf (also ships constraints_colorlight_i5.lpf and an alternate-header variant))
• Reuse: wb_interconnect.v, wb_ram.v/wb_rom.v/wb_led.v (small reusable Wishbone peripheral set)
• Tests: 1 tb/test files
• Notes: student/learning project (README centers on Colorlight i5); ULX3S is a secondary supported board; several backup/before-debug .v files left in repo root

hdl4fpga__hdl4fpga

• Functions: video-dvi, sdram, adc, uart, usb-device, usb-host, ethernet, oled-lcd, dsp-sdr, debug-instrument
• ULX3S build: boards/ULX3S/ (apps: graphics, scopeio, ser_debug) (LPF: apps.lpf (v2/v3.0))
• Reuse: library/sdram, ecp5 phys, video/tmds, usb/ dev+host, mii/ full eth stack, scope/
• Tests: dirs: ./boards/ml50x/testbenches ./boards/ULX3S/testbenches ./boards/arty/testbenches ./boards/ULX4M_LS/testbenches ./boards/orangecrab/testbenches;12 tb/test files
• Notes: Diamond only; active 2025

heichips__heichips25-template

• Functions: education, board-hw
• ULX3S build: fpga/ulx3s/{ulx3s_top.sv,pll40m.sv,ulx3s_v20.lpf} (LPF: fpga/ulx3s/ulx3s_v20.lpf)
• Reuse: src/ - the hackathon’s user-macro template (left blank for participants to fill in); fpga/ulx3s/{ulx3s_top.sv,pll40m.sv} - a reusable ULX3S board-wrapper/PLL pattern for future ASIC-macro FPGA bring-up templates
• Tests: dirs: ./tb;tools: cocotb
• Notes: Last commit 2026-03-01. Template repo (per-team designs not filled in here); ULX3S is one of six FPGA emulation targets provided alongside the ASIC tapeout flow.

hexagon5un__hackaday_supercon_2019_logic_noise_fpga_workshop

• Functions: synth-audio, audio-dac, education, gpio, constraints
• ULX3S build: 004_organ/Makefile (includes ../includes/global_makefile), 004_organ/top.v + single_pitch_oscillator.v, includes/had19_proto3.lpf (also proto1/proto2 LPF variants) (LPF: Hackaday Supercon 2019 badge (hadbadge) proto1/proto2/proto3 (not ULX3S))
• Reuse: 102_gonna_need_a_better_oscillator/oscillator.v (24-bit NCO square-wave oscillator, plain Verilog, portable), 103_more_musical/pitches.v (scale-degree-to-counter_top lookup table, portable), 104_loop_register/loop_register.v (step-sequencer loop register, portable) - no ECP5 primitives used
• Tests: none found
• Notes: Last commit 2019-11-20 (git log). Cumulative projects 001-005 (intro) and 101-105 (organ/synth); stock_badge/ ships prebuilt soc.bit+ipl.bin (badge base firmware), not source. Global Makefile targets 45k CABGA381 @38.8MHz flash freq; three LPF variants (proto1/2/3) are badge hardware revisions. Same badge board as Spritetm/hadbadge2019_fpgasoc (already catalogued).

hoglet67__ice40atom

• Functions: retro-computer, video-composite, synth-audio, ps2, spi, constraints
• ULX3S build: blackice/{blackice.pcf,build.sh} and blackice2/{blackice.pcf,build.sh} (TOP=atom, src/atom.v); Ice40Atom.core (FuseSoC) lists same fileset; no ULX3S/ECP5 support (LPF: BlackIce / BlackIce II (iCE40 HX4K, not ULX3S))
• Reuse: src/cpu.v: standalone 6502 core by Arlet Ottens, portable structural Verilog, reusable on any FPGA; src/sid/sid_6581.v: full SID 6581 audio-synth core (ported, filter TODO), reusable audio block; src/mc6847.v: MC6847 video display generator; build uses -Duse_sb_io define so SB_IO is instantiated conditionally - check before an ECP5 port
• Tests: 1 tb/test files;tools: iverilog
• Notes: Last commit 2019-06-01; release.sh present (tagged releases); no submodules; sibling project to hoglet67/Ice40Beeb, shares src/cpu.v and blackice/blackice2 build scripts

hoglet67__ice40beeb

• Functions: retro-computer, video-vga, ps2, synth-audio, adc, spi, constraints
• ULX3S build: blackice/{blackice.pcf,build.sh} and blackice2/{blackice.pcf,build.sh} (TOP=beeb, src/beeb.v); no ULX3S/ECP5 support (LPF: BlackIce / BlackIce II (iCE40 HX4K, not ULX3S))
• Reuse: src/cpu.v: same Arlet Ottens 6502 core as Ice40Atom, portable; src/mist_scandoubler.v: composite/RGB-to-VGA scandoubler vendored from the MiST project (GPLv3), reusable output stage for any retro-video core; src/mc6845.v, src/saa5050.v (teletext char gen), src/sn76489.v (PSG sound): standalone peripheral cores; VGA out on PmodVGA pins (blackice.pcf red/green/blue/hsync/vsync)
• Tests: 1 tb/test files;tools: iverilog
• Notes: Last commit 2017-12-18 (oldest of the two hoglet67 repos); no submodules; sibling project to Ice40Atom, shares src/cpu.v and blackice/blackice2 build scripts

hsa-ees__piconut

• Functions: soc-cpu, linux, uart, adc, rtc-power, education, toolchain, ml-accelerator
• ULX3S build: boards/ulx3s/ (ulx3s.lpf, piconut-board.mk) + per-system systems/*/boards/ulx3s/ (LPF: boards/ulx3s/ulx3s.lpf (also boards/orangecrab/orangecrab.lpf for 2nd target board))
• Reuse: systems/ tree: many ready SoC configs (demo_sdram, demo_video, demo_audio, demo_ai, demo_clint, refdesign, playnut) reusable as SoC templates
• Tests: dirs: ./systems/refdesign_c_soft_debugger/test ./sw/verification;tools: iverilog
• Notes: Large academic SystemC-modeled RISC-V project with Sphinx manual (80 svg figures); supports Linux/FreeRTOS and AI-accelerator extension work

htfab__asicle2

• Functions: video-vga, retro-arcade, gpio
• ULX3S build: fpga/ulx3s/{apio.ini,build.sh,fpga_top.sv,ulx3s_custom.lpf} (LPF: fpga/ulx3s/ulx3s_custom.lpf)
• Reuse: src/{project,game_board,game_feedback,game_logic,game_top,input_,qspi_,vga_*}.sv: complete Wordle game logic + VGA renderer + QSPI/gamepad input handling, portable SV; wrapped per-board by fpga/{ulx3s,pico-ice,basys3}/fpga_top.sv.
• Tests: dirs: ./test;tools: cocotb
• Notes: Last commit 2025-10-30. Tiny Tapeout ttsky25b (Sky130 ASIC) is the primary target; ULX3S/Pico-Ice/Basys3 are secondary FPGA ports, each with a real, complete, board-specific build script and constraint file present and runnable as cloned.

ibm2030__ibm2030

• Functions: retro-computer, video-vga, gpio, constraints
• ULX3S build: no ULX3S/ECP5 build; board files are digilentSP3.ucf + IBM2030.xise (Xilinx ISE project) (LPF: Digilent Spartan-3 Board (S3BOARD, XC3S1000), not ULX3S; README notes UCF can be edited to retarget other boards)
• Reuse: ibm2030-vga.vhd: self-contained 640x60 8-colour VGA output (vga_controller_640_60.vhd), portable logic, would need pin remap for ECP5/ULX3S; panel_LEDs.vhd/panel_Switches.vhd: simple I/O scanning, portable
• Tests: none found
• Notes: Last commit 2025-09-24 (repo still maintained). Author states 5+ years of varied-quality VHDL; ccros.vhd microcode files (ccros20100715/20120318/20210925.txt) track microcode revisions. No submodules.

icebreaker-fpga__icebreaker-verilog-examples

• Functions: board-hw, video-dvi, uart, synth-audio, led-matrix
• ULX3S build: NO ULX3S (LPF: iCEBreaker v1.0 / iCEBreaker-bitsy (not ULX3S, iCE40))
• Reuse: icebreaker/dvi-24bit/{vga_core.v,vga_timing.v} portable VGA/DVI timing gen (no iCE40 primitives, ported from a Xilinx Spartan3 design per README); icebreaker/pll_uart/{uart_rx.v,uart_tx.v,uart_baud_tick_gen.v} portable UART
• Tests: 2 tb/test files;tools: iverilog
• Notes: Small independent per-board examples, not a SoC. dvi-*bit target Black Mesa Labs HDMI Pmods at 800x600/40MHz. sb_rgba_blink and pll_uart use iCE40-only SB_RGBA_DRV/SB_PLL40; rest is plain Verilog, easily portable

icebreaker-fpga__icebreaker-workshop

• Functions: board-hw, education
• ULX3S build: NO ULX3S (LPF: iCEBreaker v1.0 (not ULX3S, iCE40))
• Reuse: stopwatch/solution/stopwatch.v and stopwatch-dual/solution/stopwatch.v: plain counter/7-seg BCD driver pattern, no iCE40 primitives used, directly portable to ECP5/ULX3S with a new pin constraint file
• Tests: tools: iverilog
• Notes: Workshop targets the iCEBreaker 7-Segment Pmod; guide PDFs (stopwatch/icebreaker-fpga-stopwatch-workshop.pdf) explain the exercise. Makefile has iverilog _tb rules but no actual testbench source files exist in the tree

icebreaker-fpga__icetwang

• Functions: board-hw, soc-cpu, usb-device, led-matrix, flash-spi, game-controller
• ULX3S build: NO ULX3S (LPF: iCEBreaker-bitsy v1 + custom iCEtwang ctrl-v0.1/pole-v0.1 PCBs (not ULX3S, iCE40))
• Reuse: soc/cores/{no2usb,no2ice40,no2misc} (Submodules fetched 2026-09-27: no2usb@0507086, no2ice40@e2a0c69, no2misc@7096e0c) - Wishbone USB device stack, PWM/PDM cores portable; ice40_rgb_wb.v/ice40_spram_gen.v wrap iCE40-only macros
• Tests: dirs: ./sim ./soc/ice-twang/sim;4 tb/test files
• Notes: soc/build (no2build) and hardware/lib/pkl submodules declared but not fetched. sysmgr.v uses SB_PLL40_2F_CORE/PAD, several rtl files use SB_IO, no2ice40 uses SB_RGBA_DRV/SB_SPRAM256KA - all iCE40-only, need EHXPLLL/DP16KD to port. picorv32.v core is portable

im-tomu__foboot

• Functions: bootloader, usb-device, soc-cpu, flash-spi
• ULX3S build: not ULX3S/ECP5 (iCE40 UP5K Fomu only); hw/foboot-bitstream.py, hw/rtl/VexRiscv_Fomu*.v, sw/src/main.c (LPF: Fomu evt/pvt/hacker (iCE40 UP5K, not ULX3S))
• Reuse: sw/src/main.c nerve_pinch(): touch-pad (TOUCH0/TOUCH2 loopback) forced-DFU detection, Fomu-specific (no button on this board); sw/src/dfu.c+usb-desc.c: DFU class impl, VID:PID 0x1209:0x5bf0 (sw/include/usb-desc.h:60-61); hw/deps/valentyusb eptri.TriEndpointInterface: Migen-generated USB peripheral for a LiteX SoC, not a drop-in RTL core - needs the LiteX/Migen toolchain
• Tests: dirs: ./hw/tests;tools: cocotb
• Notes: Last commit 2022-12-31 (git log). USB core is ValentyUSB’s eptri.TriEndpointInterface on a LiteX VexRiscv SoC (hw/foboot-bitstream.py:31,264,320), i.e. software-generated RTL, not hand-written. Submodule hw/deps/valentyusb fetched (submodules.tsv); hw/deps/{migen,litex,litescope,litedram,litex-boards,spibone,pythondata-software-compiler_rt} deliberately not fetched - software frameworks, not gateware. Flash layout per doc/FLASHLAYOUT.md: bootloader at 0xa0 (multiboot header)/SB_WARMBOOT image 0; user app (FBM_OFFSET) at 0x01a000; further SB_WARMBOOT images at 0x026800/0x040000/0x048000; dfu-util with no DfuSe address defaults to writing 0x040000 (README.md:99).

im-tomu__fomu-workshop

• Functions: education, board-hw, soc-cpu, usb-device
• ULX3S build: hdl/verilog/blink/ (Makefile, pcf/fomu-*.pcf via hdl/board.mk); hdl/vhdl/blink/, hdl/mixed/blink/; litex/workshop.py (LiteX SoC) (LPF: Fomu evt1/evt2/evt3/hacker/pvt (not ULX3S))
• Reuse: hdl/verilog/blink/blink.v and hdl/board.mk per-revision pin/flag-select Makefile idiom: teaching examples, reusable as a pattern more than as IP
• Tests: none found
• Notes: teaching material, not a reusable core; blink uses iCE40 hard macro SB_RGBA_DRV (no ECP5 equivalent); LiteX SoC uses ValentyUSB (im-tomu/valentyusb submodule, not fetched; different fork catalogued under orangecrab-fpga__orangecrab-examples); LiteX/migen/litedram submodules skipped

intergalaktik__ulx4m-ls

• Functions: board-hw, constraints, ulx4m, camera, video-dvi, sdcard, ethernet, jtag, bootloader, serdes-pcie-sata
• ULX3S build: NO ULX3S board itself — this IS the ULX4M-LS board; doc/constraints/ulx4m_ls_v004.lpf (latest constraint file); no top .v/Makefile gateware in the repo (LPF: doc/constraints/ulx4m_ls_v004.lpf (latest); prototypes ulx4m-ld_v001.lpf, ulx4m-ld_v002.lpf, ulx4m_ls_v003.lpf, ulx4m_v002.lpf, ulx4m_v01.lpf)
• Reuse: doc/constraints/*.lpf pin maps for future ULX4M-LS gateware ports; no HDL to reuse (PCB-only repo)
• Tests: none found
• Notes: last commit 2025-08-06; ULX3S/ULX2S successor (NLnet-funded); 2x CSI camera, 2x DSI display, true+fake diff GPDI, 4-bit SD, optional SerDes (PCIe 1x / radio experiments, ECP5-5G variant only), Ethernet LAN8720A, 32MB SDRAM IS42S16160G-7BL, USB bootloader

ipmgroup__fftd

• Functions: dsp, NEW:fft, spi, uart
• ULX3S build: NOT ULX3S; hardware/rtl/fft_top.v (top), hardware/synth/{fft_top.pcf,icezero.pcf}, hardware/synth/build_scripts/{synth.sh,pnr.sh,pack.sh} (LPF: ICEZero (TE0876-03) Raspberry Pi HAT (pinout.md; hardware/synth/icezero.pcf), not ULX3S)
• Reuse: hardware/rtl/fft_core.v (radix-2 DIT FFT core, N parametric via N_LOG2, WIDTH=16, twiddle_rom.v, block-floating-point exponent output) + fft_top.v (1024-pt instance, SPI protocol, AS6C4008 SRAM buffer); iCE40 SB_RAM40_4K inferred via (* syn_ramstyle = "block_ram" *), port to ECP5 EBR to reuse
• Tests: dirs: ./hardware/rtl/tests ./hardware/sim;15 tb/test files;tools: verilator,iverilog
• Notes: Last commit 2026-06-04 (git log). No submodules. README describes software/{kernel_driver,lib,python,utils} (Linux UIO driver + libfft.so) but none of these dirs exist in this shallow clone - aspirational gap. Root file hw (FFT_LGWIDTH=6->64pt) is a stale leftover from an earlier ZipCPU dblclockfft-based design, superseded by the hand-written 1024-pt fft_core.v.

ironsteel__nes_ecp5

• Functions: retro-console, video-dvi, sdram, sdcard, esp32, usb-host
• ULX3S build: root (LPF: ulx3s_v20.lpf)
• Reuse: same
• Tests: none found
• Notes: README 2026-01 WARNING: OSD load broken; prefer emard fork

jadephilipoom__ulx3s-experiments

• Functions: led-matrix, board-hw, examples, NEW:riscv-learning
• ULX3S build: repo root (top.v, top.ys, ulx3s_v20.lpf, Makefile, tests/double.s) (LPF: ulx3s_v20.lpf)
• Reuse: top.v (small LED-driving top-level, learning scaffold)
• Tests: dirs: ./tests
• Notes: author-labeled learning/experiment repo; no README beyond build script comments

jamchamb__cojiro

• Functions: uart, usb-host, joybus-io
• ULX3S build: top-level dir; Makefile targets top_pad (top.v), top_snap (top_snapstation.v), top_uart_host (top_uart_host.v); data/icebreaker.pcf (LPF: iCEBreaker, revision unspecified (not ULX3S, iCE40 UP5K))
• Reuse: osdvu/uart.v (submodule, MIT, cyrozap): standalone UART core with testbench tb_uart.v, portable to ECP5; n64_sender.v/n64_receiver.v/datacrc_8wide.v: bit-banged JoyBus one-wire protocol logic, portable but timed off 12 MHz
• Tests: 1 tb/test files;tools: iverilog
• Notes: Submodules fetched 2026-09-27: osdvu@276dd06. cojiro’s own code has no license file. JoyBus one-wire timing is derived from the Makefile’s FREQ=12 constant; would need re-tuning for ULX3S 25 MHz clock. software/*.py talk to the board over USB-serial (uart_host.py, accessories/).

jamesbowman__swapforth

• Functions: soc-cpu, uart, NEW:forth, constraints
• ULX3S build: j1a/icestorm/{j1a8k.v,uart.v,j1a8k.pcf},../verilog/{j1.v,stack2.v} (Makefile target j1a8k.bin); no ULX3S support, HX8K-only iCE40 PCF (LPF: iCE40 HX8K Breakout / iCEstick class boards (not ULX3S); no PCB of its own)
• Reuse: j1a/verilog/{j1.v,stack2.v}: tiny 16-bit J1 stack-CPU core, portable structural Verilog; j1a/icestorm/uart.v: simple 115200 baud UART (12MHz CLKFREQ hardcoded); j1a8k.v/j1a.v top wrap SB_RAM40_4K + SB_IO(PIN_TYPE 6’b1001_01) primitives - must be ported to ECP5 DP16KD/IO primitives
• Tests: 1 tb/test files;tools: verilator,iverilog
• Notes: Last commit 2023-09-29 (repo), j1a/icestorm files unchanged for years; 12 MHz UART clock; mostly a Forth language project, FPGA CPU (J1a/J4a) is a small side deliverable; no submodules

jamesrosssharp__1_bit_am

• Functions: radio-tx, radio-rx, dsp-sdr, multi-board, board-hw, constraints
• ULX3S build: impl/ulx3s/ (top.v, ulx3s_v316.lpf, Makefile: yosys+nextpnr-ecp5+ecppack) (LPF: ulx3s_v316.lpf)
• Reuse: pll/ecp5pll.sv PLL generator (shared between ulx3s/ice40 impls)
• Tests: dirs: ./test;tools: iverilog
• Notes: personal hobby/experiment repo with external wiring diagram; also has an ice40 target

jamesrosssharp__ulx3s_mixer_pcb

• Functions: radio-rx, dsp-sdr, board-hw
• ULX3S build: hdl/impl/ulx3s/ (Makefile, ulx3s_v316.lpf) (LPF: ulx3s_v316.lpf)
• Reuse: hdl/src/mixer.v, am_demod.v, fm_demod.v, dpll.v, bandpass_19khz.v (DSP/SDR building blocks)
• Tests: dirs: ./hdl/test;tools: iverilog
• Notes: ulx3s_mixer/ is a separate KiCad PMOD mixer front-end board with full gerbers/BOM; HDL side is a standalone SDR receiver chain.

jamon__jspcpu

• Functions: education, soc-cpu, logic-analyzer, board-hw, constraints
• ULX3S build: root (Makefile hardware.* targets, ulx3s.lpf); many per-module dirs also carry their own flash.sh using Windows-style .apio paths (LPF: ulx3s.lpf)
• Reuse: alu/, register_gp/, register_addr/, control/, bus/ – individually testable CPU datapath modules
• Tests: 11 tb/test files;tools: iverilog
• Notes: “Work in Progress”; per-module flash.sh scripts hardcode Windows paths (C:/Users/ms/.apio/…), suggesting dev-machine-specific and not portable as-is

jderobot__fpga-robotics

• Functions: camera, video-input, board-hw, constraints, examples, education
• ULX3S build: phys_fpga/ulx3s/apio/*/ (9 apio.ini + ulx3s_v20.lpf per-demo dirs: OV7670 RGB/YUV/colorfilter/centroid) (LPF: ulx3s_v20.lpf (each demo dir))
• Reuse: phys_fpga/ulx3s/apio/ov7670_* camera-interfacing blocks (RGB/YUV, color filter, centroid tracking) reusable Icestudio/Verilog IP
• Tests: 2 tb/test files;tools: verilator
• Notes: very large repo with much build-log clutter (355 .log, 141 .bak, 127 .rpt); many near-duplicate demo variants; teaching library, not one product

jeli180__shape-inference-soc

• Functions: soc-cpu, ml-accelerator, uart, sdram, NEW:mlp
• ULX3S build: Makefile (LPF=constraints/ulx3s_v20.lpf, DEVICE=–85k), constraints/ulx3s_v20.lpf, src/top.sv (LPF: ULX3S ECP5-85K/CABGA381 (constraints/ulx3s_v20.lpf))
• Reuse: src/{mac.sv,systolic_array.sv,tensor_controller.sv}: integer MLP systolic accelerator, portable SV, real DP16KD/MULT18X18D usage reported; src/{uart_tower.sv,uart_reciever.sv,uart_transmitter.sv}: credit-based UART framing tower
• Tests: dirs: ./sim ./tb;9 tb/test files;tools: iverilog
• Notes: Last commit 2026-09-09. Real, measured post-route results: 24.65 MHz Fmax at 12.5 MHz configured clock, 23835/83640 TRELLIS_COMB (28%), 128/208 DP16KD (61%), 17/156 MULT18X18D (10%) – see synth_changes/README.md. tb/*.sv testbenches are self-checking via PASS/ERROR $display comparisons against expected values, not wired to a Makefile.

jerry-d__sympl_ieee754-2019_isa

• Functions: soc-cpu, uart
• ULX3S build: SYMPL128_demo_BT/ (bitstream + Tera Term demo assets only; no HDL source, Makefile or LPF present in this clone) (LPF: RADIONA ULX3S -85F (per Quick_Start.txt); no .lpf present in this clone)
• Reuse: none - no source files found in this clone to extract reusable HDL blocks from
• Tests: none found
• Notes: Last commit 2023-12-08. Alpha/evaluation release only (README dated 2021-2023); no synthesizable source in the repo, only demo assets and a non-commercial license. ULX3S target claim is detailed and plausible but unverifiable at the HDL level from this clone.

jlopezr__mini-gpu

• Functions: soc-cpu, gpu, sdram, video-dvi, uart, examples, education
• ULX3S build: numbered stage dirs each with own ulx3s*.lpf, e.g. 21.fpga-cpu-hdmi-alu/, 14.fpga-gpu-ram/ (apio board=ulx3s-85f) (LPF: ulx3s.lpf / ulx3s_v20.lpf (varies per stage))
• Reuse: 21.fpga-cpu-hdmi-alu/ (most complete CPU+HDMI+SDRAM), 12.fpga-gpu/ (SIMT GPU SM), 1.isa/ (MiniISA spec+assembler)
• Tests: dirs: ./17.fpga-gpu-ram-v2/sim ./14.fpga-gpu-ram/sim ./22.fpga-gpu-bl8/sim;208 tb/test files
• Notes: Large (41MB), heavily documented, Spanish-language, staged/progressive repo with detailed timing-closure notes; CLAUDE.md/AGENTS.md present (AI-assisted dev).

joaln27__cordic

• Functions: dsp, radio, led-drivers
• ULX3S build: fpga/ulx3s_top.sv, fpga/ulx3s.lpf, fpga/synth.ps1; fpga/meter/ (hardware-verification harness) (LPF: ULX3S 85F (fpga/ulx3s.lpf))
• Reuse: src/cordic.sv: bit-serial CORDIC core (rotate+vector modes, 20-bit shift-register datapath, 3 full adders, fixed-tap bit-muxing instead of barrel shifters), Apache-2.0, ECP5/any-FPGA portable, no vendor primitives; fpga/meter/: reusable ULX3S CRC-32 hardware-vs-simulation equivalence-check harness pattern
• Tests: dirs: ./test;2 tb/test files;tools: cocotb
• Notes: Last commit 2026-09-25. Verification is five independent layers (exhaustive 65536-angle sim, SymbiYosys k-induction formal proof, FFT spectral test, gate-level sim, and real ULX3S-85F hardware): fpga/meter/ (2026-09-25) reports every output bit for all 128 frequency codes over 2^20 clocks matches simulation bit-exact (389/389 CRC-32 signatures) – among the most rigorously hardware-verified repos in this collection.

joaln27__koti

• Functions: soc-cpu, linux, sdram, sdcard, usb-host, video-dvi, esp32, uart
• ULX3S build: fpga/ulx3s/ (ulx3s.lpf, ulx3s_top.sv) (LPF: fpga/ulx3s/ulx3s.lpf)
• Reuse: src/koti_core.sv (RV32IMA core w/ tlb/icache/dcache/mmu), vendor/ IP (USB HID host, SD-SPI, DVI TX, audio)
• Tests: dirs: ./test;23 tb/test files;tools: cocotb
• Notes: Runs mainline Linux 6.12; substantial well-documented “home computer” project; ULX3S 85F is the sole target board.

john-k__spinose

• Functions: flash-spi, soc-cpu, bootloader
• ULX3S build: spinose.py (root; uses litex_boards.platforms.ulx3s) (LPF: litex_boards ulx3s platform (submodule not fetched, no local .lpf))
• Reuse: flash-12f.sh (12F bitstream conversion script)
• Tests: none found
• Notes: deps/{litex,litex-boards,migen,litedram,valentyusb} are empty git submodules in this shallow clone; ulx3s platform code confirmed via imports/README only

johnazoidberg__ulx3s-espi-analyzer

• Functions: logic-analyzer, uart, board-hw, constraints
• ULX3S build: hdl/espi_sniffer_top.v + proj/constraints/ulx3s_v20_espi.lpf (LPF: proj/constraints/ulx3s_v20_espi.lpf)
• Reuse: hdl/ecp5pll.sv (EMARD’s PLL generator, BSD-licensed), hdl/espi_capture.v + espi_packet_decoder.v eSPI decode pipeline
• Tests: none found
• Notes: well-documented, Nix-flake reproducible build, recently active (pushed 2026-03-08)

johngannon4__riscv-cpu-portfolio

• Functions: soc-cpu, education
• ULX3S build: none - repo contains only README.md and docs/*.md; no RTL, no LPF, no build files ("Why this repo has no RTL" section, README.md) (LPF: unknown (no board file))
• Reuse: none (no source files)
• Tests: none found
• Notes: last commit 2026-09-24. Course policy explicitly withholds source ("Publishing the source would hand future students a solution set"). Reported results (17.56/17.19 MHz Fmax, TRELLIS_COMB/DP16KD/MULT18X18D counts) are unverifiable claims, not checked against any file in this clone.

joshajohnson__ecp5-mini-projects

• Functions: examples, usb-device, uart, hyperram, soc-cpu, led
• ULX3S build: verilog// (Makefile -> verilog/common.mk, ../ecp5-mini_r0.2.lpf); litex/soc-hr/ (ecp5_mini.py, platform/ecp5_mini.py); nmigen/blink/ (LPF: ECP5 Mini r0.1/r0.2 (not ULX3S))
• Reuse: verilog/common/usb/*.v (vendored tinyfpga_bx_usbserial USB CDC core + usb_uart_ecp5.v wrapper, Apache-2.0, needs 48 MHz); verilog/common/{pwm,debounce,seven_segment,clk_div_hz,dfu_reset}.v (small portable helpers); litex/soc-hr/ecp5_mini.py (LiteX SoC using litehyperbus HyperRAM, 8 MB at 0x20000000)
• Tests: dirs: ./verilog/fade/sim ./verilog/usb_serial/sim ./verilog/common/sim ./verilog/wtfpga/sim ./verilog/blink/sim;7 tb/test files;tools: iverilog
• Notes: Small, clean open-flow example set for a 12F CABGA256 board; each Verilog project has an iverilog sim/ testbench. HyperRAM is via LiteX litehyperbus (pins in platform/ecp5_mini.py), not plain Verilog. dfu_reset.v pairs with the had2019-playground bootloader (ecp5-mini branch). Last commit 2021-08-29.

kazkojima__litex-lattice-ecp5-evn

• Functions: ethernet, NEW:serdes-pcie-sata
• ULX3S build: not ULX3S; liteeth/ecp5sgmii.py (SGMII PHY module), litex-boards/lattice_ecp5_evn-sdram-sgmii.patch (board file patch), linux-on-litex-vexriscv/ecp5_evn-sdram-sgmii.patch (SoC target patch); no local Makefile/.pcf, applies against an external litex-boards checkout (LPF: ECP5-5G Evaluation Board + kazkojima/ecp5evn-sdram-addon (SDRAM daughterboard) + kazkojima/dp83867s-sgmii-board (TI DP83867S PHY board); both addon repos external, not cloned here)
• Reuse: liteeth/ecp5sgmii.py – SGMIITX/SGMIIRX/SGMIIECP5: Instance(‘DCUA’, CHX_PROTOCOL=’GBE’) SGMII PHY, reduction of liteeth pcs_1000basex.py + liteiclink serdes_ecp5.py (comment at line 224); portable to any LiteX ECP5-UM board with a SGMII PHY chip, needs the DCU GBE config redone for other rates
• Tests: none found
• Notes: last commit 2021-05-25 (git log -1); README: ‘Everything here is experimental’; console screenshot of linux-on-litex-vexriscv SMP boot shown (images/console-smp.png); no gitmodules

kbeckmann__pergola_projects

• Functions: examples, video-dvi, video-input, uart, crypto, radio-tx, soc-cpu
• ULX3S build: verilog// (Makefile -> verilog/common.mk, pergola_hdmi.lpf); pergola/ (python -m pergola run <applet>, platform/pergola.py) (LPF: Pergola (not ULX3S))
• Reuse: pergola/gateware/tmds.py, vga2dvid.py, dvid2vga.py (nMigen TMDS encode/decode, DVI in and out), gearbox.py, uart.py; verilog/hdmi_passthrough_ddr*/top.v (ECP5 ODDR/IDDR HDMI pass-through, pins need remap)
• Tests: none found
• Notes: Pergola is an ECP5-12F CABGA256 board (pergola-fpga/pergola). nMigen code predates the Amaranth rename, may need porting. Several gateware modules carry unittest/formal tests (python -m unittest -v, pergola/util/test.py), which the path scan does not detect. Last commit 2021-06-23.

kbeckmann__tt08-flame

• Functions: video-dvi, audio-dac, education, constraints
• ULX3S build: ulx3s/top.v, ulx3s/ulx3s_v20.lpf, ulx3s/Makefile (src/tt_um_top.v is the TT ASIC top) (LPF: ULX3S (ulx3s/ulx3s_v20.lpf, DEVICE=85k); primary target is the TT ASIC shuttle (Sky130/GF180, not a board))
• Reuse: ulx3s/{ecp5pll.sv,hdmi.v,top.v}: portable ECP5 HDMI wrapper (hdmi.v borrowed from lawrie/ulx3s_altair_8800, TMDS_encoder, no SB_* primitives); src/{tria.v,voice.v,scale_rom.v,hvsync_gen.v}: portable Verilog-2001 flame/plasma + PDM-voice demo core, board-agnostic
• Tests: dirs: ./test ./web/src/sim;tools: cocotb
• Notes: Last commit 2024-09-06 (git log -1). ULX3S clk_25mhz; ulx3s/Makefile overrides DEVICE to 85k (ulx3s.mk default is 12k). TT ASIC entry for the tinytapeout.com demoscene competition. No submodules.

kbob__icebreaker-candy

• Functions: led-matrix
• ULX3S build: ~25 independent dirs each with own Makefile + shared root icebreaker.pcf, e.g. first-demo/ (Makefile, first-demo.v), munch1/, gradient-pwm/, ws2812/ (+testbench) (LPF: iCEBreaker, revision unspecified (not ULX3S, iCE40 UP5K))
• Reuse: include/led-pwm-gamma.v, led-pdm-gamma.v, led-simple.v: generic technology-independent PWM/PDM LED brightness+gamma drivers; ws2812/ws2812.v (+ws2812_tb.v): portable WS2812 protocol driver with testbench
• Tests: dirs: ./sim;2 tb/test files;tools: iverilog
• Notes: ~25 self-contained single-file demos; README author states “I am an FPGA n00b”. Only gray/ and queue/ have testbenches (iverilog); most examples are untested visual effects. Portable to ULX3S with clock change (12 MHz ext vs 25 MHz) and pin remap; HUB75 panel wiring is ad hoc via PMOD.

kelu124__lit3rick

• Functions: adc, spi, i2c, audio-i2s, dsp-sdr, NEW:ultrasound-pulser, NEW:ultrasound-acquisition, NEW:ultrasound-envelope-dft
• ULX3S build: verilog/src/rtl/top.v (top) + verilog/src/synth.ys (yosys synth_ice40, partial open flow: top+debounce+i2c_slave*+mcp4812+ram_256k+spi_slave+main_fsm only); full design also captured as verilog/radiant/fft_adc/fft_adc.rdf (Lattice Radiant project, device iCE40UP5K-SG48I, P&R already run in impl_1/); no ULX3S/ECP5 support (LPF: lit3rick up5k board (Lattice iCE40UP5K-SG48I) (not ULX3S) - owner’s own single-channel open ultrasound pulse-echo board)
• Reuse: verilog/src/rtl/fft/dft.v + dft_core.v/dft_preproc.v/dft_postproc.v/dft_complex_abs.v/dft_sqrt.v (16-point sliding-window Goertzel-style DFT over 8192 12-bit samples -> 3 frequency bins -> magnitude; code_fourrier/README.md calls it “Fourier (envelope extraction) IP-core”; no vendor primitives, portable); verilog/src/rtl/alaw_coder.v (G.711 A-law 15->8bit compressor per ITU G.191, no vendor primitives); verilog/src/rtl/adc_receiver.v (AD9629 12-bit ADC capture + DC-offset removal, portable); verilog/src/rtl/i2c_slave_axil_master.v (Alex Forencich MIT I2C-slave-to-AXI-lite bridge, same lineage as pifive-verilog-i2c core already catalogued); verilog/src/rtl/spi_slave.v (OpenCores SPI slave); verilog/src/rtl/mcp4812.v (MCP4812 SPI DAC driver, drives TGC gain ramp). iCE40-only: top.v HSOSC (internal ~48MHz osc) and RGB (LED driver) primitives; verilog/src/rtl/ip_cores/ebr_dp.v + sc_fifo.v are Radiant IP-Catalog-generated UP5K EBR dual-port RAM / sync FIFO wrappers, need reimplementing for ECP5 DP16KD.
• Tests: dirs: ./verilog/src/tb;1 tb/test files
• Notes: Last commit 2024-07-13 (git log, matches sources.tsv pin ca4ad98). Repo owner’s own board (kelu124@gmail.com); README says it derives conceptually from echomods and un0rick projects but is not a git fork of either. Clock: internal HSOSC (~48MHz) feeds a Radiant-IP-catalog PLL (pll_adc) generating ADC_REF_CLK for the AD9629BCPZ-65 ADC (up to 65Msps); most internal logic runs on ADC_DCLK. Two parallel captures of the same design: verilog/src/ (hand-written RTL + partial open synth.ys) and verilog/radiant/fft_adc/ (full Radiant project, P&R already completed, bitstream fft_adc_impl_1.bin present). Prebuilt bitstream verilog/lit3_v2.0.bin (101.7K), programmed via a custom RPi-SPI tool (program/utilities/lit3prog, no FTDI/openFPGALoader). No .gitmodules found.

kelu124__un0rick

• Functions: adc, spi, sram, gpio, NEW:ultrasound-pulser, NEW:ultrasound-acquisition
• ULX3S build: usb/verilog/impl/icestorm/run_impl, usb/verilog/src/rtl/top.v (top), usb/verilog/impl/icestorm/un0rick.pcf; also usb/verilog/impl/icecube2/* and vhdl/ (matty_main.vhd, MATTY_Implmnt/) for a VHDL/iCEcube2 flow on the same board (LPF: un0rick v1.0/v1.1 (Lattice iCE40HX4K-TQFP144) (not ULX3S) - owner’s own ultrasound imaging board, un0rick.cc)
• Reuse: usb/verilog/src/rtl/acq.v + acq_buff.v (acquisition sequencer + line buffer; acq_buff.v uses SB_RAM40_4K, iCE40-only, needs ECP5 DP16KD to port), dacctl.v/hvmuxctl.v (pulser/HV-mux + TGC DAC control), csr.v+spi2csr.v (SPI-to-register bridge), ramctl.v/ram_filler.v (external async SRAM ctrl). sys_pll.v (SB_PLL40_2F_CORE) and pll.v/vga_pll.v (SB_PLL40_CORE) are iCE40-only, need ECP5 PLL primitives. src/beh/* are icarus-only non-synthesizable sim models.
• Tests: dirs: ./usb/verilog/sim
• Notes: Last commit 2025-01-19 (git log). Repo owner’s own board (kelu124@gmail.com, un0rick.cc). This clone’s default branch (master) already carries BOTH the Verilog/icestorm flow (usb/verilog) and a VHDL/iCEcube2 flow (vhdl/) for the same chip - the hx-boards-survey.md note about a separate VHDL/iCEcube2 branch is not needed to see the VHDL, it’s on master too. Clock: ICE_CLK pin, run_impl FREQMHZ=12 (12 MHz). No .gitmodules found.

kholia__colorlight-5a-75b

• Functions: board-hw, jtag, uart, dsp-sdr
• ULX3S build: blink/Makefile, blink/blink.v, blink/blink.lpf; dds_ssb_uart/Makefile, dds_ssb_uart/top.v, dds_ssb_uart/dds.lpf (per-example dirs) (LPF: Colorlight 5A-75B v7.0/v8 (LFE5U-25F-6CABGA256) (not ULX3S))
• Reuse: dds_ssb_uart/nco.v (CORDIC NCO/DDS core, derived from drom/NCO, portable); dds_ssb_uart/uart_rx.v + uart_tx.v (simple UART, portable); blink/rst_gen.v (reset generator, portable); top.v EHXPLLL PLL wrapper (25MHz->100MHz) is ECP5-specific, needs reparam for other FPGAs
• Tests: none found
• Notes: Verified from source. Last commit 2026-02-26. Board clock 25MHz ext osc (blink.lpf: clk_i 25MHz). No submodules. Repo mixes source with large prebuilt .bit/.svf/.json bitstreams and .wav audio assets. Six independent example subdirs, each self-contained (own Makefile+LPF); no top-level build.

kost__fujprog

• Functions: programmer-tool, toolchain
• ULX3S build: n/a (host tool, no gateware); talks to ULX3S over FTDI FT231X JTAG/UART from fujprog.c; ulx2s_prep.sh drives ujprog for the ULX2S flow (LPF: ULX2S, ULX3S (README.md); ulx2s_prep.sh flashes ulx2s_8e.jed via ujprog)
• Reuse: fujprog.c: single-file host JTAG bitstream/SVF/img/jed loader + SPI flash programmer + f32c (MIPS/RISCV) binary loader over FTDI; portable host-side code, nothing FPGA-side to reuse
• Tests: none found
• Notes: last commit 2020-11-12 (git log); CI via Travis; historically the standard ULX3S programmer, largely superseded by openFPGALoader per current board docs

kost__ulx3s-ghdl-examples

• Functions: examples, education, audio-dac, esp32, toolchain
• ULX3S build: 01-Basics/*, 02-Audio, 80-Test/10-passthru (LPF: ulx3s.lpf)
• Reuse: passthru.vhdl, debounce.vhdl
• Tests: none found
• Notes: 2020

krishkc5__trng-ring-oscillator

• Functions: crypto, uart, board-hw, logic-analyzer
• ULX3S build: rtl/ (trng_demo.sv top) + ulx3s_v20.lpf (LPF: ulx3s_v20.lpf)
• Reuse: rtl/ring_oscillator.sv, rtl/trng_core.sv (standalone entropy source, board-independent)
• Tests: dirs: ./tb;1 tb/test files;tools: cocotb,verilator
• Notes: Well-documented student/research project; includes report.pdf writeup and statistical plots; sim-first workflow, real HW just a demo wrapper

kulp__tenyr

• Functions: soc-cpu, board-hw, constraints, toolchain, wishbone-bus
• ULX3S build: hw/yosys/{Makefile,ulx3s_v20.lpf,ulx3s_top.v}; 3rdparty/ulx3s (vendored reference) (LPF: ulx3s_v20.lpf)
• Reuse: full software toolchain (assembler, linker, simulator, C compiler) plus hw/ CPU core; 3rdparty/wb_intercon/rtl/verilog/{wb_mux.v,wb_arbiter.v,wb_cdc.v,wb_data_resize.v,wb_upsizer.v} (olofk Wishbone interconnect) is wired into hw/verilog/top.v and hw/yosys/Makefile, reusable for any Wishbone SoC
• Tests: dirs: ./test ./hw/verilog/sim;5 tb/test files
• Notes: primarily a software+ISA project; the FPGA implementation (hw/yosys) is a smaller part of a much larger tenyr ecosystem. Submodules fetched 2026-09-27: 3rdparty/wb_intercon@3c5d2fc

l0r3m1psum__videogame_verilog

• Functions: video-dvi, board-hw, examples
• ULX3S build: ulx3s_game.v + ulx3s_v20.lpf + build.sh (LPF: ulx3s_v20.lpf)
• Reuse: TMDS_encoder and ecp5pll modules inside ulx3s_game.v are reusable but not split out
• Tests: tools: iverilog
• Notes: Single-file design (all modules in one .v); test.sh present but minimal; screenshot IMG_1082.jpeg shows running game

lawrie__apple-one

• Functions: retro-computer, video-dvi, ps2, uart
• ULX3S build: boards/ulx3s/yosys/, rtl/boards/ulx3s/ (LPF: ulx3s_v20.lpf)
• Reuse: small Verilog DVI encoder; Apple 1 core
• Tests: 3 tb/test files;tools: iverilog
• Notes: prebuilt bit committed

lawrie__blackicemxbook

• Functions: education, examples, retro-computer, video-vga, camera, audio-dac, adc, gpio
• ULX3S build: not ULX3S; all code is in examples// (Makefile, *.pcf, *.v), shared rules examples/blackicemx.mk (nextpnr) and examples/arachne.mk (arachne-pnr); chapter dirs (Actuators/, PicoSoC/, SpinalHDL/, etc.) hold only .md prose, no code (LPF: MyStorm BlackIce Mx (STM32F4 + iCE40 HX8K carrier, not ULX3S))
• Reuse: examples/baby/{baby.v,line_ram} Manchester-Baby-style toy CPU+RAM, no SB_* primitives, portable; examples/vgabuff/vgatest.v and examples/camera/camera.v use SB_IO/SB_PLL40_CORE, need ECP5 porting; examples/*/blackicemx.mk build rules are toolchain-portable
• Tests: dirs: ./Simulation ./examples/sim;tools: verilator
• Notes: Last commit 2019-11-15 (git log). Book targets MyStorm BlackIce Mx (BlackIce II family), not ULX3S; clk25 pin name in PCFs suggests 25 MHz oscillator but not confirmed in README. Same author as many lawrie__ulx3s_* ECP5 cores already catalogued; this repo predates and does not overlap their code (different board/toolchain, book-style layout).

lawrie__fpga_pio

• Functions: board-hw, constraints, examples, NEW:pio
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: rtl PIO core (state machine + FIFO) is the main reusable IP; asm/ example PIO programs
• Tests: dirs: ./sim;tools: iverilog
• Notes: recreates the RP2040 PIO peripheral in FPGA fabric; ULX3S is one of several supported boards (also blackicemx)

lawrie__fpgacosmacelf

• Functions: soc-cpu, retro-computer, uart, education
• ULX3S build: ulx3s/ (LPF: custom minimal ulx3s.lpf)
• Reuse: CDP1802.scala CPU, CDP1861.scala video
• Tests: dirs: ./verification
• Notes: minimal I/O; unverified on HW

lawrie__hdmi_examples

• Functions: examples, video-dvi, retro-arcade
• ULX3S build: not ULX3S; per-example dir (Makefile, hdmi.pcf, *.v); root Makefile also builds hdmipong.v directly (LPF: BlackIce II (iCE40 HX8K, not ULX3S); hdmi_test_ibr/ additionally targets iCEBreaker (iCE40 UP5K, not ULX3S))
• Reuse: root/hdmipong.v and ball_paddle/ball_paddle.v: self-contained VGA-timed DVI/TMDS pong+ball-paddle game logic, no SB_* seen in the .v files themselves (TMDS/DVI serialization likely relies on external IP not vendored here); portable core game logic, DVI serializer needs checking before reuse
• Tests: tools: iverilog
• Notes: Last commit 2022-05-12 (git log, most recent of the lawrie BlackIce trio). dfu-util flash target (STM32 DFU) confirms BlackIce II carrier, same family as blackicemxbook/verilog_examples but separate repo, no code overlap seen.

lawrie__ice40logicsniffer

• Functions: logic-analyzer, uart
• ULX3S build: ulx3s/ (build.sh, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/ SUMP core (trigger, sampler, rle_enc), ecp5_pll.v
• Tests: 1 tb/test files;tools: iverilog
• Notes: BRAM-based, not SDRAM

lawrie__jupiter_ace

• Functions: retro-computer, ps2, uart, multi-board, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_ace.lpf) (LPF: ulx3s_ace.lpf (also ulx4m_v002.lpf for ULX4M variant))
• Reuse: src/cpu, src/top/jupiter_ace_ulx3s.v
• Tests: none found
• Notes: Also supports the ULX4M board (ulx4m/ dir) alongside ULX3S; 16kb RAM extension mentioned as current feature set

lawrie__slabboy

• Functions: retro-console, oled-lcd
• ULX3S build: root (GameBoyUlx3s.scala → .v) (LPF: ulx3s_v20.lpf)
• Reuse: ST7789.scala (SpinalHDL LCD driver), GB CPU
• Tests: none found
• Notes: WIP 2020; no HDMI

lawrie__spinalulx3s

• Functions: video-dvi, ps2, usb-host, synth-audio, oled-lcd, soc-cpu, linux, hdl-language, examples
• ULX3S build: repo root: multiple Makefile.* (hdmi/oled/ps2/tone/usb/audio) + ulx3s_hdmi.lpf/ulx3s_ps2.lpf/ulx3s_usb.lpf/ulx3s_v20.lpf/ulx3s_vga.lpf + src/main/scala/mylib/ULX3S.scala (LPF: ulx3s_v20.lpf (+ dedicated ulx3s_hdmi.lpf, ulx3s_ps2.lpf, ulx3s_usb.lpf, ulx3s_vga.lpf per feature demo))
• Reuse: ULX3S.scala SpinalHDL board-definition component reusable across SpinalHDL projects; saxon-bin/ prebuilt SaxonSoc bitstreams (minimal/sdram/linux variants) usable standalone
• Tests: none found
• Notes: Multiple independent example designs share one repo, each with its own Makefile.* and .lpf; saxon-bin/*.bit are prebuilt third-party (SaxonSoc) binaries, not built from source here

lawrie__ulx3s-nmigen-examples

• Functions: video-dvi, camera, sdram, ps2, oled-lcd, retro-computer, uart, examples, hdl-language
• ULX3S build: 30 example dirs (blinky/, camera85/, dvi/, sdram/, ps2_keyboard/, retro/, mitecpu/, opc/, life/, st7789/, …) (LPF: nmigen_boards.ulx3s platform (external package; no local .lpf))
• Reuse: camera85/ (OV7670 pipeline), sdram/sdram16/sdram32 controllers, dvi/ (vga2dvid+tmds), retro/, mitecpu/
• Tests: dirs: ./camera/sim ./opc/tests;11 tb/test files;tools: iverilog
• Notes: large actively-curated example set; no local .lpf because constraints come from the nmigen_boards.ulx3s Python platform package

lawrie__ulx3s_68k

• Functions: retro-computer, esp32, hdl-language
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: shared ulx3s/ulx3s.mk build-glue pattern; roms/gcc/ cross-build setup for 68k software
• Tests: none found
• Notes: README is a single-line stub (“Experiments with the 68000 CPU”); appears to be a testbed/precursor to lawrie’s other 68k-CPU retro cores rather than a finished computer

lawrie__ulx3s_acorn_atom

• Functions: retro-computer, video-dvi, ps2, flash-spi, audio-dac
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf, pll.v); ulx4m/ is a second ULX4M-board variant (LPF: ulx3s_v20.lpf (also ulx4m_v002.lpf for the ULX4M variant))
• Reuse: src/sid/ (SID 6581 audio emulation), src/m6522.v (VIA), src/mc6847.v (video chip emulation)
• Tests: none found
• Notes: Multi-board (ulx3s + ulx4m variants); no LICENSE file found.

lawrie__ulx3s_altair_8800

• Functions: retro-computer, video-dvi, board-hw, esp32
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: shared ulx3s/ulx3s.mk build-glue pattern; front-panel LED/switch UI logic reusable for other vintage-computer front-panel emulations
• Tests: none found
• Notes: ulx3s.mk’s own default (12k) contradicts the Makefile-level override (85k) and the README’s explicit 85F-only requirement - a likely leftover/inconsistent default, not a real 12F build option

lawrie__ulx3s_amstrad_cpc

• Functions: retro-computer, video-dvi, synth-audio, ps2, esp32, sdcard
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf (also ulx4m/ulx4m_v002.lpf for the separate ulx4m board target))
• Reuse: shared ulx3s/ulx3s.mk build-glue pattern; OSD disk-image loader logic reusable for other lawrie retro cores
• Tests: none found
• Notes: README documents real limitations: video memory fixed at 0xC000 (BRAM), CPU runs slightly faster than real hardware (no shared-memory contention), only one read-only disk drive supported

lawrie__ulx3s_atari_2600

• Functions: retro-console, video-composite, esp32, uart, oled-lcd, multi-board, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf (also ulx4m_v002.lpf))
• Reuse: src/cpu (6502), src/video (TIA), src/pot (paddle input)
• Tests: dirs: ./roms/tests
• Notes: roms/tests/ holds test ASM ROMs assembled with bundled dasm assembler

lawrie__ulx3s_ay_3_8500

• Functions: retro-arcade, video-composite, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/ (AY-3-8500 Pong chip recreation, small self-contained core)
• Tests: none found
• Notes: Minimal single-purpose demo, no README beyond one line

lawrie__ulx3s_bbc_micro

• Functions: retro-computer, video-composite, sdcard, flash-spi, uart, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/ (6502-based BBC Micro core), roms/build.sh ROM packer
• Tests: none found
• Notes: ROMs (os12.rom, basic2.rom, MMFS.rom) are copyrighted BBC/Acorn binaries bundled as-is

lawrie__ulx3s_colecovision

• Functions: retro-console, video-dvi, esp32, multi-board
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf, ulx3s_v20_diag.lpf); also ulx4m/ for a related (non-ULX3S) board (LPF: ulx3s_v20.lpf (+ ulx3s_v20_diag.lpf); ulx4m/ulx4m_v002.lpf is for the separate ulx4m board, not ULX3S)
• Reuse: shared ulx3s/ulx3s.mk build-glue pattern reused across lawrie’s other retro cores
• Tests: none found
• Notes: Repo covers two boards: ulx3s/ (this catalogue’s target) and a separate ulx4m/ (different LPF, different device um-45k) - keep the two build trees distinct when reusing

lawrie__ulx3s_cpm_z80

• Functions: retro-computer, sdcard, ps2, uart, oled-lcd, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/Components/Z80, src/Components/SDCARD, src/Components/UART, src/Components/TERMINAL
• Tests: dirs: ./src/Test;2 tb/test files
• Notes: README notes loading CP/M “currently hangs or gives a repeated K>” error – known-broken at time of writing; needs external SD card image

lawrie__ulx3s_examples

• Functions: examples, education, video-dvi, oled-lcd, audio-dac, uart, ps2, sdram, usb-host, soc-cpu, retro-computer, retro-arcade, led-matrix
• ULX3S build: each top-level dir (ulx3s.mk) (LPF: ulx3s_v20.lpf)
• Reuse: hdmi/ (hdmi_video, terminal, sprite, menu PicoRV32); st7789/oled_video.v; sdram16/sdram.v; ps2*; cpu grom, i8080 altair, picorv32, fx68k
• Tests: 1 tb/test files;tools: iverilog
• Notes: 2022

lawrie__ulx3s_gamegear

• Functions: retro-console, video-dvi, ps2, esp32, oled-lcd, audio-dac
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/Z80 (tv80 core), src/osd, src/spi_display (ST7789 LCD driver), src/sn76489.v
• Tests: none found
• Notes: Same Z80/SMS-family core as lawrie__ulx3s_sg_1000; adds SPI LCD (ST7789) support not present in the SG-1000 version.

lawrie__ulx3s_mac128

• Functions: retro-computer, video-dvi, sdram, synth-audio, esp32, ps2
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: fx68k 68000 CPU, floppy/iwm.v disk controller, SDRAM controller by Paul Ruiz - all reusable across lawrie’s 68k-family cores
• Tests: none found
• Notes: README documents known bugs: floppy read errors requiring eject/reinsert, keyboard repeat timing issues; SCSI hard disk not supported

lawrie__ulx3s_msx

• Functions: retro-computer, esp32, video-dvi, ps2, sdcard
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf, ulx3s_v20_diag.lpf) (LPF: ulx3s_v20.lpf (+ ulx3s_v20_diag.lpf diagnostic variant))
• Reuse: shared ulx3s/ulx3s.mk build-glue pattern reused across lawrie’s other retro cores; roms/make_rom.sh ROM packaging script
• Tests: none found
• Notes: README is a single-line stub; part of lawrie’s large family of same-pattern retro-computer ULX3S ports

lawrie__ulx3s_pdp_11

• Functions: retro-computer
• ULX3S build: NO ULX3S (LPF: none)
• Reuse: none
• Tests: none found
• Notes: EMPTY repo — only a one-line README, no HDL/LPF/build files whatsoever; survey description was accurate in intent but nothing was ever implemented/pushed

lawrie__ulx3s_ql

• Functions: retro-computer, sdcard, esp32, uart, oled-lcd, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/fx68k (68000 core), src/osd, src/spi_display
• Tests: none found
• Notes: esp32/ dir for ESP32-side OSD/menu firmware; roms/gcc toolchain bundled for building QDOS-side tools

lawrie__ulx3s_sg_1000

• Functions: retro-console, video-dvi, ps2, esp32, sdram
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/Z80 (tv80 core), src/osd (SPI on-screen-display), src/sn76489.v (PSG audio)
• Tests: none found
• Notes: Includes one ROM (roms/chop_lifter.sg); esp32/ dir holds ESP32-side OSD firmware.

lawrie__ulx3s_sms

• Functions: retro-console, video-dvi, audio-dac, sdram, esp32, sdcard, oled-lcd
• ULX3S build: ulx3s/, ulx4m/ (LPF: ulx3s_v20.lpf)
• Reuse: src/sn76489.v, sdram.v, src/osd/ (standard ESP32 SPI OSD stack), hdmi.v
• Tests: none found
• Notes: many games fail; 2023

lawrie__ulx3s_trs_80

• Functions: retro-computer, video-dvi, ps2, esp32, sdcard
• ULX3S build: ulx3s/ (LPF: ulx3s_v20.lpf)
• Reuse: src/osd/*, ps2.v, hdmi.v, tv80
• Tests: none found
• Notes: 2020

lawrie__ulx3s_vhdl_examples

• Functions: examples, education, audio-dac, board-hw, constraints, hdl-language
• ULX3S build: root (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: basics/ (led, counter, sum, trigger, button, debounce), audio/ (piano, sound) – small teaching examples
• Tests: none found
• Notes: Straightforward teaching repo, no HDL synthesis surprises

lawrie__ulx3s_vic_20

• Functions: retro-computer, sdcard, esp32, uart, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/ (VIC-20 core), esp32/snapshots (expansion RAM snapshot support), esp32/cmdline
• Tests: none found
• Notes: roms/kernal.rom, basic.rom, characters.rom are Commodore-copyrighted vendor binaries checked into the repo

lawrie__ulx3s_z80_template

• Functions: retro-computer, sdcard, esp32, uart, ps2, oled-lcd, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/Z80 (core), src/video, src/keyboard, src/memory, src/lattice – explicitly designed as a reusable base for other Z80 machines
• Tests: none found
• Notes: Template project: README lists ~8 machines meant to be derived from it (several are separate cloned repos in this catalogue, e.g. ulx3s_z80_trs80)

lawrie__ulx3s_z80_trs80

• Functions: retro-computer, sdcard, esp32, uart, ps2, oled-lcd, board-hw, constraints
• ULX3S build: ulx3s/ (ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/Z80, src/video (TRS-80 character generator), src/keyboard (MiSTer-derived PS/2 matrix mapper)
• Tests: none found
• Notes: roms/BOOT.ROM and charrom.mem are vendor-copyrighted TRS-80 binaries; several .cas game images (dslogo, galaxy, meteor, spores) bundled too

lawrie__ulx3s_zx81

• Functions: retro-computer, video-dvi, ps2, audio-dac
• ULX3S build: ulx3s/, ulx4m/ (LPF: ulx3s_zx81.lpf)
• Reuse: scandoubler.v, ps2.v, hdmi.v, ecp5pll.sv
• Tests: none found
• Notes: 2022

lawrie__ulx3s_zx_spectrum

• Functions: retro-computer, video-dvi, video-composite, ps2, esp32, sdcard, synth-audio
• ULX3S build: ulx3s/ (Makefile, ulx3s.mk, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: shared ulx3s/ulx3s.mk build-glue pattern reused across lawrie’s other retro cores
• Tests: none found
• Notes: ROM handling: open opense.rom bundled; copyrighted real 48.rom left to user to source

lawrie__ulx4m_amaranth_examples

• Functions: board-hw, video-dvi, sdram, ps2, oled-lcd, synth-audio, soc-cpu, ulx4m, examples
• ULX3S build: 13 example dirs (audio/, blinky/, dvi/, life/, mitecpu/, oled/, ps2_keyboard/, sdram16/, st7789/, uart/, …), each with its own ulx4m.py platform (LPF: per-example ulx4m.py platform file (BG381 package, speed 6); no checked-in .lpf)
• Reuse: dvi/ (tmds_encoder.py, vga2dvid.py), life/ (Conway’s Life + OSD loader), st7789/ (SPI LCD driver), blinky/ulx4m.py (reusable platform base)
• Tests: 3 tb/test files
• Notes: Python/Amaranth sibling of lawrie’s ULX3S nmigen-examples repo; targets the ULX4M board specifically

lawrie__ulx4m_examples

• Functions: board-hw, video-dvi, sdram, soc-cpu, uart, ulx4m, examples
• ULX3S build: 13 example dirs (basics/, hdmi/, sdram/, softcore/, gpi2/, audio/, protocols/); ulx4m_v002.lpf, ulx4m.mk at root (LPF: ulx4m_v002.lpf)
• Reuse: hdmi/ (vga2dvid.v, tmds_encoder.v), softcore/riscv, softcore/altair (Altair 8800), sdram/sdram16, sdram/sdram8
• Tests: 1 tb/test files
• Notes: targets the ULX4M (ECP5-on-Raspberry-Pi-CM4 board), a sibling device to ULX3S not an error; SDRAM examples need the SDRAM (not DDR3) ULX4M variant

lawrie__verilog_examples

• Functions: examples, retro-computer, video-vga, ps2, audio-dac, synth-audio, gpio, spi
• ULX3S build: not ULX3S; per-example dir with Makefile + *.pcf + *.v, shared rules fpga/blackice.mk, ebook/blackice.mk (both arachne-pnr) and fpga4fun/main.mk (nextpnr-ice40 or arachne-pnr via USE_ARACHNEPNR) (LPF: BlackIce II (myStorm, iCE40 HX8K, not ULX3S))
• Reuse: fpga/computer/ (baby-style retro computer + PS2ScanToAscii.v + vga.v text field): portable core logic, no SB_* seen; fpga4fun/main.mk generic %.v->%.bin build-rule pattern is toolchain-agnostic and reusable for any iCE40 example dir
• Tests: tools: iverilog
• Notes: Last commit 2019-09-08 (git log). Book/example companion repo to lawrie__blackicemxbook (same author, same BlackIce II board+toolchain); no code overlap seen (different example set). fpga4fun/main.mk defines %_tb/%_syntb iverilog simulation rules but no *_tb.v source files exist in this clone.

lazardjurovic__edulent_rtl

• Functions: soc-cpu, education
• ULX3S build: rtl/Makefile (make yosys), rtl/build.ys, rtl/ulx3s.lpf (LPF: rtl/ulx3s.lpf (“ULX3S v2.0 and v2.1”))
• Reuse: rtl/src/{control_unit,data_path,edulent,memory}.sv: small CISC CPU core (39 one/two-byte instructions), portable SV, no vendor primitives. README also states the design is meant to go through OpenLane (Skywater130 ASIC flow), not only FPGAs.
• Tests: dirs: ./rtl/tb;5 tb/test files;tools: verilator
• Notes: Last commit 2025-03-26. rtl/tb/*.sv are waveform-only (#-delay/wait, no PASS/FAIL/assert). A second Makefile (verilator_scripts/Makefile) also exists, running control_unit via $(VERILATOR) (uppercase variable, missed by the automated make_tests scanner) and dumping dump.vcd – also waveform-only, no self-check.

lcausevic__ulx3s_fpga_logic_structures

• Functions: board-hw, education, adc, examples
• ULX3S build: ULX3S-85F.zip (extract) -> ULX3S-85F///*.ldf + *.vhd, one Diamond project per topic (LPF: unknown (LPF not found outside Diamond project constraint files, not inspected inside zip))
• Reuse: none identified as standalone reusable (all small teaching exercises)
• Tests: none found
• Notes: Entire repo is one ULX3S-85F.zip with 8 Diamond sub-projects (adc, automati, brojaci, i2c, kombinacijska_logika, muxevi, pid, pwm, uart), prebuilt .bit/.ncd, no top-level README/LICENSE; Croatian folder names (coursework)

lfglabs-dev__lean-silicon

• Functions: uart, jtag, board-hw, constraints, bootloader, crypto, logic-analyzer
• ULX3S build: fpga/ulx3s/ (Makefile, ulx3s_v318_smoke.lpf, ulx3s_top.sv, uart_tx/rx/bridge.sv) – a minor smoke-test harness, not the project’s main deliverable (LPF: ulx3s_v318_smoke.lpf (explicitly a “pin-subset hypothesis” for v3.1.8, unconfirmed beyond a few pins))
• Reuse: fpga/ulx3s/uart_tx.sv, uart_rx.sv, uart_bridge.sv – small standalone UART blocks usable outside this project
• Tests: dirs: ./test ./sim ./fpga_harness/tests;64 tb/test files;tools: cocotb,iverilog
• Notes: ULX3S is a tiny fraction of a large ASIC/formal-verification research repo (asic_core, formal proofs, silicon bringup); per its own docs the FPGA smoke artefacts are “reviewable artefacts only, never programmed to hardware”

linuxjedi__minimig_ecs

• Functions: retro-computer, board-hw, ps2, usb-host, video-dvi, sdram, audio-spdif, multi-board
• ULX3S build: proj/lattice/ulx3s/universal_make_{ps2kbd,usbjoy}/; proj/lattice/constraints/ulx3s_v20.lpf; rtl_emard/lattice/ulx3s/ (LPF: proj/lattice/constraints/ulx3s_v20.lpf, ulx3s_v17p.lpf)
• Reuse: source_emard/Minimig1.v, rtl_emard/ generic SDRAM/USB/VGA/OSD modules, proj/lattice/include/ dual-toolchain build scripts
• Tests: none found
• Notes: heavyweight multi-vendor project; ULX3S is a secondary target alongside FleaFPGA Ohm; full core needs Minimig_ECS_Diamond_Project.zip on some paths

litex-hub__linux-on-litex-vexriscv

• Functions: soc-cpu, linux, sdram, sdcard, uart, video-dvi, bootloader
• ULX3S build: boards.py class ULX3S (uses litex-boards radiona_ulx3s) (LPF: litex-boards radiona_ulx3s)
• Reuse: boards.py ULX3S block, buildroot tree
• Tests: dirs: ./test;2 tb/test files
• Notes: thin glue; ULX4M too; active 2026

litex-hub__litex-boards

• Functions: toolchain, board-hw, sdram, video-dvi, ethernet, sdcard, spi, ulx4m, serdes-pcie-sata
• ULX3S build: litex_boards/platforms/radiona_ulx3s.py + litex_boards/targets/radiona_ulx3s.py (also radiona_ulx4m_ld_v2.py, radiona_ulx4m_ls_v2.py); no static Makefile/.lpf — LiteX/Migen generate the build at run time (LPF: radiona_ulx3s.py revision default “2.0” (device default LFE5U-45F, asserts 12F/25F/45F/85F); radiona_ulx4m_ld_v2.py revision “0.3”; radiona_ulx4m_ls_v2.py revision “0.1”)
• Reuse: litex_boards/platforms/radiona_ulx3s.py + targets/radiona_ulx3s.py: ready-made ULX3S pin/IO map + SoC target (python3 -m litex_boards.targets.radiona_ulx3s); litex_boards/targets/lambdaconcept_ecpix5.py + litex_acorn_baseboard.py show ECP5-5G SATA/SerDes CRG wiring (with_sata=, ECP5PLL sata_refclk) portable to other ECP5-5G boards
• Tests: dirs: ./test;12 tb/test files
• Notes: last commit 2026-09-28 (very active upstream LiteX-Hub project); real unittest test suite (test/test_targets.py etc., 12 test files, smoke-builds many targets via subprocess) — not Makefile-driven, so the Makefile scanner finds nothing; radiona_ulx4m_ld_v2/ls_v2 targets themselves wire no SATA/PCIe/SerDes (only lambdaconcept_ecpix5 and litex_acorn_baseboard do)

logoposeidon__ulx3sjukebox

• Functions: sdcard, audio-dac
• ULX3S build: root (ulx3s_v20.lpf, prebuilt ulx3s.bit/ulx3s_out.config) (LPF: ulx3s_v20.lpf)
• Reuse: SDKartenLeser.v (SD card reader), dacpwm.v (PWM DAC), queue.v
• Tests: none found
• Notes: No Makefile/build script committed (only synthesized outputs); pcmtohex.c is an offline PCM-to-hex song converter, not part of the FPGA build.

lucasebskora__wav-player

• Functions: soc-cpu, sdcard, oled-lcd, audio-dac, gpio
• ULX3S build: Makefile (BOARD ?= ulx3s), hardware/soc-wav.si (LPF: ULX3S (‘this project is aimed at implementation on an ulx3s board’, README))
• Reuse: hardware/ice-v-oled.si / ice-v.si: RISC-V core + OLED integration variants of Silice’s Ice-V, portable; firmware/{display.c,sdcard.c,oled.c}: reusable bare-metal C drivers for the same peripheral set
• Tests: tools: verilator
• Notes: Last commit 2025-02-07. School project (Telecom Nancy SLE major). .gitmodules declares firmware/fat_io_lib (ultraembedded/fat_io_lib) – NOT fetched in this clone (no such directory present), and firmware/Makefile’s OBJS list references fat_io_lib.o directly, so the firmware cannot actually build from this clone alone without fetching that submodule.

lucysrausch__colorlight-led-cube

• Functions: led-matrix, ethernet, constraints
• ULX3S build: fpga/syn/Makefile (fpga/syn/top.lpf, fpga/top.v top; fpga/syn/syn.ys yosys script) (LPF: Colorlight 5A-75B v7.0 (not ULX3S))
• Reuse: fpga/ledpanel.v (HUB75e RGB LED panel driver/scan-out, plain Verilog, portable), fpga/udp_panel_writer.v (UDP payload -> panel framebuffer writer, portable), fpga/pll.v uses ECP5 EHXPLLL (25->125MHz clock + 52MHz panel clock), needs porting for other boards
• Tests: none found
• Notes: Last commit 2023-01-10 (git log). liteeth_core.v/.yml is regenerated from LiteEth at build time (external dependency, not reproducible from this repo alone without LiteX installed). 112 GitHub stars per survey. Prebuilt fpga/syn/top.bit/top.svf present in repo.

machdyne__fpga-dac

• Functions: audio-dac, flash-spi, board-hw
• ULX3S build: Makefile (audio_konfekt/audio_lakritz/audio_noir targets); rtl/ (audio.v, spiflashro32.v, pll.v); boards/{konfekt,lakritz,noir}_v0.lpf (LPF: Machdyne Konfekt v0 / Lakritz v0 / Noir v0 (not ULX3S))
• Reuse: rtl/audio.v (sigma-delta DAC + SPI-flash PCM reader, plain portable Verilog); rtl/pll.v (ECP5 PLL wrapper, header warns it targets Diamond synth quirks - verify params, would need re-deriving for ULX3S 25 MHz input)
• Tests: none found
• Notes: Small, focused, README calls it ‘experimental’. rtl/pll.v comments warn of Diamond 3.7-3.10 CPHASE/FPHASE issues even though the Makefile builds it via the open yosys+nextpnr-ecp5 flow - verify PLL output before reuse. Last commit 2024-06-17 per sources.tsv.

machdyne__nes_ecp5

• Functions: retro-console, video-dvi, sdcard, esp32, flash-spi, usb-host, audio-dac
• ULX3S build: top.v, nes.v, ulx3s_v20.lpf (root) (LPF: ulx3s_v20.lpf only)
• Reuse: mappers/ (same MMC/VRC library as cheyao’s fork), t65/
• Tests: none found
• Notes: cheyao__nes_ecp5 is the better/more complete copy (adds ULX4M + icepi-zero + OSD refinements); this targets 12F by default

machdyne__tinydfu-bootloader

• Functions: bootloader, usb-device, flash-spi, i2c
• ULX3S build: not ULX3S; per-board dirs boards/{lakritz,obst,konfekt,kopflos,klinge,minze,schoko,kaugummi,kuchen,riegel}/ (Makefile, tinydfu_.v, .lpf/pcf) for ECP5/iCE40; boards/arty_a7 for Xilinx XC7 (LPF: Lone Dynamics Lakritz/Obst/Konfekt/Kopflos/Klinge/Minze/Schoko/Kaugummi/Kuchen/Riegel; also TinyFPGA BX, Logicbone ECP5, Arty A7 (none ULX3S))
• Reuse: usb/usb_dfu_core.v + usb_phy_ecp5.v/usb_phy_ice40.v/usb_phy_xc7.v: portable bit-banged USB DFU core with a per-family PHY wrapper (boards/lakritz/tinydfu_lakritz.v instantiates usb_dfu_core+usb_phy_ecp5; the core itself uses no SB_*/proprietary primitives, only BB tristate + ECP5 USRMCLK in the board top); i2c/i2c_master.v: standalone I2C master with its own testbench (testbenches/i2c_master_tb.v)
• Tests: dirs: ./testbenches;1 tb/test files
• Notes: Last commit 2026-09-06 (git log). VID:PID 0x16d0:0x116d used by ALL Machdyne ECP5 boards (per-board boardinfo.vh BOARD_VID/BOARD_PID, e.g. boards/lakritz/boardinfo.vh) - confirms the guide’s downstream citation directly in this upstream source. Flash layout has BOTH variants coexisting here: 1MB boot region / 0x100000 user start on kaugummi, klinge, konfekt, kopflos, minze, schoko; 256KB boot / 0x040000 user start on lakritz and obst (boardinfo.vh comment: sized to twice the compressed bootloader; “KEEP USERPART_START AND BOOTADDR IN THIS BOARD’S Makefile IN SYNC”); kuchen/riegel use a third, ~132KB-boot/163840-user layout. Entry is NOT button-based: the bootloader always runs first from flash address 0 and auto-boots the user image after a ~5s timer unless DFU activity or an explicit dfu-util detach changes that (boards/lakritz/tinydfu_lakritz.v boot_delay/user_auto_boot/dfu_detach logic).

machdyne__zeitlos

• Functions: soc-cpu, video-dvi, sdram, sdcard, usb-host, ethernet, audio-dac, linux, bootloader, board-hw, constraints
• ULX3S build: boards/ulx3s.lpf, docs/ulx3s.md, release/{targets/ulx3s_{12f,45f,85f}.spec,hw/boards/ulx3s.spec}, Makefile BOARD=ulx3s target (LPF: ulx3s.lpf)
• Reuse: rtl/cpu (PicoRV32/Zeitlos32), rtl/ext/{usb_cdc,usb_hid_host} vendored reusable IP with own licenses; sw/ext/nextvi editor
• Tests: dirs: ./rtl/tests ./rtl/tb ./sim ./tools/ask/tests ./sw/test;57 tb/test files;tools: iverilog
• Notes: Machdyne’s own boards (e.g. Alverstone) are the primary target; ULX3S is one of several supported boards; large WIP scope

makisness__inductiq

• Functions: dsp, adc, uart, gpio
• ULX3S build: hdl/rtl/top.sv, hdl/rtl/ulx3s_v20.lpf, hdl/rtl/apio.ini (apio board=ulx3s-85f) (LPF: ULX3S (hdl/rtl/ulx3s_v20.lpf, apio board=ulx3s-85f))
• Reuse: hdl/rtl/dds/configurable_nco.v + quarter_sine_lut_Q1_15.mem: 32-bit phase-accumulator NCO with quarter-wave BRAM sine LUT (Q1.15), portable Verilog, no vendor primitives; hdl/rtl/lia/lia_core.sv: digital lock-in mixer + dual (I/Q) accumulator (12-bit ADC sample x 16-bit sine/cosine reference, 48-bit accumulators, averages up to 2^15 samples), portable SV
• Tests: dirs: ./hdl/tb;1 tb/test files
• Notes: Last commit 2026-09-15 (git log -1). PLL 25MHz->80MHz (hdl/rtl/clocks/pll_25_to_80.sv, header notes it targets Diamond 3.7-3.9, may break on 3.10+). ADC SPI master (adc_spi_master.v) clocked so o_sclk=16MHz for ~1MSa/s. DDS SPI master runs off a fixed 25MHz DDS_MCLK_HZ local parameter (dds_manager.sv) independent of the 80MHz system clock. No submodules.

mangelajo__orangecrab-usb

• Functions: usb-device, audio-i2s, camera, board-hw
• ULX3S build: ./ (Makefile, Makefile.audio, synthesis/orangecrab_r0.2.1.pcf) (LPF: OrangeCrab r0.1/r0.2/r0.2.1 (CSFBGA285, not ULX3S))
• Reuse: hdl/i2s/i2s.v (I2S RX, portable), hdl/clkdiv/clkdiv.v (clock divider, portable); ip/FPGA-USB-Device/RTL/usbfs_core/*.v (USB1.1 FS device core, portable Verilog); RTL/usb_class/ also ships unused usb_keyboard_top.v, usb_disk_top.v, usb_serial_top.v/usb_serial2_top.v classes not wired into this repo’s two demos
• Tests: 2 tb/test files;tools: cocotb
• Notes: Build is container-based (podman/docker via container.mk). Submodules fetched 2026-09-27: ip/FPGA-USB-Device@6cfd6fb (GPL-3.0). Flagging: submodule is GPLv3 while the wrapping repo declares no license - a real license mismatch for anyone redistributing the combined work.

marinsiric__ulx3s

• Functions: board-hw, jtag, uart, education
• ULX3S build: Diamond/lab2 (serial_tx lab); Diamond/passthru/ulx3s-v2.0-{12f,25f,45f,85f} (LPF: Diamond/lab2/ulx3s_v20.lpf; ulx3s-v2.0-{12f,25f,45f,85f}/project.ldf)
• Reuse: none
• Tests: none found
• Notes: README is just a title; Dokumentacija/*.doc is Croatian; looks like a university (FER2) lab exercise repo, mostly a copy of stock examples

markus-zzz__hyperram-test

• Functions: psram, hyperram, soc-cpu, uart
• ULX3S build: syn/build-ulx3s.sh, syn/ulx3s-top.v, syn/ulx3s-top.ys, syn/ulx3s.lpf (ULX3S v2.0/2.1); rtl/top.v is the portable SoC top instantiated by syn/ulx3s-top.v (LPF: ULX3S v2.0/2.1 (syn/ulx3s.lpf header comment))
• Reuse: rtl/hyper_xface.v: portable dword HyperRAM interface (no vendor primitives, div-4 core-clock DDR timing, avoids needing a PLL), CERN-OHL-v1.2, drop-in on any ECP5/iCE40 board; rtl/top.v shows a minimal picorv32+spram+sprom+hyper_xface SoC wiring pattern
• Tests: dirs: ./sim;tools: verilator
• Notes: last commit 2021-12-30; sim/test-bench.v is waveform-only ($dumpvars + fixed-time $finish, no assertions) and needs an external Cypress s27kl0642.v HyperRAM model (sim/README links Infineon/Cypress verilog model, not vendored in the clone) to actually run; tests HyperRAM add-on boards the author assembled (README: “not a PMOD”)

markus-zzz__max9850-test

• Functions: soc-cpu, i2c, audio-dac, gpio
• ULX3S build: syn/build-ulx3s.sh, syn/ulx3s.lpf, syn/ulx3s-top.v (LPF: ULX3S (custom MAX9850 expansion board, not a PMOD, per README))
• Reuse: rtl/picorv32.v: vendored PicoRV32 RISC-V core, ISC-licensed, widely portable; sw/max9850-test.c: bare-metal SW-driven I2C register-write pattern for the MAX9850 codec, small and reusable
• Tests: dirs: ./sim;tools: verilator
• Notes: Last commit 2022-01-30. Purpose-built hardware-assembly smoke test, not a general design; no .gitmodules (picorv32 vendored as a plain file copy).

markus-zzz__myc64

• Functions: retro-computer, usb-host, synth-audio, board-hw
• ULX3S build: syn/ (ulx3s-top.v, ulx3s-top.ys, ulx3s.lpf, build-ulx3s.sh) (LPF: syn/ulx3s.lpf)
• Reuse: syn/ulx3s-top.v/.ys build pattern; C64 core itself (rtl/) reusable on other boards via Verilator sim harness
• Tests: dirs: ./sim;tools: verilator
• Notes: README marks project “[WIP]”; full MyC64-SoC (USB keyboard) needs 2 extra external repos not present in this clone; ROMs must be fetched separately via roms/fetch-roms.sh (copyrighted C64 ROMs)

markus-zzz__zzz-rv

• Functions: soc-cpu, linux, sdram, uart, spi
• ULX3S build: syn/ulx3s.lpf, syn/ulx3s-top.v, syn/soc.ys, syn/ecp5pll.sv (LPF: ULX3S (syn/ulx3s.lpf))
• Reuse: syn/ecp5pll.sv: parametric ECP5 PLL wrapper (same lineage as emard’s ecp5pll); rtl/{cache.py,clint.py,uart.py,spi.py,sdram.py}: portable Amaranth peripheral/cache modules
• Tests: dirs: ./sim ./tests;tools: verilator,iverilog
• Notes: Last commit 2023-09-16. README’s own FPGA section is literally the placeholder text ‘Bla bla ULX3S bla bla’ – docs unfinished – but syn/ulx3s.lpf + syn/ulx3s-top.v are real and exercised in the full-SoC Icarus cosim (make sim-iverilog). .gitmodules declares thirdparty/riscv-tests and thirdparty/mini-rv32ima (software/tests) – NEITHER is fetched (no thirdparty/ contents present), so ISA compliance tests cannot run; a separate self-contained tests/ dir is unaffected.

marph91__pocket-bnn

• Functions: ml-accelerator, uart, examples
• ULX3S build: syn/ulx3s_v20.lpf + top Makefile (target bnn.bit / prog) (LPF: syn/ulx3s_v20.lpf)
• Reuse: Generic BNN-to-VHDL generation flow (src/) reusable for other BNN topologies/boards; submodules/icestick-uart/hdl/uart_top.vhd (marph91’s lightweight 115200 8-N-1 UART sender/receiver, echoes received words) is the actual UART core streaming BNN results off-board, reusable standalone
• Tests: dirs: ./submodules/icestick-uart/sim ./sim;11 tb/test files;tools: cocotb,ghdl-sim
• Notes: README gives concrete resource numbers: 17276/41820 (41%) TRELLIS_SLICE at 25MHz (max 132MHz) for the MNIST demo; "first example, more stats will follow" - early-stage framework. Submodules fetched 2026-09-27: submodules/icestick-uart@426b25d

marph91__yaaes

• Functions: crypto, examples
• ULX3S build: syn/ (synth.sh, constraints/ulx3s_v20.lpf) (LPF: syn/constraints/ulx3s_v20.lpf)
• Reuse: aes core (VHDL) directly reusable as a standalone crypto IP block; cocotb testbench suite for verification
• Tests: dirs: ./sim;tools: vunit
• Notes: README notes “Test on FPGA” checkbox unticked (only reported working on an Altera Max 10 by a third party, not confirmed on ULX3S itself); CI badges for testsuite/vhdl_style/synthesis

mattvenn__fpga-sdft

• Functions: dsp, NEW:fft, video-vga, adc
• ULX3S build: NOT ULX3S; hdl/top.v (top), hdl/{8k.pcf,icestick.pcf}, Makefile (LPF: iCE40 HX8K breakout (ct256, default) / iCEstick HX1K (icestick.pcf present); not ULX3S)
• Reuse: hdl/sdft.v (sliding-DFT core, parametric data_width/freq_bins/freq_w) + hdl/twiddle_rom.v (twiddle_real.list/twiddle_imag.list generated by python/gen_twiddle.py); validated against numpy fft via python/sdft.py model (make model-sdft)
• Tests: dirs: ./tests;5 tb/test files;tools: iverilog
• Notes: Last commit 2020-04-24 (git log). tests/localparams.vh sets freq_bins=32, data_width=8, freq_data_w=20; VGA bar height = 480/32 bins. No submodules, no LICENSE file.

maxhpc__ecpix-5

• Functions: ddr3, uart, gpu, constraints, board-hw
• ULX3S build: not ULX3S; top-level ecpix5.sv/ecpix5.lpf/ecpix5ports.hv + build.mk (yosys/nextpnr-ecp5/ecppack); per-design dirs leds/, uart/, vx/ each include ../build.mk (LPF: ECPIX-5 (revision unstated; ecpix5_ports.hv pin names incl. rst_ft2232, hdmi_rst_, phy_rst_ match an early/r02-class board))
• Reuse: libs/{maxhpc_fifo_dc.sv,maxhpc_fifo_sc.sv,maxhpc_dpram.sv} (small dual/single-clock FIFO and DPRAM, plain SV, no vendor primitives, portable); libs/uart/uart.sv (self-contained UART, parametric CLK_HZ/BAUD, portable)
• Tests: dirs: ./vx/tb;tools: verilator
• Notes: Last commit 2025-02-09. libs/ddr3/ddr3_top.sv includes ../../core_ddr3_controller (git submodule -> maxhpc/core_ddr3_controller, a copy of ultraembedded/core_ddr3_controller); NOT fetched here since the same upstream is cloned separately as ultraembedded__core_ddr3_controller. vx/ needs an external, un-vendored Vortex GPGPU tree (hardcoded VORTEX_ROOT path); vx_stub.sv only stubs its interface.

maxzischka1__fastfouriertransformproject

• Functions: dsp, NEW:fft, uart
• ULX3S build: NOT ULX3S; TopLevel.sv (top, chains SDFCell/SDFCell0 stages), top.sv/top.v uart wrapper, Makefile (MODULE=top) (LPF: unknown iCE40 UP5K SG48 board (no .pcf found in this clone, no board name in README); not ULX3S)
• Reuse: TopLevel.sv + SDFCell.sv/SDFCell0.sv (radix-2 SDF butterfly stages chained for N=16, sizes 16/8/4/2 hardcoded; an N>8 generate-loop variant exists but is commented out); SBM16.sv (parametric complex multiplier instantiating 4x SB_MAC16 - iCE40-only, needs porting to ECP5 DSP/inferred multiplier for reuse elsewhere)
• Tests: 1 tb/test files;tools: verilator
• Notes: Last commit 2026-09-28 (git log, same day as this survey). README: “Early stages of a Radix-2 FFT IP block … will later be compared to a more parallel implementation on a MAX10 FPGA.” Fixed point is Q1.15 (inputsGen.py). No LICENSE.

mb-sat__ulx3s-longwave-sdr

• Functions: dsp-sdr, radio-rx, video-dvi, adc, flash-spi, board-hw, constraints
• ULX3S build: logic/ulx3s-stream-verilog/ (ulx3s.v, ulx3s_v20.lpf, compile script) (LPF: ulx3s_v20.lpf)
• Reuse: logic/common-verilog/{bitlog16,bitexp16,uart-fifo,femtorv32_gracilis,MappedSPIFlash}.v; fft-core; usb_cdc module (own LICENSE)
• Tests: dirs: ./testbench
• Notes: substantial real project by named author (Dr. Matthias Koch); GPL-3.0; verified working ULX3S 85F build with compile script

mcejp__poly94

• Functions: soc-cpu, uart, sdram, flash-spi, examples, board-hw, constraints
• ULX3S build: root (ulx3s_v20.lpf, rtl/top_ulx3s.v, Makefile) (LPF: ulx3s_v20.lpf)
• Reuse: rtl/ip (reusable IP blocks), lib/verilog-uart/rtl/ (alexforencich’s UART-to-AXI-Stream core with its own cocotb testbenches, wired via poly94.ys/Makefile), sdk/ (firmware SDK), tools/ci (Fmax/benchmark CI scripts)
• Tests: dirs: ./rtl/sim ./sim ./lib/verilog-uart/tb;3 tb/test files;tools: cocotb,verilator
• Notes: Well-engineered: has simulation (sim/), test vectors, CI badges (Fmax/Dhrystone), cocotb tests (test_my_design.py); prebuilt bitstreams for 3 FPGA sizes ship in repo. Submodules fetched 2026-09-27: lib/verilog-uart@b973f08

mebner86__icesugar-pro_sound2fft

• Functions: audio-i2s, dsp-sdr, video-dvi, education, uart, constraints
• ULX3S build: projects/06_live_fft/Makefile (icesugar_pro.lpf, live_fft.v) and projects/07_live_real_fft/ (I2S->FFT->HDMI demos); each of the 17 projects/_*/ has its own Makefile+icesugar_pro.lpf+top .v; root Makefile drives them all (LPF: iCESugar-Pro (ECP5-25F) (not ULX3S))
• Reuse: rtl/fft256.v + fft_real512.v (streaming radix-2 FFT cores, portable), rtl/tmds_encoder.v + tmds_serializer.v (DVI/HDMI TMDS output; serializer uses ECP5 ODDRX1F, needs porting), rtl/pdm_cic.v + pdm_modulator.v + i2s_rx.v/i2s_tx.v (PDM/I2S front-end, portable), rtl/ecp5_stubs.v (EHXPLLL Verilator black-box stub showing exact PLL primitive used)
• Tests: dirs: ./tests;27 tb/test files;tools: cocotb,verilator,iverilog
• Notes: Last commit 2026-04-03 (git log). Active CI-gated project (GitHub Actions badge, pre-commit hooks). rtl/ holds shared modules reused across the 17 numbered projects/ demos; tests/ holds separate cocotb unit tests per rtl module.

meharbaan2__systemverilog-ofdm-phy-core

• Functions: dsp, NEW:fft, radio-rx, radio-tx
• ULX3S build: no Makefile; synth/run_synth.sh (yosys+nextpnr-ice40 –up5k –package sg48); rtl/ofdm_fft64.sv (LPF: generic UPduino/iCE40UP5K SG48 (synthesis-only, no board bring-up); not ULX3S)
• Reuse: rtl/ofdm_fft64.sv: 64-pt iterative radix-2 in-place FFT/IFFT (array-based work[]/next_work[], bit-reversed output, 24-bit Q8.16 fixed point, ROM twiddle case-table) inside a full OFDM TX/RX PHY (56 data + comb pilots, QPSK/16-QAM/64-QAM, LS channel est + ZF/MMSE equalizer); plain SV, no vendor primitives, portable; only synthesised for iCE40 UP5K SG48 (no board test)
• Tests: dirs: ./sim ./tb;3 tb/test files;tools: verilator

• Notes: Last commit 2026-06-11. No LICENSE. Author states synthesis-only (no board bring-up); nextpnr-ice40 run in synth/run_synth.sh is best-effort (‘

  true’) so a P&R failure would not fail the script. 24-bit fixed point (Q8.16) throughout the datapath. README shows a passing local Verilator regression (basic/streaming/scoreboard).

mehrdadh__lora-modulator

• Functions: dsp-sdr, radio-tx, dsp
• ULX3S build: not ULX3S; source/rtl/topModule.v, source/lora_modulator.lpf, lora_tx.ldf (Lattice Diamond project, no Makefile) (LPF: tinySDR board with AT86RF215 RF IC (not ULX3S); lora_modulator.lpf, LVDS serial_iq pins)
• Reuse: source/rtl/{chirpGenerator.v,accInc.v,phaseInc.v,initialPhase.v,sinIdeal.v,cosIdeal.v}: parametrized chirp/phase-accumulator + sin/cos generator, BW 31.25kHz-500kHz and SF6-12 selectable (PRECISION-parametrized, portable); IQSerializer.v: LVDS I/Q serializer for AT86RF215; loraPacketGenerator.v/loRaModulator.v: symbol/packet FSM
• Tests: none found
• Notes: Last commit 2025-02-20. Companion module mehrdadh/fsk-modulator (also tinySDR, ECP5 25F, not cloned) shares the same PLL. Top clock 32MHz (PERIOD PORT top_clk 31.25ns), PLL to 64MHz (my_pll_64mhz). No submodules, no test directory found.

michaelbell__nanov

• Functions: soc-cpu, hdl-language, uart, spi, NEW:bit-serial-cpu, NEW:tiny-tapeout
• ULX3S build: NOT ULX3S: root Makefile (iceFUN), pico_ice/Makefile + pico_ice/pico_ice.pcf (pico-ice) (LPF: iceFUN (iCE40 HX8K), pico-ice (iCE40 UP5K) (neither ULX3S))
• Reuse: core.v/cpu.v/alu.v/register.v/shift.v/multiply.v (bit-serial RV32E core, area-minimized register-ring design), uart/uart_tx.v + uart/uart_rx.v (simple UART) – register.v uses SB_ (iCE40) primitive, rest is portable plain Verilog
• Tests: 11 tb/test files;tools: cocotb,verilator
• Notes: last commit 2024-11-17; author’s successor project is TinyQV (4-bit serial, QSPI PSRAM/flash, taped out TT06, per README); no ULX3S port; README documents FRAM-backed persistent-RAM design

micki0271__maeri

• Functions: soc-cpu, sdram, ml-accelerator, ethernet
• ULX3S build: maeri/gateware/platform/ulx3s/{top,ulx3s85f,mem,sdram_controller}.py (LPF: maeri/gateware/platform/ulx3s/ulx3s85f.py (custom platform, revision unspecified))
• Reuse: maeri/gateware/compute_unit/*: MAERI-style reconfigurable-interconnect compute core (nMigen); maeri/gateware/platform/shared/{store,load,serial_link,interface_controller,load_afifo,store_afifo}.py: portable serial-link/AFIFO glue; maeri/gateware/platform/ulx3s/sdram_controller.py: ECP5 SDRAM controller.
• Tests: dirs: ./test ./maeri/compiler/tests;7 tb/test files
• Notes: Last commit 2020-12-06 (‘[Not yet ready!]’ per README). README claims ‘RTL extensively formally verified’ and reverse-engineered PNR/synth tools, but no .sby formal scripts exist in this clone; maeri/common/formal.py is only a generic FHDLTestCase helper. Depends on LUNA’s StreamInterface (external, not vendored).

mikeakohn__apollo11_fpga

• Functions: soc-cpu, retro-computer, uart, spi, oled-lcd, NEW:agc-cpu
• ULX3S build: NOT ULX3S: root Makefile, src/agc.v, icefun.pcf (LPF: iceFUN (iCE40 HX8K CB132) (not ULX3S))
• Reuse: src/agc.v (16-bit AGC-ISA CPU core, non-RISC historical ISA), src/display_spi.v (bit-bang SPI LCD driver), src/servo_control.v (PWM servo driver), src/eeprom.v (SPI EEPROM controller) – plain Verilog, no SB_ vendor primitives used, portable
• Tests: dirs: ./test
• Notes: last commit 2024-12-25; runs on iceFUN at 6 MHz per README; test/ holds 16 hand-written .asm programs assembled with naken_asm, not HDL testbenches; no ULX3S port

mikeakohn__riscv_fpga

• Functions: soc-cpu, uart, spi, gpio, synth-audio, NEW:mandelbrot-accel
• ULX3S build: Makefile, src/riscv.v (top); alt target tang_nano: src/riscv.v, tangnano20k.cst (LPF: iceFUN (Lattice iCE40 HX8K, CB132) (not ULX3S); Sipeed Tang Nano 20K (Gowin GW2A-18C) (not ULX3S))
• Reuse: src/riscv.v (or riscv_mandel.v/ciscv.v alt tops), src/alu.v, src/memory_bus.v, src/uart.v (fixed 9600 baud), src/spi.v, src/eeprom.v - pure behavioral Verilog, no SB_ primitives found (grep), board-agnostic; only icefun.pcf/tangnano20k.cst are board-specific. src/mandelbrot.v: fixed-point (6.10) Mandelbrot core wired to a custom mulw opcode.
• Tests: dirs: ./test;1 tb/test files
• Notes: Last commit 2026-06-26 (git log). raw_clk on iceFUN pin P7, internally divided (clock_div[0]); no board osc frequency documented in repo. No submodules.

mit-plv__koika

• Functions: soc-cpu, uart, examples, hdl-language
• ULX3S build: examples/rv/etc/{top_ulx3s.v,ulx3s_v20.lpf} (LPF: ulx3s_v20.lpf)
• Reuse: the koika language/compiler (coq/, ocaml/) is the real reusable artifact; examples/rv is a demo RISC-V core
• Tests: dirs: ./tests ./examples/rv/tests;tools: verilator,iverilog
• Notes: academic HDL-research project (Coq-verified rule-based HDL); ULX3S support is a minor example target, FPGA size unpinned

mithro__asus-d16-ulx3s-interface

• Functions: board-hw, jtag, uart, flash-spi, esp32, programmer-tool
• ULX3S build: wiring/ (pinmap only; SoC platform/gateware not yet written) (LPF: none yet (no .lpf; pin map still CSV/JSON, not synthesized))
• Reuse: wiring/make_pinmap.py pin-map generator + validator; wiring/pinout_diagrams.py
• Tests: dirs: ./test ./sim
• Notes: Early bring-up (P0/P1): README says Quickstart ‘to be filled in during P1’; only wiring/pinout tooling exists, no LiteX SoC/gateware source yet despite the description; genuinely NO ULX3S bitstream/build present.

mkvenkit__learn_fpga

• Functions: examples, education, video-dvi, uart, hdl-language
• ULX3S build: ecp5_ulx3s/{uart_tx,vga_bram,vga_hello}/ (each with Makefile + ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf (x3, one per sub-example))
• Reuse: uart_tx, vga_bram, vga_hello small self-contained examples
• Tests: dirs: ./ice40up5k/i2s_mic/tb;2 tb/test files;tools: iverilog
• Notes: Repo is a multi-board grab-bag; only ecp5_ulx3s/ subtree targets ULX3S, rest is iCE40HX1k/UP5k/Zynq/Migen

mkvenkit__ulx3s_examples

• Functions: none
• ULX3S build: NO ULX3S (LPF: none)
• Reuse: none
• Tests: none found
• Notes: EMPTY repo: just a README saying it migrated to mkvenkit/learn_fpga; no HDL/build files at all; survey listed it as ULX3S examples but there is nothing here

mmicko__fpga101-workshop

• Functions: education, examples, video-vga, oled-lcd, audio-dac, uart, soc-cpu, retro-computer, NEW:micropython
• ULX3S build: no ULX3S target (FPGA101 badge only); per-exercise apio projects: tutorials//{top.v,pinout.pcf,apio.ini}; tests/led, tests/riscv; projects/galaksija. ULX3S version: ulx3s__fpga-odysseus (LPF: FPGA101 badge (Hackaday Belgrade 2018, iCE40 UP5K, parallel RGB LCD, RGB LED, buttons, audio) (not ULX3S))
• Reuse: tutorials/10-CPU/grom_cpu.v + alu.v + grom_computer.v: original toy 8-bit ‘grom’ CPU (portable, no SB_*; identical copies in lawrie__ulx3s_examples, lawrie__ulx4m_examples, ulx3s__fpga-odysseus); tutorials/11-Computer: i8080 (Bashkiria-2M) + mc6850 ACIA + Altair wrapper (portable); tutorials/12-RiscV: PicoSoC with SB_SPRAM256KA RAM (up_spram.v), LCD text video, simpleuart, + 02-Micropython/ports/picorv32 (MicroPython port with LCD/LED/switch modules); video exercises use SB_PLL40_CORE/SB_HFOSC (port to EHXPLLL)
• Tests: dirs: ./tests;3 tb/test files
• Notes: Last commit 2019-03-17 (workshop held 2018-05-26). 20 exercises: 00 IceStudio, 01 Basics, 02 LED, 03 Buttons, 04 Audio, 05 Video (2), 06 StateMachine, 07 Memory (3), 08 MovingSprite, 09 Pong (4), 10 CPU, 11 Computer, 12 RiscV (+01-Simple, 02-Micropython firmware). Slides in presentation/ (pruned locally). Solves the ‘grom CPU origin unknown’ question of the lawrie__ulx3s_examples review.

mmicko__ulx3s-examples

• Functions: board-hw, examples
• ULX3S build: blinky/ (blinky.v + ulx3s_v20.lpf + apio.ini) (LPF: blinky/ulx3s_v20.lpf)
• Reuse: none (trivial blinky)
• Tests: none found
• Notes: Tiny repo: exactly one example (blinky), no README; matches survey description.

mole99__tt05-one-sprite-pony

• Functions: video-vga, spi
• ULX3S build: fpga/rtl/{ulx3s_top.sv,pll40m.v}, fpga/constraints/ulx3s_v20.lpf (LPF: fpga/constraints/ulx3s_v20.lpf)
• Reuse: src/ - sprite/background renderer core (SVGA 800x600, SPI-configurable sprite/colors); self-contained Verilog/SV, no vendor primitives observed in fpga/rtl/ulx3s_top.sv besides a board PLL (pll40m.v, not verified as EHXPLLL by grep)
• Tests: dirs: ./tb;2 tb/test files;tools: cocotb,verilator,iverilog
• Notes: Last commit 2025-02-09. No submodules. Primary target is the TT05 ASIC tile; ULX3S is an FPGA emulation/bring-up target (bring-up/ dir).

mpardalos__clash-blinky

• Functions: hdl-language, board-hw, examples, toolchain
• ULX3S build: src/Top.hs (compiles to Verilog) + ulx3s_v20.lpf, built via Shakefile.hs (LPF: ulx3s_v20.lpf)
• Reuse: Shakefile.hs build pipeline (Clash->Verilog->synth) reusable as a Clash+ULX3S template
• Tests: dirs: ./tests ./tests/Tests
• Notes: Template/scaffold repo, not a real application; useful as reference for Clash-on-ULX3S toolchain integration

msiddalingaiah__centurion

• Functions: soc-cpu, retro-computer, timer, gpio, NEW:bitslice-cpu, NEW:microcode
• ULX3S build: NOT ULX3S: Verilog/Makefile, Verilog/CPU6.v, Verilog/ice40_alchitry_cu.pcf (also unused Verilog/iceblink40_vq100.pcf for an older iCEBlink40 target) (LPF: Alchitry Cu (iCE40 HX8K CB132) (not ULX3S))
• Reuse: Verilog/Am2901.v (AM2901 4-bit ALU-slice model), Am2909.v/Am2911.v (microsequencer models), Verilog/CPU6.v (top-level CPU6 datapath/control), MapROM.v+CodeROM.v (microcode ROM, stored in iCE40 block RAM) – Verilog/iCE40.v wraps vendor SB_ primitives, rest is behavioral Verilog portable to ECP5
• Tests: tools: iverilog
• Notes: last commit 2022-08-01; microcode is 2048x56-bit stored in internal block RAM (30/32 ICESTORM_RAM used per README util report); README claims “All CPU6 instruction tests pass” but CPU6TestBench.v has no $display PASS/FAIL, only $finish – verification is VCD/GTKWave trace inspection (parse_vcd.py); interrupt/DMA pending; no ULX3S port

msinger__iceboy

• Functions: retro-console, video-vga, oled-lcd, uart, constraints, board-hw
• ULX3S build: src/boards/hx8k_brk-top.sv, src/boards/hx8k_brk.pcf, src/Makefile.am (autotools, BOARD=hx8k_brk); also src/boards/gbreveng-top.sv/.pcf; no ULX3S/ECP5 support (LPF: Lattice iCE40-HX8K Breakout Board (hx8k_brk, CT256, not ULX3S); also “gbreveng” custom Game Boy-shaped board)
• Reuse: src/cpu/sm83*.sv: cycle-accurate SM83 (Game Boy CPU) core with formal-verified ALU/control (tests/alu, tests/cpu via SymbiYosys), board-agnostic, no vendor primitives seen, portable to ECP5; src/lcds/lcd_uc1611.sv, lcd_lh507x.sv: LCD panel drivers, portable with new pin mapping
• Tests: dirs: ./sim ./sim/test ./tests
• Notes: Last commit 2025-03-29; doc/test_results.html tracks Blargg/mooneye test-suite pass rates; no submodules; board clock not found in README (not stated)

msrraju07__iop

• Functions: camera, video-dvi, sdram, board-hw, examples
• ULX3S build: src/.v (top_module.v) + constraint/ulx3s_v20.lpf; also icestudio_blocks/.ice + ULX3S_SOBEL.ice as alt Icestudio entry point (LPF: ulx3s_v20.lpf)
• Reuse: src/camera_interface.v, src/sobel_convolution.v, src/sdram_controller.v, src/hdmi_device.v, src/tmds_encoder.v, src/i2c_top.v (OV7670+SDRAM+HDMI pipeline, reusable modules)
• Tests: none found
• Notes: Makefile has hardcoded Windows path for TRELLIS var (C:/Users/…) that must be overridden; requires OV7670 PMOD camera add-on board

mysteriouswolf__vna_fpga_dsp

• Functions: dsp, dsp-sdr, adc, spi
• ULX3S build: source/core.v (top dsp_core), source/impl_1/impl_1.pdc, VNA_FPGA_DSP.rdf (Radiant project) - not ULX3S, no ECP5 support (LPF: custom VNA_Hardware PCB (iCE40UP5K-SG48I, not ULX3S); companion repos VNA_Hardware / VNA_Firmware (not cloned))
• Reuse: source/dsp.v: fir_filt (16-tap, 4-stage pipelined-MAC FIR used as the RBW/decimation filter, runtime-loadable coefficients over an addr/coef bus) and iq_demodulator (running-sum amplitude/phase detector on two ADC channels); both plain Verilog, no vendor primitives, portable to ECP5. source/spi.v: soft_spi_slave register-readout core, portable.
• Tests: dirs: ./adc_counter/testbench ./raw_meas_ram/testbench ./testbench; 2 tb/test files
• Notes: Last commit 2025-03-02. Radiant-only project, no yosys/nextpnr build path in the clone. adc_counter/pll_core are IPgen-generated black-box wrappers tied to Lattice primitives, not portable as-is. Companion hardware/firmware in separate MysteriousWolf/VNA_Hardware and VNA_Firmware repos (not cloned).

mystorm-org__blackice-ii

• Functions: board-hw, examples, uart, sram, bootloader, constraints, gpio
• ULX3S build: examples//{chip.v,*.pcf,Makefile}, e.g. examples/hello_world/{chip.v,../common/blackice-ii.pcf,Makefile}; examples/sram/{src/*.v,blackice-ii.pcf,Makefile}; examples/pll_advanced/*/pll.v (LPF: BlackIce II (not ULX3S); iCE40 HX4K TQ144; STM32L4 MCU sidecar for USB-DFU programming (100 MHz onboard oscillator, examples/common/blackice-ii.pcf: "set_io clk 129"))
• Reuse: examples/uart_loopback/{uart_rx.v,uart_tx.v}: small self-contained UART TX/RX FSMs, no SB_* primitives, portable to ECP5 as-is; examples/common/blackice-ii.pcf: reference pin map (LEDs/buttons/PMOD) for the board, needs full remap for ECP5; examples/sram/src/sram_io_ice40.v: external async SRAM I/O uses SB_IO primitives directly, needs ECP5 IO-primitive port; examples/pll_advanced//pll.v (8 variants): SB_PLL40_ instantiations, iCE40-only, needs EHXPLLL port for ECP5
• Tests: tools: iverilog
• Notes: Stale: last commit 2020-12-29. No board schematic beyond hardware/BlackIce.{sch,brd} (Eagle/OrCAD, proprietary formats); no submodules

nesl__ice40_examples

• Functions: examples, education, gpio
• ULX3S build: not ULX3S; per-example dir (Makefile, pinmap*.pcf, top.v [+helper .v]) (LPF: iCE40-HX8K Breakout Board (Lattice, part ICE40HX8K-B-EVN; not ULX3S); README notes examples are also adaptable to the smaller iCEstick)
• Reuse: blinky/top.v: minimal 32-bit binary counter on LEDs from a 12 MHz hwclk, no SB_* used, trivially portable; fsm_simple/button.v: simple debounced-button FSM pattern, portable
• Tests: none found
• Notes: Last commit 2023-04-24 (git log). Board clock is 12 MHz per README (“simple project with a 32 bit 12 MHz counter”). No overlap with lawrie__* repos (different author/board family, BlackIce II vs Lattice HX8K breakout).

nh428__ulx3s-tft-display-sobel-object-detection

• Functions: board-hw, video-input, video-composite, camera, sdram, oled-lcd, constraints
• ULX3S build: src/ (CameraToTFTSobel.ice, ice-build/main.v + main.lpf) (LPF: src/ice-build/main.lpf)
• Reuse: none (single-purpose project)
• Tests: none found
• Notes: README documents real design (pin mapping table, LUT utilization report) but code is Icestudio-generated main.v with obfuscated net names (e.g. v40f83b); self-described ‘landmines’ (wrong clock domain naming, unstable timing) — functional but rough personal project.

nickmqb__fpga_craft

• Functions: gpu, soc-cpu, video-vga, flash-spi
• ULX3S build: hw/ (build.sh, top.v, icebreaker_spi.pcf); requires external wyre/muon/kasm compiler toolchains + bram_swap host tool, not vendored here (LPF: iCEBreaker (iCE40 UP5K, SG48) + VGA PMOD + N64 controller (not ULX3S))
• Reuse: hw/top.v shows SB_PLL40_2F_PAD/SB_GB/SB_IO wiring pattern only; core logic is in Wyre (.w) files compiled via external toolchain, not portable Verilog without that toolchain - limited direct reuse for ULX3S
• Tests: none found
• Notes: Verified Apache-2.0 via LICENSE+SPDX headers. README disclaims ‘no real testing, may damage hardware’ - hobby/prototype. No prebuilt bitstream; needs user Minecraft textures + external muon/wyre toolchains. Not portable without reimplementing top.v’s iCE40 primitives + Wyre toolchain.

nicocavallu__fpga-lora-receiver

• Functions: radio
• ULX3S build: none (no code at all in this clone: only LICENSE and README.md) (LPF: ULX3S LFE5U-85F claimed, HackRF One/Pro SDR front-end (README))
• Reuse: none in this repo; the real DSP blocks are the separate sibling repos nicocavallu/rf-dds-lo (DDS local oscillator, complete per README) and nicocavallu/rf-sdr-frontend (20 MSPS digital-downconverter frontend, complete per README) – both ARE separately cloned in this collection as their own slugs (not part of this task’s 18) – and nicocavallu/rf-fft-engine (in progress, see that slug’s own row in this catalogue)
• Tests: none found
• Notes: Last commit 2026-08-18. No .gitmodules; the README’s links to rf-dds-lo/rf-sdr-frontend/rf-fft-engine are plain markdown links to separate GitHub repos by the same author, not git submodules of this repo. This repo itself is purely a project-status index page.

nicocavallu__rf-dds-lo

• Functions: dsp-sdr, radio-rx, examples
• ULX3S build: src/*.v + ulx3s.lpf (no committed synth/build script; README documents manual yosys/nextpnr/ecppack flow) (LPF: ulx3s.lpf)
• Reuse: src/dds_top.v, src/phase_accumulator.v, src/sine_lut.v (generic DDS core, board-independent)
• Tests: dirs: ./sim;2 tb/test files;tools: iverilog
• Notes: Sim-focused repo (run_sim.sh + waveform screenshots); no committed FPGA build script despite ulx3s.lpf being present; part of a larger planned LoRa/IRIS project

nicocavallu__rf-fft-engine

• Functions: dsp, radio
• ULX3S build: none: README claims ‘This repository includes a .lpf file for hardware integration of the ULX3S FPGA board’ but no .lpf file exists anywhere in the repo (verified) (LPF: ULX3S LFE5U-85F claimed (README), HackRF Pro SDR (README))
• Reuse: src/ping_pong_buffer.v: double-buffered dual-port-BRAM I/Q sample store with a built-in 2.5x fractional decimation counter (312.5kSPS -> 125kSPS), the only real, working block in the repo, portable Verilog
• Tests: none found
• Notes: Last commit 2026-08-21. This is the ‘Fourier Processing Block’ sub-module of nicocavallu__fpga-lora-receiver’s umbrella project, itself marked (In Progress) there. README describes a full Radix-2 FFT engine (log2(128)=7 stages, twiddle ROM) and an I^2+Q^2 peak-bin detector in detail, but src/radix2_fft.v and src/peak_finder.v are both verified-empty placeholder files with zero implementation – README/system.jpg describe intended, not built, hardware.

nicocavallu__rf-sdr-frontend

• Functions: dsp-sdr
• ULX3S build: modules/rf-dds-lo/ulx3s.lpf (only .lpf in repo, belongs to the LO submodule); src/sdr_frontend_top.v is the design top but has no board-level Makefile/build script of its own (LPF: modules/rf-dds-lo/ulx3s.lpf (“Radiona ULX3S” per both READMEs))
• Reuse: src/{clock_domain_cross,complex_mixer,cic_filt,fir_filter,tpdf_dither,dither_truncate}.v: full DDC chain – 2-stage CDC (8b I/Q alternating strobe) -> complex mixer (8x18-bit muls, 27b I/Q) -> 3-stage CIC integrator/comb decimate-by-64 (45b acc) -> 31-tap serial FIR (16b coeffs, Hamming window, fir_coeff.mem) -> 2x12-bit Galois-LFSR TPDF dither + truncate to 18b signed I/Q. Portable, no vendor primitives. modules/rf-dds-lo/*: DDS LO, catalogued separately as nicocavallu__rf-dds-lo.
• Tests: dirs: ./sim ./modules/rf-dds-lo/sim;6 tb/test files;tools: iverilog
• Notes: Last commit 2026-08-18 (rf-dds-lo submodule pinned at 2026-07-04, fetched 2026-09-28). digital_downconvert.v genuinely instantiates dds_top from the submodule. No board Makefile/lpf of its own: ULX3S build is claimed in prose, not demonstrated in this clone. Sim-only (iverilog+gtkwave), no self-checking assertions seen in testbenches.

nklabs__libnklabs-ulx3s

• Functions: soc-cpu, uart, flash-spi, sdram, bootloader
• ULX3S build: root (ulx3s.lpf, ulx3s.ldf, impl1/) (LPF: ulx3s.lpf / ulx3s.ldf)
• Reuse: rtl/picorv32.v, rtl/bus_*.v (simple bus fabric), fw/libnklabs (portable embedded CLI/database library, git subtree)
• Tests: dirs: ./fw/libnklabs/tests;3 tb/test files
• Notes: libnklabs pulled in as a git subtree (fw/subtree); firmware combined with bitstream via Diamond’s ddtcmd into one flashable image.

nkrackow__singularitysurfer-fpga-lock-in-amplifier

• Functions: dsp-sdr, dsp, adc
• ULX3S build: not ULX3S; FPGA/HDL/top.v, FPGA/HDL/Makefile (nextpnr-ice40 –up5k) (LPF: custom SingularitySurfer lock-in board (not ULX3S); 36MHz base/DSP clock, 900kHz ADC sample rate)
• Reuse: FPGA/HDL/dds.v: 1/4-sine-LUT DDS/NCO (16-bit amplitude, 18-bit phase, LFSR-dithered), portable; filter/CIC.v + filter/RIIR.v (multiplier-less shift-based IIR, RIIR_migen.py generator); cordic/{cordic.v,fullcordic.v} rect->polar CORDIC (from opencores verilog_cordic_core, 9-iteration 16-bit); mult16x16.v, sigma_delta.v DAC, pll.v; no vendor SB_* primitives seen in the DSP cores themselves
• Tests: 4 tb/test files;tools: iverilog
• Notes: Last commit 2023-05-11. ADC: MCP33131D 1MSps/16bit SAR (run at 900kHz here), PGA AD8253, ref REF5050. Uses ~85% of UP5K LUTs per README. Cores credited from opencores (CORDIC, wb_lcd) and smunaut/ice40-playground (SPI flash reader). No submodules.

no2fpga__no2bootloader

• Functions: bootloader, usb-device, soc-cpu, flash-spi
• ULX3S build: not ULX3S/ECP5 (iCE40 UP5K only; README.md: “current code targets the iCE40 FPGA boards only”); gateware/ice40-stub/Makefile (warmboot stub), gateware/ice40/Makefile (DFU core), firmware/fw_dfu.c (LPF: iCEBreaker/bitsy v0/v1, reDIP-SID, icE1usb, iCEpick, E1 tracer, osmo-amr, Fomu hacker/pvt1, Xmas Snoopy (firmware/usb_str_dfu.txt board-name JSON; none are ULX3S))
• Reuse: firmware/fw_dfu.c+usb_desc_dfu.c: DFU class firmware, own default VID:PID 0x1d50:0x6146 (BOARD=icebreaker/bitsy fallback), per-board overrides 0x6144/6148/6150/6156/617d/6174 (firmware/usb_desc_dfu.c:118-145); gateware/ice40-stub/rtl/top.v: SB_WARMBOOT 4-image selector FSM driven by one button (SB_IO/SB_WARMBOOT, iCE40-only primitives); gateware/cores/no2usb: no2usb device core (fetched submodule)
• Tests: dirs: ./gateware/ice40/sim ./gateware/ice40-stub/sim;5 tb/test files
• Notes: Last commit 2026-01-29 (git log). Submodules fetched: gateware/cores/{no2usb,no2ice40,no2misc} (pinned submodules.tsv); gateware/build (the no2build build system) deliberately NOT fetched - it is not gateware, so include ../build/project-rules.mk in gateware/ice40*/Makefile cannot resolve and neither synth nor make sim can actually run in this clone. README.md: “A modified version was already used on the ECP5 for the Hack-a-day badge 2019 supercon but the improvements still need to be integrated here” - i.e. smunaut__had2019-playground predates and is not merged into this generalized bootloader.

noxharmonium__sirc

• Functions: NEW:retro-console-vm
• ULX3S build: none - no Verilog/VHDL/lpf/pcf files exist in the clone; ULX3S is only a stated future target (README.md:65 target board "at the moment" is the ULX3s; :168 unchecked TODO "Implement Verilog based on ULX3S FPGA board") (LPF: none (no board files))
• Reuse: none (Rust simulator code, not gateware; not reusable as an FPGA block)
• Tests: dirs: ./sirc-vm/toolchain/tests ./sirc-vm/libsirc/tests ./sirc-vm/sirc-vm/tests ./sirc-vm/peripheral-bus/tests ./sirc-vm/peripheral-cpu/tests (Rust unit tests, not HDL testbenches)
• Notes: last commit 2026-09-18, active. Purely software project (VM, assembler, tile editor, VS Code extension); FPGA implementation is an unstarted roadmap item.

nullobject__counter-ulx3s

• Functions: board-hw, examples
• ULX3S build: hdl/top.v + ulx3s_v20.lpf, Makefile target toplevel.bit (LPF: ulx3s_v20.lpf)
• Reuse: none (trivial single-file counter)
• Tests: none found
• Notes: Tiny template-style repo, companion to the author’s larger m68k-ulx3s and riscv-ulx3s projects (shared Makefile conventions)

nullobject__m68k-ulx3s

• Functions: soc-cpu, oled-lcd, gpu, uart, retro-computer, board-hw
• ULX3S build: hdl/top.v + ulx3s_v20.lpf, Makefile target toplevel.bit (LPF: ulx3s_v20.lpf)
• Reuse: hdl/gpu.v, hdl/layer_processor.v, hdl/framebuffer.v, hdl/oled.v, hdl/dual_port_ram.v (tile/sprite GPU + OLED driver, reusable), lib/fx68k (vendored 68000 core)
• Tests: tools: verilator
• Notes: Sibling project to nullobject/riscv-ulx3s (shares GPU/OLED/RAM modules); m68k C toolchain (gcc-m68k-linux-gnu) required for ROM firmware

nullobject__riscv-ulx3s

• Functions: soc-cpu, oled-lcd, gpu, uart, synth-audio, board-hw
• ULX3S build: hdl/top.v + ulx3s_v20.lpf, Makefile target toplevel.bit (LPF: ulx3s_v20.lpf)
• Reuse: hdl/gpu.v, hdl/layer_processor.v, hdl/oled.v, hdl/prng.v, hdl/uart.v, hdl/encoder.v, lib/hal.c/midi.c (reusable SoC peripherals + software HAL)
• Tests: tools: verilator
• Notes: Companion to nullobject/m68k-ulx3s (shared GPU/OLED architecture, different CPU core); MIDI library suggests audio/synth use case

nusgreyhats__greybadge25

• Functions: board-hw, uart, crypto, oled-lcd, soc-cpu
• ULX3S build: firmware/ecp5/main/ (Makefile, pinout.lpf, src/top.v) main badge app; firmware/ecp5/uart_coprocessor/ (Makefile, pinout.lpf) AES demo; firmware/ecp5/tests/* bring-up tests (LPF: Greybadge25 prototype 3 (RP2350 + ECP5 25F custom CTF badge) (not ULX3S))
• Reuse: firmware/ecp5/main/src/uart/.v (baud_rate_generator, uart_top, fifo_shift - simple portable UART); src/computation/aes/.v, sha256.v, tl_des.v (crypto cores, portable Verilog, review timing/reset before reuse)
• Tests: dirs: ./firmware/ecp5/tests
• Notes: AES core under uart_coprocessor/src/aes/ is OpenCores aes_core (Usselmann), embedded without repo-level LICENSE; check its header before reuse. Confirmed 25F/CABGA256 via Makefile –25k. One-off CTF badge (commit 2026-02-05), many test/ dirs suggest active bring-up, not a finished library.

obijuan__open-fpga-verilog-tutorial

• Functions: education, hdl-language, gpio, uart, spi, timer, synth-audio, soc-cpu
• ULX3S build: no ULX3S/ECP5 support found; per-lesson Makefile+.v+.pcf, e.g. tutorial/ICESTICK/T04-counter/{Makefile,counter.v,counter.pcf} (LPF: Lattice iCE40-HX8K Breakout Board (not ULX3S); generic iCEstick HX1K (not ULX3S); FPGAwars Alhambra II (HX8K TQ144) (not ULX3S); TinyFPGA BX (LP8K CM81) (not ULX3S))
• Reuse: Small didactic Verilog blocks (counters, prescalers, mux, shift/tristate regs, FSM, UART tx/rx, ROM/RAM) meant to be copied per lesson, not a library; plain synthesizable Verilog, no vendor primitives in spot-checked files (counter.v, echowire1.v) - should port to ECP5 directly. T30-microbio/microbio.v: minimal 2-bit-opcode toy CPU (WAIT/HALT/LEDS/JP) with masm.py assembler - good tiny soc-cpu teaching reference.
• Tests: 95 tb/test files;tools: iverilog
• Notes: Last commit 2020-04-15 (git log); 872-star Spanish-language course (docs/hx-boards-survey.md). No submodules. Clock frequency varies per lesson/board pcf, not centrally documented; not verified across all dirs.

openconcepts-ar__accel2d

• Functions: gpu, soc-cpu, ddr3, ethernet, video-dvi
• ULX3S build: not ULX3S; lambdaconcept_ecpix5.py is the ECP5 LiteX target (make BOARD=lambdaconcept_ecpix5); Makefile.common’s c2v target Silice-transpiles accel_.cc into accel_.v (LPF: LambdaConcept ECPIX-5 (lambdaconcept_ecpix5.py, revision unstated); also Digilent Arty A7 and OrangeCrab (gsd_orangecrab.py))
• Reuse: accel_{ellipse_fill32,line32,rectangle_fill32}.v (Silice-generated Wishbone-attached 2D fill accelerator cores, portable RTL, no vendor primitives, generated from the matching .cc) + accel_glue.py/wpu.py (LiteX Wishbone Peripheral Unit wrapper for the accelerator cores)
• Tests: 2 tb/test files (false positive: these are demos/micropython/*_test.py demo scripts, not testbenches)
• Notes: Last commit 2026-06-09 (local shallow clone; survey lists a later 2026-09-18 push). Needs external ../CflexHDL and ../litex trees (not vendored) to rebuild accel_*.v or the SoC. Submodules micropython, fat_io_lib, agg-2.4, target-cpu/SyterKit NOT fetched (software: MicroPython fork, FAT lib, AGG 2D rasterizer, SyterKit bootloader; none are gateware).

orangecrab-fpga__orangecrab-examples

• Functions: board-hw, usb-device, soc-cpu, constraints, education

• ULX3S build: verilog/blink/ (Makefile, ../orangecrab_r0.2.1.pcf); verilog/usb_acm_device/ (Makefile); riscv/blink

  button/ (Makefile+firmware); litex/SoC-CircuitPython.py; amaranth/blink.py (LPF: OrangeCrab r0.1/r0.2/r0.2.1 (not ULX3S))

• Reuse: verilog/usb_acm_device/usb_acm_device.v + blocks/usbserial submodule (tinyfpga core, 48MHz, portable w/ new pins); litex/modules/*.py (rgb.py, analog.py, io_block.py CSR blocks); litex/deps/valentyusb/valentyusb/usbcore/ (Migen USB device core, hw_cdc_eptri branch, for LiteX SoCs)
• Tests: tools: cocotb
• Notes: Verified: Makefile builds OrangeCrab-only bitstream+DFU (CSFBGA285). DFU flashing, not JTAG/SD like ULX3S. Submodules fetched 2026-09-27: litex/deps/valentyusb@c595e1c (BSD-3-Clause), verilog/usb_acm_device/blocks/usbserial@00608c2 (Apache-2.0).

orbcode__orbtrace

• Functions: jtag, swd-debug, debug-bridge, logic-analyzer, debug-instrument, usb-device
• ULX3S build: not ULX3S; orbtrace/platforms/ecpix5.py (LiteX/Migen platform, device 45F/85F default 85F, via litex_boards lambdaconcept_ecpix5) built by orbtrace_builder.py –platform ecpix5; separate legacy plain-Verilog flow in verilog/Makefile builds an ECPIX_5_85F target directly (LPF: ORBTrace mini (own ECP5 board, primary target, orbtrace/platforms/orbtrace_mini.py); ECPIX-5 + optional breakout board (README mentions lcd/bob dir; secondary target, –device 45F/85F default 85F))
• Reuse: verilog/{swdIF.v,jtagIF.v,traceIF.v,dbgIF.v} (legacy plain-Verilog SWD/JTAG probe + parallel TRACE state machines, no vendor primitives, portable, each with a verilog/testbeds/*_tb.v); orbtrace/trace/swo.py (Amaranth SWO/TPIU pulse-length decode core, unit-tested by tests/test_swo.py)
• Tests: dirs: ./tests;10 tb/test files
• Notes: Last commit 2026-02-06 (active; 181 GitHub stars per survey). README: validated against BlackMagic Probe/OpenOCD/pyOCD; TRACE side tested against Orbuculum. Optional SUMP2 logic-analyzer core in verilog/Makefile is flagged “Probably bitrotted”.

osmocom__osmo-e1-hardware

• Functions: usb-device, soc-cpu, e1-telecom, board-hw
• ULX3S build: gateware/icE1usb/ (Makefile, data/top-ice1usb.pcf, rtl/top.v); gateware/e1-tracer/ (Makefile, data/top-e1-tracer.pcf); shared gateware/build (no2build submodule, not fetched) (LPF: icE1usb USB-E1 adapter + osmo-e1-tracer board (both iCE40 UP5K); also icE1usb-proto (iCEBreaker Bitsy/iCEBreaker prototypes) (not ULX3S))
• Reuse: gateware/cores/no2e1/rtl/*.v (submodule fetched: no2e1@dac3a8b - E1 G.703/704 framer/LIU-IF core; own README says “easy to adapt to other FPGA architectures”); common/rtl/{picorv32.v,soc_base.v,wb_arbiter.v} portable Wishbone/RISC-V SoC glue
• Tests: dirs: ./gateware/icE1usb/sim;1 tb/test files
• Notes: License verified in gateware/README.md + doc/LICENSE-*.txt; no top-level LICENSE file. no2ice40/no2misc/no2usb submodules unfetched (uses not fetched here; same core catalogued under smunaut__ice40-playground). SB_IO/SB_PLL40_2F_CORE in sysmgr.v/misc.v/top.v need EHXPLLL rework for ECP5

osresearch__spispy

• Functions: flash-spi, sdram, usb-device, uart, flash-emulator
• ULX3S build: verilog/ (spispy.v, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: verilog/sdram_ctrl.v, verilog/usb/ (TinyFPGA USB-CDC), spi_device.v
• Tests: none found
• Notes: last 2019

osresearch__up5k

• Functions: board-hw, uart, oled-lcd, audio-dac, usb-device, dsp-sdr
• ULX3S build: top-level (Makefile + Makefile.icestorm, upduino_v2.pcf); also icebreaker.pcf, tomu.pcf, tinyfpga-bx.pcf; usb/ (Makefile) for USB demos (LPF: UPduino v2 (default, not ULX3S, iCE40 UP5K); also builds for iCEBreaker, Tomu, TinyFPGA-BX)
• Reuse: spram.v (UP5K SPRAM 32K wrapper via SB_SPRAM256KA, iCE40-only), cordic.v (portable DSP core, no SB_ primitives), usb/usb_fs_*.v (full-speed USB device PHY+protocol engine, mostly primitive-free but timing tuned for iCE40 48MHz osc)
• Tests: tools: iverilog
• Notes: No LICENSE/attribution anywhere (checked README + all .v headers). SB_HFOSC/SPRAM256KA/RGBA_DRV/IO/PLL40 used in dac/spram/led_matrix/oled/pulse/blink/serial*.v - need ECP5 EHXPLLL/DP16KD/diff-IO rework. usb/ and cordic.v are more portable. upduino_v2.pcf serial pins disagree w/ schematic (per README, found by experiment).

ox-computing__real-time-analytics-fpga

• Functions: dsp, NEW:fft, ml-accelerator, i2c, spi

• ULX3S build: Makefile (DESIGN=wesad

  mnist); wesad/rtl/wesad_i2c_top.sv (ECP5, rtl/constraints/ECP5/constraints_ecp5_wesad_i2c.lpf); rtl/dwn_uart_top.v (iCE40, rtl/constraints/UP5K/dwn_uart_mnist.pcf) (LPF: ECP5 evaluation board ‘ecp5-evn’ (WESAD/FFT design, ECP5 lpf) + generic iCE40UP5K-SG48I breakout (MNIST design, UP5K pcf); not ULX3S)

• Reuse: wesad/rtl/feature_engine/fft_engine.sv: 2048-pt block-floating-point radix-2 FFT (preprocessing/detrend+Hann window, complex_butterfly, address_generator, fft_scratch_* memories, fft_twiddle_rom, hann_rom, segment_stats) feeding psd_features.sv Welch PSD; time-shares 2 SB_MAC16 DSPs; portable SV apart from wesad/rtl/frontend/input_buffers/input_buffer_spram_ice40.sv (SB_SPRAM256KA) - _ecp5.sv/_radiant.sv variants already provided for porting
• Tests: dirs: ./verification ./wesad/tb;11 tb/test files;tools: cocotb
• Notes: Last commit 2026-08-31. Two builds share one Makefile: DESIGN=wesad -> ECP5 (2048-pt FFT/DWN classifier, 460-bit thermometer code, 152 LUT4), DESIGN=mnist -> iCE40UP5K (no FFT, LUT-only classifier). Self-checking SV tb (tb_fft_engine.sv, golden-model bin comparison) exists but no make target wires it up (see make_tests).

p-kraszewski__cs-ulx3s-03

• Functions: board-hw, constraints, examples, education
• ULX3S build: 001_Knight_Rider/ (knight_rider.v + Makefile); .constraints/; .make/ulx3s.mk (LPF: .constraints/ulx3s_v20.lpf, ulx3s_v314.lpf, ulx3s_v316.lpf (default v316))
• Reuse: .make/ulx3s.mk (reusable build makefile), udev rules doc
• Tests: tools: verilator
• Notes: mostly a hardware/toolchain setup README naming the exact Mouser CS-ULX3S-03 SKU, with one worked LED example

pablogs9__rocketfpga

• Functions: board-hw, examples, uart, adc, audio-dac, audio-i2s, synth-audio, flash-spi, bootloader
• ULX3S build: Software/FPGA Sample Code/Blink/ (Makefile, pins.pcf); many sibling example dirs each w/ own Makefile+pins.pcf (LPF: RocketFPGA custom board, CH551 MCU + iCE40 UP5K (not ULX3S))
• Reuse: Software/FPGA Sample Code/UART/ (uart_rx.v, baudgen_rx.v), WaveformGenerators/ (sine/square/triangle gens + ROM hex tables), Filters/ - plain portable iCE40 Verilog, no SB_* primitives seen
• Tests: none found
• Notes: No LICENSE file despite otherwise polished repo; last commit 2020-04-11 per sources.tsv, looks dormant/prototype-stage (README TODOs unchecked). Hardware is Altium PCB (not portable). CH551 bootloader is 8051 C, unrelated to FPGA gateware.

pat-pgt__multifrequenciesdetector

• Functions: dsp, NEW:cordic-note-detector
• ULX3S build: VHDL/Makefile (targets simul_, synth_); no .pcf/.lpf; nextpnr-ice40 –hx4k –package tq144/cm225; nextpnr-ecp5 –12k target present but commented out (VHDL/Makefile:202-204) (LPF: generic iCE40 HX4K TQ144/CM225 breakout (VHDL/Makefile, no .pcf pin constraints); ECP5 12F TQFP144 target unused/commented; not ULX3S)
• Reuse: VHDL/{Cordic_.vhdl,Downsampling.vhdl,Prefilter_.vhdl}: parametric multi-stage CORDIC (rotation split one angle/stage across pipelined modules) + downsampling/pre-filter cascade driving a 12-notes-per-octave log-frequency note detector; not an FFT/DFT - no multiply/divide IP; portable VHDL (ghdl+yosys ghdl plugin), no vendor primitives seen; only iCE40 HX4K targets actually built
• Tests: none found
• Notes: Last commit 2026-09-24. AGPL-3.0. Early-stage/WIP per README (“detailed tests are going to be done after”). Only iCE40 HX4K targets actually run through synth_ice40+nextpnr-ice40 in VHDL/Makefile; the ECP5 –12k TQFP144 target (lines 202-204) is commented out and never built. No .pcf/.lpf - nextpnr invoked with only –package, no pin constraints. VHDL/Makefile literally runs ghdl -a/-e/-r simulations (e.g. simul_AnglesGene, simul_Cordic_E2E_DC_*) but via $(GHDL_PROG) variables, which the make_tests scanner’s literal-string regex misses (see make_tests).

pavlenkog__ecp5_pcie_analyzer

• Functions: logic-analyzer, NEW:serdes-pcie-sata
• ULX3S build: not ULX3S; fpga_logic/src/top.vhd (top), fpga_logic/src/analyzer.lpf (constraints), fpga_logic/script/make.tcl (Diamond project script) (LPF: Lattice ECP5 Evaluation Board (ECP5-5G EVN) + custom adapter PCB via VERSA expansion headers/SMA cables (hardware/, 3D_Freecad/))
• Reuse: fpga_logic/src/pcs_pci_rx.vhd, pcs_pci_tx.vhd – PCS-block wrappers feeding the Diamond PCIe/EXTREF IP cores for 8b10b PCIe lane capture; tied to proprietary Diamond IP (.lpc), not portable to the open toolchain without regenerating those cores
• Tests: dirs: ./fpga_logic/sim;3 tb/test files;tools: vunit
• Notes: last commit 2023-10-06 (git log -1); README shows hardware assembly photos + a Raspberry Pi capture script; status WIP/experimental per serdes_survey.md; no gitmodules found

pcotret__ulx3s-examples

• Functions: board-hw, uart, examples, hdl-language, constraints
• ULX3S build: basics/ (6 example dirs, each with its own ulx3s_v20.lpf) (LPF: basics/*/ulx3s_v20.lpf (6 copies))
• Reuse: none (example set only)
• Tests: none found
• Notes: Survey evidence (‘fork’) confirmed: README explicitly states it is taken from kost/ulx3s-ghdl-examples; good working example set.

pepijndevos__litedhrystone

• Functions: soc-cpu, NEW:benchmark
• ULX3S build: make.sh (python -m litex_boards.targets.radiona_ulx3s --device LFE5U-85F ... --build) + src/{Makefile,dhrystone*.c,main.c} (LPF: ULX3S (LFE5U-85F via litex_boards, revision unspecified))
• Reuse: src/{dhrystone.c,dhrystone_main.c}: portable Dhrystone benchmark C source (not gateware); no HDL blocks to reuse
• Tests: none found
• Notes: last commit 2024-10-30. README reports DMIPS/MHz for three CPU variants at 50 MHz (SERV 0.01, PicoRV32 0.12, VexRiscv 0.41) without stating whether they came from real hardware or litex_sim; make.sh drives openFPGALoader+litex_term against real hardware while makesim.sh is the separate simulation path.

pepijndevos__rust-litex-example

• Functions: soc-cpu, examples
• ULX3S build: NO ULX3S (no gateware/LPF/bitstream in repo; firmware only, for a LiteX SoC built elsewhere) (LPF: none)
• Reuse: src/main.rs Rust HAL demo driving SSD1306 via litex-hal
• Tests: none found
• Notes: pure firmware/software repo, no FPGA gateware included; depends on a separately-built LiteX SoC bitstream not present here

pfontvilanova__pfforthmachine

• Functions: none
• ULX3S build: NO ULX3S (LPF: none)
• Reuse: none
• Tests: none found
• Notes: repo contains only README.md, .license, .gitignore, .docs-architecture; no verilog/, tools/, tests/ despite README describing them; aspirational/empty, survey evidence unverified and turned out empty

pietptr__ulx3s-dsp

• Functions: board-hw, audio-dac, adc, dsp-sdr, hdl-language, constraints
• ULX3S build: fpga/ulx3s/ (ulx3s_v20.lpf, project.ys, prebuilt bitstream.bit committed) (LPF: fpga/ulx3s/ulx3s_v20.lpf)
• Reuse: fpga/src/Effects/ (Amplify.hs, ConstantSine.hs) DSP effect modules; fft/ standalone Haskell FFT experiments (not yet on FPGA)
• Tests: none found
• Notes: Two halves: fft/ is host-side Haskell FFT prototyping (Main.hs/Recursive.hs/Violin.hs, no FPGA), fpga/ is the actual Clash ULX3S build with DAC/ADC; a prebuilt .bit is committed so the build path is demonstrably real.

pmezydlo__beaglewire

• Functions: board-hw, gpio, uart, spi, i2c, pwm, sdram, oled-lcd, bus-fabric, examples, NEW:gpmc-bus
• ULX3S build: examples//{top.v,pinmap.pcf,Makefile} (e.g. examples/blink_leds/); shared beaglewire_pinmap.pcf, examples/Makefile.beaglewire; no ULX3S/ECP5 support (LPF: BeagleWire cape (hw by Michael Welling) on BeagleBone Black/Wireless/Industrial (not ULX3S))
• Reuse: components/{gpio-port,uart-tx,uart-rx,spi-master,i2c-master,pwm,fifo,dp-sync-ram}.v: small self-contained peripherals, portable Verilog; components/{gpmc-sync,i2c-master,sdram_controller,gpio-port}.v use SB_IO primitives (must be ported to ECP5 IO primitives for reuse); components/sdram_controller.v byte-wide SDRAM controller logic otherwise portable
• Tests: dirs: ./examples/test
• Notes: Last commit 2018-10-10 (git log). “100Mhz external clock” per README (unverified claim, not checked in source). examples/test/ is actually a blink demo (misleading dir name, not a testbench - false-positive hit in the test scanner). drivers/, DTS/, bridge_lib/, load_fw/ are BeagleBone-side Linux kernel driver + host bridge software, out of scope (gateware only catalogued here per task).

pnru__ti99

• Functions: retro-computer, video-dvi, ps2, esp32
• ULX3S build: ti99_2/ (LPF: ulx3s.lpf)
• Reuse: tms99000.v (PD CPU core), hdmi.v, ps2kb.v, hexbus.v, sdram.v
• Tests: 1 tb/test files
• Notes: gitlab source

punchthatface__tinydma

• Functions: flash-spi, board-hw, bootloader
• ULX3S build: fpga/ChipInterface_psram_bringup.sv (+ fpga/ChipInterface.sv) + constraints.lpf; prebuilt build_fpga/bitstream.bit committed (LPF: constraints.lpf (ULX3S-style LOCATE COMP pin names, e.g. clk on G2))
• Reuse: src/dma_controller.sv, src/dma_scheduler.sv, src/spi_master.sv, src/spi_psram_ctrl.sv, src/cfg_reg.sv (reusable DMA/SPI-PSRAM core, ASIC-oriented but synthesizable for ECP5)
• Tests: dirs: ./tb;5 tb/test files
• Notes: README_FPGA_BRINGUP.md frames ULX3S use only as a button/LED bring-up checkpoint for the ASIC core, not a full application; absolute macOS paths (/Users/andrewkim/…) left in README links

q3k__ulx3s-foss-blinky

• Functions: board-hw, constraints, examples, jtag, programmer-tool
• ULX3S build: ulx3s/ (top.lpf) + rtl/ + Makefile (LPF: ulx3s/top.lpf)
• Reuse: Makefile pattern for FOSS-only build+OpenOCD flash
• Tests: none found
• Notes: Requires specific old yosys/nextpnr/openocd git revisions pinned in README; template project, not a design

quigleyj97__nesgate

• Functions: soc-cpu, retro-console
• ULX3S build: targets/ulx3s_85k.vhdl, targets/ulx3s.lpf, top-level synth script (ghdl+yosys+nextpnr-ecp5+ecppack via Docker) (LPF: targets/ulx3s.lpf)
• Reuse: cores/ricoh_2A03/*: MOS 6502 sub-blocks (ALU, register file, datapath) each with its own cocotb+GHDL testbench; cores/phased_clock_generator, cores/clock_divider: small reusable utility cores. Portable VHDL, no vendor primitives seen.
• Tests: tools: cocotb
• Notes: Last commit 2025-04-20. CI (GitHub Actions) builds and publishes a ULX3S bitstream on each push (nightly.link), so the ULX3S target is real/CI-verified even though the 6502 datapath itself is still WIP per README.

racerxdl__colorlight-picorv32

• Functions: board-hw, soc-cpu, uart
• ULX3S build: Makefile, src/top.v, constraints/colorlight-i5.lpf (LPF: Colorlight I5 v6.1 (LFE5UM5G-25F, CABGA381) (not ULX3S))
• Reuse: src/picorv32.v (vendored PicoRV32 RV32I CPU core, portable, ISC-licensed); src/simpleuart.v (minimal UART peripheral, portable); src/top.v (SoC glue: 8K-word $readmemh block-RAM + memory-mapped LED + simpleuart, portable pattern for any FPGA with inferable BRAM)
• Tests: tools: iverilog
• Notes: Verified from source (Makefile, src/). Last commit 2021-02-27. Board clock 25MHz (constraints/colorlight-i5.lpf: clk_25mhz, site P3). No LICENSE/README in repo. Makefile defines test/%.dsn/%.dsn.result targets for iverilog testbenches (docker racerxdl/icarus, PASS via grep -q NOK) but no *_tb.v file exists anywhere in the clone - targets are dead/unused.

rainbow1128__vhdl-aes-master

• Functions: crypto
• ULX3S build: syn/synth.sh, syn/constraints/ulx3s_v20.lpf (LPF: syn/constraints/ulx3s_v20.lpf)
• Reuse: src/{aes,cipher,key_expansion,input_conversion,output_conversion,aes_pkg}.vhd: standalone AES-128/256 core (8/32/128-bit interface, ECB/CBC/CFB/OFB), portable VHDL-2008, no vendor primitives; already catalogued once as marph91__yaaes (data/catalogue.json, function crypto, rank best).
• Tests: dirs: ./sim;tools: vunit
• Notes: Last commit 2023-05-02. Real ECP5-85F PnR results reported (3109/41820 TRELLIS_SLICE, 121MHz Fmax) but README’s own ‘Test on FPGA’ checkbox is unticked – only a third party reported running it, on an Altera Max10, not on ULX3S hardware itself. This repo is an unmodified copy of the already-catalogued marph91__yaaes.

ranzbak__fpga-workshop

• Functions: board-hw, education, examples, constraints
• ULX3S build: 03-blink/ (Makefile, upduino_v2.pcf); 11-sim/ (Makefile, simulate.v, simulate_tb.v) for the simulation lesson (LPF: UPDuino v2.0 (iCE40UP5K breakout board) (not ULX3S))
• Reuse: 11-sim/simulate.v + simulate_tb.v (iverilog+gtkwave testbench pattern, portable); 13-temp-ds18b20/ (1-wire protocol Verilog, plain logic, no UP5K primitives)
• Tests: 11 tb/test files;tools: iverilog
• Notes: Legacy toolchain: uses arachne-pnr not nextpnr-ecp5/ice40, so the build flow itself needs replacing to port to ULX3S even though lesson Verilog is plain and portable. Dormant since 2020-03-10 per sources.tsv. Teaching-quality code, not production cores.

reddocmd__klaus

• Functions: education
• ULX3S build: src/ulx3s.ml, src/ulx3s_top.ml, src/constraints.lpf, bin/build.ml (dune exec src/build.exe -- build dayNN) (LPF: src/constraints.lpf (“ULX3S v2.x.x and v3.0.x”))
• Reuse: src/{day01,day01_pt2,day10}.ml: small Hardcaml example designs; src/loadable_pseudo_dual_port_ram.ml, src/uart.ml: reusable Hardcaml RAM/UART blocks, portable (plain generated Verilog, no vendor primitives).
• Tests: dirs: ./test
• Notes: Last commit 2026-01-16. Only day01/day01-pt2/day10 are wired into the designs list in bin/build.ml and actually buildable for hardware. Tests are OCaml dune expect-tests against a software model (waveform captured via hardcaml_waveterm), not gate-level cosimulation.

remyciterin__3driscv

• Functions: soc-cpu, gpu, sdram, video-dvi, uart, linux, ddr3
• ULX3S build: root ulx3s.lpf + Makefile (nextpnr_ulx3s target); src/Top_ulx3s.v (LPF: ulx3s.lpf)
• Reuse: src/Core.hs/Cache.hs/MMU.hs (Blarney RV32IMA CPU), src/DDR3.hs (Wishbone wrapper), simulation/vga2dvid.v+tmds_encoder.v (DVI); UberDDR3/rtl/ddr3_controller.v+ddr3_phy.v + rtl/ecp5_phy/ddr3_phy_ecp5.v (ECP5 DDR3 PHY) - instantiated per Makefile SOURCES
• Tests: dirs: ./UberDDR3/testbench ./simulation;3 tb/test files;tools: verilator,iverilog
• Notes: Uses Blarney (Haskell HDL) to generate Verilog for CPU+GPU, plus a custom compiler (compiler-experiments/) for GPU kernels; “linux” tag is loose - it boots xv6, not mainline Linux. Submodules fetched 2026-09-27: UberDDR3@a1258e2.

remyciterin__adventoffpga

• Functions: gpu, soc-cpu, examples, education, hdl-language
• ULX3S build: repo root: ulx3s.lpf, Makefile (targets: compile/yosys/nextpnr/ecppack/prog_t) (LPF: ulx3s.lpf)
• Reuse: gpu_firmware/, elf_to_hex/ toolchain, DOoOM out-of-order CPU submodule - reusable Bluespec puzzle/CPU infrastructure
• Tests: tools: verilator
• Notes: Recreational/educational project (Advent of Code puzzles as hardware); includes day1/9/10/11 recorded demo videos (mp4) directly in the repo

remyciterin__dooom

• Functions: soc-cpu, sdram, video-dvi, uart, retro-arcade
• ULX3S build: root ulx3s.lpf + Makefile (yosys/nextpnr/ecppack targets); Bluespec top compiled to Verilog (LPF: ulx3s.lpf)
• Reuse: src/Core.bsv (OOO RISC-V core), src/SDRAM.bsv (AXI4 SDRAM ctrl), src/vga2dvid.v/fake_differential.v (DVI out)
• Tests: dirs: ./simulation;tools: iverilog
• Notes: Also targets Xilinx Nexys Video via nexysvideo/+UberDDR3; needs an SD card with a DOOM WAD; ULX3S is one of two board targets. Submodules not fetched: the Nexys Video (Xilinx) build uses nexysvideo/UberDDR3 (same core is fetched in remyciterin__3driscv); nexysvideo/core_ddr3_controller is declared but unused by the Makefile.

rhobbie__library704

• Functions: cpu-retro, examples
• ULX3S build: none - pure software simulation tool (C# converter + generated Verilog run only under Icarus Verilog/vvp); no FPGA top-level, no constraints file, no synthesis Makefile of any kind (LPF: none (no target board; simulates the historical IBM 704 vacuum-tube mainframe))
• Reuse: none suitable for the ULX3S core catalogue: the “core” is a from-scratch gate-level netlist DSL + C# compiler, not portable HDL, and the generated CPU is simulation-only (Icarus-specific, no synthesis path); not added to cores.json (cpu-retro alternative slots are already full there anyway, and this would not qualify as FPGA-synthesizable gateware regardless)
• Tests: dirs: ./Library704/Testbench;tools: iverilog
• Notes: last commit 2026-09-06 (most recently active of the four group-E2 repos; the others date 2016-2019). Testbench/check.sh is a self-checking regression gate (PASS/FAIL via iverilog+vvp, README-documented) but is a shell script, not a Makefile target, so scan_make_tests.py correctly reports none found.

richardegeorge__ulx3s-chase

• Functions: board-hw, examples
• ULX3S build: blinky.v + ulx3s_v20.lpf, Makefile + committed blinky.ys yosys script and prebuilt ulx3s.bit (LPF: ulx3s_v20.lpf)
• Reuse: none (trivial single-file LED chase)
• Tests: none found
• Notes: One of 3 near-identical tiny examples by the same author (chase/flipflop/passthru); prebuilt ulx3s.bit and ulx3s_out.config committed alongside source

richardegeorge__ulx3s-flipflop

• Functions: board-hw, examples
• ULX3S build: flipflop.v + ulx3s_v20.lpf, Makefile + committed flipflop.ys and prebuilt ulx3s.bit (LPF: ulx3s_v20.lpf)
• Reuse: none (trivial single-file flip-flop demo)
• Tests: none found
• Notes: Sibling of richardegeorge/ulx3s-chase and ulx3s-passthru; source is inlined in README as well as in flipflop.v

richardegeorge__ulx3s-passthru

• Functions: board-hw, examples
• ULX3S build: passthru.v + ulx3s_v20.lpf, Makefile + committed passthru.ys and prebuilt ulx3s.bit (LPF: ulx3s_v20.lpf)
• Reuse: none (trivial single-file passthrough)
• Tests: none found
• Notes: Simplest of the 3-repo richardegeorge example series; good minimal-toolchain reference

riltonf__thermal_camera_ulx3s

• Functions: camera, video-input, video-dvi, sdram, board-hw, constraints
• ULX3S build: top.sv, top_mlx_stream.sv, top_camera_*.sv, src/ (root) (LPF: src/constraints/ulx3s_v20_edited.lpf, ulx3s_v20.lpf)
• Reuse: src/mem/mu_*.v (generic RAM/FIFO library), src/misc/i2c_master.sv, src/memory colormap ROMs, sdram_controller.sv
• Tests: dirs: ./src/test;25 tb/test files;tools: verilator,iverilog
• Notes: README says "still under construction and development"; substantial working SV codebase with svut testbenches but author-flagged WIP

rj45__vdp

• Functions: video-composite, gpu, board-hw, constraints, logic-analyzer
• ULX3S build: ulx3s/ (ulx3s.mk, top_ulx3s.sv, ulx3s_v316.lpf) (LPF: ulx3s_v316.lpf)
• Reuse: rtl/ (VDP core, C64/Amiga/NeoGeo-style tile+sprite engine), vdpemu/ (Rust emulator for co-development)
• Tests: dirs: ./sim;2 tb/test files;tools: verilator,iverilog
• Notes: Under active development (2026 pushes); includes companion Rust tools: imgconv (asset converter), vdpemu (emulator), colortest

rob-ng15__pawsv2

• Functions: soc-cpu, retro-console, video-dvi, sdcard, uart, hdl-language, examples
• ULX3S build: RV32/ULX3S/ and RV64/ULX3S/ (PAWS-ULX3S.ice, Makefile, BUILD_ulx3s/ output dir) (LPF: not found as standalone .lpf (Silice project defines board indirectly))
• Reuse: Whole RV32/SOFTWARE and RV64/SOFTWARE C program suite (games, forth, basic, jpeg, raytrace) portable to other Silice RV32/64 cores
• Tests: tools: verilator
• Notes: Huge repo (3038 files) mixing CPU core, BIOS, and a large ported C software library (games/demos/forth); RV32 dev stopped, RV64 is current

robinsonb5__eightthirtytwodemos

• Functions: soc-cpu, sdram, video-composite, examples, multi-board, board-hw, constraints
• ULX3S build: Board/ulx3s_85f/ (ulx3s_85f.lpf, ulx3s_85f_top.vhd, board.mk) (LPF: ulx3s_85f.lpf)
• Reuse: EightThirtyTwo/RTL/ (portable soft CPU core RTL, now populated), EightThirtyTwo/832a + 832ocd (assembler/on-chip debugger), EightThirtyTwo/vbcc (C compiler backend), EightThirtyTwo/lib832 (LGPL C runtime), lib832soc/, RTL/ (SoC building blocks), Lib/
• Tests: dirs: ./EightThirtyTwo/vbcc/test;2 tb/test files
• Notes: Primarily targets Altera/Intel boards; ULX3S is one of ~5 supported boards (mmm-v4r0_l5sd, icesugarpro, icepi-zero, ulx3s_85f); needs 85F. Submodules fetched 2026-09-27: EightThirtyTwo@c42d06f

romavis__lwdo-sdr-fw

• Functions: dsp-sdr, adc
• ULX3S build: not ULX3S; fpga/top.v, fpga/top.pcf, fpga/Makefile (yosys+nextpnr-ice40+icepack, DEVICE=hx4k PACKAGE=tq144) (LPF: LWDO-SDR custom board (not ULX3S); VCTCXO 20MHz reference clock (p_clk_20mhz_gbin1/2))
• Reuse: fpga/modules/{ad7357_driver.v,ad7357_clk_gen.v,adc_pipeline.v}: dual-channel AD7357 ADC SPI driver+pipeline, portable; tdc.v+tdc_pipeline.v time-to-digital converter; pps_generator.v; dac8551.v SPI DAC driver; ft245sync.v FT245 sync-FIFO host link; ice40_sspll.v wraps SB_PLL40_PAD spread-spectrum PLL (iCE40-specific, port to ECP5 EHXPLLL)
• Tests: dirs: ./fpga/test;1 tb/test files;tools: cocotb,verilator,iverilog
• Notes: Last commit 2025-03-25. fpga/3rdparty/{verilog-axis,rggen-verilog-rtl} submodules FETCHED (present on disk, listed in .gitmodules and submodules.tsv). fpga/test/ has 12 test_.v files (heuristic scanner pattern *_tb.v/tb_.v undercounts them). README calls its own testbenches "non-asserting" (VCD dump + GtkWave only).

rschlaikjer__fpga-3-softcores

• Functions: soc-cpu, wishbone-bus, uart, timer, NEW:rgb-led
• ULX3S build: rtl/top.v, hx4k_pmod.pcf, CMakeLists.txt (CMake-driven synth_ice40() target, not a plain Makefile); no ULX3S/ECP5 support (LPF: rschlaikjer/hx4k-pmod custom dev board (iCE40 HX8K, TQ144) (not ULX3S))
• Reuse: vendor/wb_intercon/rtl/verilog/{wb_arbiter,wb_mux}.v + vendor/verilog-arbiter/src/arbiter.v (submodules, fetched 2026-09-27, see submodules.tsv): portable Wishbone interconnect RTL, no iCE40 primitives, directly reusable on ECP5; rtl/{wb_ram,fifo,timer_wb,uart_wb,rgb_led_wb}.v: small self-contained Wishbone peripherals, portable; rtl/ice_pll.v uses SB_PLL40_CORE (iCE40-only, needs ECP5 EHXPLLL equivalent); vendor/vexriscv/VexRiscv.v: vendored (not submodule) SpinalHDL-generated VexRiscv core, portable RV32 CPU, reusable as-is
• Tests: dirs: ./test ./sim;8 tb/test files
• Notes: Last commit 2020-08-23 (git log). 12 MHz ext osc -> ice_pll.v -> 42 MHz wb_clk (rtl/top.v CLOCK_HZ 42_000_000; CMakeLists FREQ_MHZ=42). Repo/blog name says “3 softcores” but the gateware here builds only ONE VexRiscv-based SoC - no second/third core found in rtl/. Submodules vendor/wb_intercon@3c5d2fc7 and vendor/verilog-arbiter@782bf8f3 fetched per task instructions; vendor/vexriscv and vendor/catch are committed directly, not submodules.

ruebenschus__atari-fpcartridge

• Functions: retro-computer, board-hw, programmer-tool
• ULX3S build: stacy-cart-menu/ (rtl/top.v, ulx3s.lpf, prebuilt build/top.bit) (LPF: stacy-cart-menu/ulx3s.lpf)
• Reuse: rtl/cart_rom.v ROM-emulation module, rtl/ssd1306_menu.v OLED menu UI
• Tests: none found
• Notes: combines FPGA gateware with a KiCad adapter PCB hardware design; prebuilt bitstream committed in build/top.bit confirms a working build; Makefile hardcodes a macOS oss-cad-suite path

rxrbln__picorv32

• Functions: soc-cpu, uart, flash-spi, video-dvi, video-vga, sdram, ps2, audio-dac, constraints, board-hw
• ULX3S build: picosoc/ulx3s.v, picosoc/ulx3s.lpf, picosoc/Makefile (targets ulx3s.json/ulx3s.cfg/ulx3s.bit, ulx3sim/ulx3synsim sim) - all NEW vs upstream (LPF: ULX3S v2.0/2.1 (picosoc/ulx3s.lpf) - NEW; upstream also targets iCE40-HX8K Breakout (hx8kdemo) and iCEBreaker (UP5K))
• Reuse: picosoc/{ulx3s.v,ulx3s.lpf}: portable PicoRV32 SoC top ported to ECP5 (yosys synth_ecp5 –85k, nextpnr-ecp5 freq 50), no SB_* primitives; picosoc/{vga2dvid.v,tmds_encoder.v,video_timing.v,vga.v}: ECP5 HDMI/VGA stack (vga2dvid MIT); picosoc/sdram.v: MiST-derived SDR SDRAM controller (GPL-3.0-or-later); picosoc/audio.v: 1-bit delta-sigma DAC
• Tests: dirs: ./tests;6 tb/test files;tools: verilator,iverilog
• Notes: Last commit 2021-05-12 (git log -1; older than upstream yosyshq__picorv32’s 2026-09-07 CI touch). Fork adds picosoc/{ulx3s.v,ulx3s.lpf,sdram.v,vga.v,vga2dvid.v,tmds_encoder.v,video_timing.v,ps2.v,audio.v,spimmc.v,clk_25_250_125_25.v,fake_differential.v,libc/,user.c,sections-user.lds}. Its Makefile ulx3sim/ulx3synsim sim targets reference picosoc/ulx3s_tb.v, which is ABSENT from this clone (same missing-tb pattern as upstream’s test_rvf/rvfimon.v). No submodules.

sangwoojun__ulx3s_bsv

• Functions: soc-cpu, sdram, uart, hdl-language, ml-accelerator
• ULX3S build: src/ulx3s_bsv.lpf + projects/{rv32i,nn_fc_accel,image_proc,test}/ (each Makefile: apio init -b ulx3s-85f) (LPF: src/ulx3s_bsv.lpf)
• Reuse: src/{Uart,Sdram,PLL,Mult18x18D,BRAMSubWord,SimpleFloat}.bsv reusable modules; projects/rv32i RV32I core; projects/nn_fc_accel NN accelerator
• Tests: dirs: ./projects/test
• Notes: real ULX3S 85F build path via apio confirmed; niche Bluespec toolchain (needs bsc compiler, not widely available)

saul-rodriguez__ulx3s

• Functions: board-hw, soc-cpu, uart, examples
• ULX3S build: blink/ (blinky.v); picoRV32_rom/ (picorv32.v SoC) (LPF: blink/ulx3s_v20.lpf, picoRV32_rom/ulx3s_v20.lpf)
• Reuse: picoRV32_rom/picorv32.v (well-known picorv32 core), picoRV32_rom/uart.v, SPI_Master.v
• Tests: 5 tb/test files;tools: verilator,iverilog
• Notes: bulk of repo (firmware/) is unrelated 8-bit MCU assembler/C coursework (Eclipse CDT projects), not FPGA; blink/README.md is the stock ULX3S quick-start template

schlae__graphics-gremlin

• Functions: retro-computer, video-vga, video-composite, constraints, board-hw
• ULX3S build: verilog/mda_top.v, verilog/cga_top.v, verilog/mda70_top.v (VGA-freq MDA variant), verilog/gremlin.pcf, verilog/Makefile; no ULX3S/ECP5 support (LPF: Graphics Gremlin ISA card (custom PCB, iCE40HX4K-TQ144, not ULX3S))
• Reuse: verilog/crtc6845.v: standalone Motorola 6845 CRTC reimplementation, board-agnostic, directly reusable; verilog/cga_scandoubler.v: 15.7kHz->31.4kHz digital RGBI scan doubler, portable logic, no iCE40 primitives seen in the graphics modules themselves
• Tests: tools: iverilog
• Notes: Last commit 2024-10-24 (README banner claims this is superseded, but repo itself still active per last push date in survey: 578 stars); external SRAM (IS61C5128) is the video RAM, modeled behaviorally for sim (verilog/is61c5128_t.v); no clock frequency stated in Makefile beyond board oscillator (14.318 MHz ISA/onboard per README); no submodules

secworks__cryptkey

• Functions: soc-cpu, uart, timer, adc, NEW:trng, NEW:crypto-hsm
• ULX3S build: Makefile (TOPMOD=cryptkey) + config/ulx3s_v20.lpf; cores/srng/fpga/{rtl/srng_fpga.v,config/ulx3s_v20.lpf} for the standalone srng core (LPF: ulx3s_v20.lpf (v2.0))
• Reuse: cores/{trng,uart,timer,uds}/rtl: secworks’ own portable Verilog peripherals with per-core tb/ testbenches (verilator+iverilog); cores/srng/rtl/{srng.v,srng_core.v,blake2s_core.v}: BLAKE2s-based seeded RNG core, no vendor primitives
• Tests: dirs: ./cores/trng/tb ./cores/uart/tb ./cores/uds/tb ./cores/timer/tb;5 tb/test files;tools: verilator,iverilog
• Notes: last commit 2025-02-25. "Status: Just started. Not completed. Does. Not. Work." (README). Tillitis Tkey is the eventual target hardware but has no board files in this repo; only ULX3S build files exist.

sefbkn__versa-ecp5-demo

• Functions: ethernet, soc-cpu, uart, board-hw, constraints
• ULX3S build: ./ (Makefile, rtl/top.v, constraints/versa_sgmii.lpf / versa_rgmii.lpf) (LPF: Lattice Versa ECP5-5G (100 MHz clock, FT2232H JTAG/UART, dual 88E1512 PHYs; not ULX3S))
• Reuse: rtl/common/async_frame_fifo.v, sync_ff.v (CDC primitives, portable); rtl/ethernet/mdio/, rtl/uart/ - portable logic; SGMII/RGMII/DCU code is ECP5-specific but board-agnostic
• Tests: dirs: ./sim;1 tb/test files;tools: iverilog
• Notes: Copyright (c) 2026 Youssef Boukenken; explicitly a bring-up/demo image per README, not a general network stack; sim_async_frame_fifo target wired to iverilog; no prebuilt bitstream seen

semify-eda__waveform-generator

• Functions: dsp-sdr, synth-audio, soc-cpu, examples, logic-analyzer
• ULX3S build: fpga/ulx3s_barebones/ (ulx3s_top.sv, ulx3s_v20.lpf) and fpga/ulx3s_soc/ (LiteX-based radiona_ulx3s.py) (LPF: ulx3s_v20.lpf)
• Reuse: wfg_core/wfg_subcore/wfg_interconnect/wfg_stim_sine/wfg_stim_mem/wfg_drive_spi/wfg_drive_pat modules, each with own cocotb sim + register-file jinja2 templating
• Tests: dirs: ./design/wfg_core/sim ./design/wfg_core/testbench ./design/wfg_subcore/sim ./design/wfg_subcore/testbench ./design/wfg_interconnect/sim;17 tb/test files;tools: cocotb,verilator
• Notes: Well-engineered IP-core repo with CI, register templating, and cocotb verification; ULX3S is one demo target among generic core

seminlim__bluerv32

• Functions: soc-cpu, uart, toolchain, examples
• ULX3S build: ulx3s/ulx3s.lpf + system/Top.bsv/TopAct4.bsv (compiled via bsc to Verilog, then Makefile ‘synth’ target) (LPF: ulx3s/ulx3s.lpf)
• Reuse: processor/Processor.bsv, processor/Decode.bsv, processor/Execute.bsv, processor/RFile.bsv, processor/Multiplier.bsv, processor/Divider.bsv (clean multi-cycle RV32 core, profile-selectable ISA)
• Tests: dirs: ./tests
• Notes: Very thorough verification (riscv-arch-test, differential testing vs spike, directed tests, lint) for a student/portfolio-quality CPU core; ULX3S is one of possibly more targets via BOARD= makefile var but only ulx3s/ directory exists

seminlim__blueyosys

• Functions: sdram, gpio
• ULX3S build: boards/ulx3s/{README.md,constraints/ulx3s.lpf,85f/board.mk,rtl/{sdram.v,pll_fastclk.v,inout16.v},bsv/{PLL.bsv,Sdram.bsv,Top.bsv}} (LPF: boards/ulx3s/constraints/ulx3s.lpf)
• Reuse: boards/ulx3s/rtl/pll_fastclk.v: instantiates EHXPLLL (ECP5-specific primitive, grep-verified) - not portable to iCE40 without rework; boards/ulx3s/rtl/{sdram.v,inout16.v}: SDRAM controller wrapper + bidirectional GPIO, paired with bsv/{Sdram.bsv,PLL.bsv} wrappers
• Tests: dirs: ./projects/sway_observation/sim;tools: iverilog
• Notes: Last commit 2026-09-23 (active). Single real target currently (ULX3S-85F); the iCE40 ‘backend’ mentioned in the README is explicitly future work, not present in this clone - so this repo is not actually multi-board yet despite the group-C listing.

seminlim__sway

• Functions: dsp, ml-accelerator, uart
• ULX3S build: hw/Makefile (BOARD ?= ulx3s-85f, TOP_MODULE mkTop), hw/HwMain.bsv, hw/Top.bsv (LPF: ULX3S-85F (BOARD=ulx3s-85f))
• Reuse: hw/bsv/{SwayLinear.bsv,SwayNorm.bsv,SwayScan.bsv}: INT8 affine/norm/scan engines with explicit ties-to-even requantization, portable BSV; hw/reference/check_sim.py: generic self-checking log-vs-hex-fixture comparator
• Tests: dirs: ./hw/sim;7 tb/test files;tools: iverilog
• Notes: Last commit 2026-09-28. Requires the external seminlim/blueyosys repo (not in this collection) for the actual board LPF and build.mk; the constraint file itself is not vendored in this clone. hw/README states packing succeeds (60.47% LUT4+CCU2C+TRELLIS_DPR16X4 use) but place&route/timing closure and physical-board operation are explicitly ‘unverified’.

seminlim__zfpe

• Functions: dsp, ml-accelerator, NEW:compression
• ULX3S build: projects/{nn_fc,nn_fc_accel}/Makefile (apio init -b ulx3s-85f) – references ../../src/*.lpf which does not exist anywhere in this clone (LPF: ULX3S-85F claimed (README: “Implemented on Lattice ECP5 ULX3S”; Makefile apio -b ulx3s-85f))
• Reuse: projects/nn_fc_zfpe/{ZfpCompress.bsv,ZfpDecompress.bsv}: block floating-point-style compress/decompress pair (9-bit shared exponent + per-lane truncated mantissa over a 4-wide vector), portable BSV, but repo is incomplete
• Tests: none found
• Notes: Last commit 2021-08-20. README claims ULX3S but the repo as cloned has no src/ directory that the Makefiles reference (BSVPATH=../../src), so the ULX3S build cannot actually be reproduced from this repo alone; nn_fc_zfpe additionally has no top-level Makefile at all (only nn_fc and nn_fc_accel do).

seth16225__riscv-core-portfolio

• Functions: soc-cpu, video-dvi, usb-host, dsp
• ULX3S build: common/constraints/ulx3s.lpf, common/make/fpga.mk (included by each core’s own Makefile, e.g. cached-core/Makefile) (LPF: common/constraints/ulx3s.lpf)
• Reuse: carry-lookahead-adder/CarryLookaheadAdder.sv: 32-bit CLA, formally verified (sby); multi-cycle-core/DividerUnsignedPipelined.sv: pipelined divider; cached-core/AxilCache.sv: direct-mapped write-back AXI4-Lite cache; axil-core/system/hdmi/{tmds_encoder,vga2dvid,hdmi_video}.v + system/usb/usb_hid_host.v: vendored HDMI TMDS + USB HID host IP. Plain SV/Verilog, no vendor primitives.
• Tests: tools: cocotb,iverilog
• Notes: Last commit 2026-07-28. Fmax/FF numbers in README (4.72-36.07MHz post-PnR) are real per-core results. Cores are verified with cocotb+Verilator against the official riscv-tests RV32IM suite plus cycle-accurate reference traces (trace-*.json).

smunaut__had2019-playground

• Functions: bootloader, usb-device, soc-cpu, flash-spi, constraints
• ULX3S build: not ULX3S (HAD2019 badge only); projects/bootloader/ (Makefile, rtl/top.v, data/top-had2019-badge.lpf, fw/usb_dfu.c, fw/usb_desc_dfu.c) (LPF: HAD2019 badge (data/top-had2019-badge.lpf; not ULX3S))
• Reuse: cores/usb/rtl/usb*.v: early no2usb-for-ECP5 device core, 9/10 files byte-identical to emard__had2019-playground’s copy; usb_phy.v differs only in per-board D+/D- wiring, already uses ECP5 TRELLIS_IO (portable); fw/usb_dfu.c+usb_desc_dfu.c: DFU class firmware, 6 alt zones (fpga/soc, riscv/ipl, cart_fpga, cart_ipl, cart_tjftl/fs, bootloader); rtl/qspi_phy_ecp5.v QSPI PHY (USRMCLK/TRELLIS_IO, ECP5-specific)
• Tests: dirs: ./cores/misc/sim ./cores/usb/sim;7 tb/test files;tools: iverilog
• Notes: Last commit 2019-11-13 (git log). Upstream origin of emard__had2019-playground, which adapts pins/top for ULX3S (rtl/top-ulx3s.v) and adds ESP32 passthru + Saxonsoc/User-Data/RTC DFU zones not present here. This repo’s own dfu_zones[] (fw/usb_dfu.c:156-163): bootloader 0x000000-0x17FFFF, SoC bitstream 0x180000-0x2FFFFF, RISC-V fw 0x300000-0x37FFFF, cart zones on a separate flash chip. VID:PID 0x1d50:0x614b (fw/usb_desc_dfu.c:215-216) - same as emard’s fork, NOT 0x614a. No RTC zone/interface exists in this original at all (it is a ULX3S-only addition in emard’s fork). No submodules.

smunaut__ice40-playground

• Functions: soc-cpu, usb-device, video-dvi, led-matrix, flash-spi, psram, multi-board, constraints
• ULX3S build: projects/memtest/ (Makefile, data/top-icebreaker*.pcf); also projects/hdmi_text, rgb_panel, riscv_doom, riscv_usb, usb_amr, usb_audio (LPF: iCEBreaker v1.0/Bitsy v0-v1, MCH2022 badge, ReDIP-SID (not ULX3S, iCE40 UP5K))
• Reuse: cores/no2ice40 (SB_IO/PLL/SPRAM/RGB wrappers), cores/no2hyperbus (HyperRAM ctrl), cores/no2qpimem (QSPI PSRAM ctrl), cores/no2usb (USB FS device), cores/no2misc (WB utils), cores/no2hub75 (LED panel driver) - all iCE40-specific
• Tests: dirs: ./projects/riscv_doom/sim ./projects/usb_amr/sim ./projects/riscv_usb/sim ./projects/rgb_panel/sim ./projects/usb_audio/sim;27 tb/test files
• Notes: Verified: pure UP5K/sg48 in every projects/*/Makefile. build/ submodule (no2build) not fetched; nextpnr flags only as shown in Makefiles. Cores also used by smunaut__ice40linux (unfetched there, maybe different pin). ECP5 port needs replacing SB_IO/PLL40/SPRAM256KA/RGBA_DRV/HFOSC.

smunaut__ice40linux

• Functions: soc-cpu, linux, psram, uart, flash-spi
• ULX3S build: gateware/riscv_linux/ (Makefile, data/top-icebreaker.pcf, rtl/top.v) (LPF: iCEBreaker (not ULX3S, iCE40 UP5K) + Quad HyperRAM PMOD or Quad SPI-PSRAM PMOD)
• Reuse: gateware/riscv_linux/rtl/VexRiscv.v (SpinalHDL RV32 CPU, largely portable Verilog), rtl/soc_bram.v, rtl/platform.v (bus/peripheral glue) - depend on no2ice40/no2hyperbus/no2memcache/no2qpimem PHYs (iCE40-specific)
• Tests: dirs: ./firmware/test ./gateware/riscv_linux/sim;2 tb/test files
• Notes: Verified from source. gateware/cores/{no2ice40,no2hyperbus,no2memcache,no2misc,no2qpimem} are empty submodules here, not missing data - same no2fpga cores fetched under smunaut__ice40-playground/cores/ (pin may differ, not verified). Port needs replacing no2ice40 SB_* wrappers.

smunaut__mch2022-ice40

• Functions: board-hw, video-dvi, gpu, soc-cpu, psram, oled-lcd
• ULX3S build: projects/hdmi/ (Makefile, rtl/hdmi_top.v, rtl/top.v); projects/_common/data/mch2022-prod.pcf (LPF: MCH2022 badge FPGA (iCE40 UP5K), proto4/prod PCB revisions (mch2022-proto4.pcf, mch2022-prod.pcf) (not ULX3S))
• Reuse: cores/lcd/rtl/lcd_phy_full.v, lcd_phy_mux.v (parallel LCD PHY variants incl. HDMI-out muxing, mostly protocol logic); projects/hdmi/rtl/hdmi_tmds_simple.v, hdmi_tgen.v (TMDS/timing-gen blocks, IO buffering is iCE40-specific)
• Tests: dirs: ./projects/riscv_doom/sim ./projects/selftest/sim ./projects/tinygpu_doom/sim ./cores/spi_slave/sim;5 tb/test files
• Notes: Verified LICENSE statement + doc/LICENSE-*.txt. no2ice40/no2misc/no2qpimem/no2memcache/build submodules unfetched here; same no2fpga cores catalogued under smunaut__ice40-playground/cores/. hdmi_phy.v/sysmgr.v use SB_IO/SB_PLL40_2F_CORE - needs EHXPLLL/DDR-IO rework for ECP5 GPDI; no prebuilt bitstreams found

speccery__icy99

• Functions: retro-computer, video-composite, audio-dac, board-hw, constraints
• ULX3S build: top_ulx3s.v, ulx3s.lpf, ti994a_ulx3s.bit (prebuilt), Makefile ulx3s target (LPF: ulx3s.lpf)
• Reuse: TMS9900 CPU + TMS9918 VDP + sound-chip cores could be reused for other TI-99/99xx-family projects
• Tests: 1 tb/test files;tools: iverilog
• Notes: also has a flea_ohm (FleaFPGA Ohm, 25F) build target alongside ULX3S; no license file means default all-rights-reserved

spinalhdl__saxonsoc

• Functions: soc-cpu, linux, sdcard, uart, ps2, video-dvi, flash-spi, sdram, board-hw, constraints
• ULX3S build: hardware/synthesis/radiona/ulx3s/{minimal,smp}/ (+lpf variants); bsp/radiona/ulx3s/; hardware/scala/saxon/board/radiona/ulx3s/; deprecated hardware/synthesis/deprecated/ulx3s (LPF: ulx3s_v20_{led,linux_uboot,sdcard,hdmi,linux_ps2,xip}.lpf)
• Reuse: hardware/scala/saxon SoC generator (BMB bus, peripherals) reusable across boards; bsp/radiona/ulx3s U-Boot/Linux configs
• Tests: dirs: ./test ./software/standalone/test
• Notes: large multi-board SoC framework; deprecated ulx3s dir superseded by radiona/ulx3s; documented in bsp/radiona/ulx3s/smp/README.md

splinedrive__kianriscv

• Functions: soc-cpu, linux, sdram, flash-spi, uart, ethernet, oled-lcd, audio-dac, bootloader, education
• ULX3S build: linux_socs/kianv_mc_rv32ima_sv32/engineering/boards/ulx3s/, LinuxSoC_v2/…/ulx3s/, kianv_harris_mcycle_edition (LPF: ulx3s_v20.lpf)
• Reuse: sdram/ ctrls (mt48lc16m16a2, w9864g6jt), icache/dcache, clint/plic, qqspi, uart; CPU cores; linux_socs/LinuxSoC_v2/engineering/kianv-rv32-linuxcore/kianv_sv32.v (standalone Linux-only RV32IMA+Sv32 CPU core, SoC-independent, Apache-2.0)
• Tests: 1 tb/test files
• Notes: Linux needs 85F + 32/64MB; active 2026. Submodules fetched 2026-09-27: linux_socs/LinuxSoC_v2/engineering/kianv-rv32-linuxcore@e9640ba.

splinedrive__my_hdmi_device

• Functions: video-dvi, examples, multi-board
• ULX3S build: root (chip_balls.v) (LPF: ulx3s_v20.lpf)
• Reuse: tmds_encoder.v, hdmi_device.v, video_timings.v
• Tests: none found
• Notes: clean portable DVI core; 2025

spritetm__hadbadge2019_fpgasoc

• Functions: soc-cpu, usb-device, video-dvi, psram, audio-dac, synth-audio, jtag, uart
• ULX3S build: soc/ (Makefile, had19_prod.lpf, had19_proto1/2/3.lpf); blink/ (had19_proto1.lpf, had19_proto2.lpf) (LPF: Hackaday Supercon 2019 badge (had19_prod/proto1-3 board variants), custom ECP5-45F badge PCB (not ULX3S))
• Reuse: soc/qpi_cache/qspi_phy_2x_ecp5.v + qpimem_iface.v (ECP5 QPI PSRAM PHY/cache); soc/hdmi/vga2dvid.v + tmds_encoder.v (DVI/TMDS encoder, portable to ULX3S GPDI); soc/audio/synth_core.v + pdm.v (audio synth + PDM DAC); soc/usb/.v (USB2 device PHY/MAC); soc/picorv32/picorv32.v (single-file RV32I CPU core, highly portable)
• Tests: dirs: ./soc/picorv32/tests ./soc/sim;3 tb/test files;tools: verilator,iverilog
• Notes: Verified from source (soc/Makefile, soc/soc.v headers). Multi-year project, verilator/iverilog testbenches per block. LPF pins hardcoded to custom badge headers and PSRAM (ly68l6400) not on stock ULX3S; DVI/audio/USB cores most portable. Input clock freq unknown (generic “clk” port). Submodules fetched 2026-09-27: soc/picorv32@e0baf2e (ISC-style, the most ULX3S-friendly license in the mix).

srjilarious__fpga_start

• Functions: education, examples, board-hw, gpio
• ULX3S build: 00_blinky/CMakeLists.txt (ecp5_synthesis macro) + support/ulx3s_pins.lpf; only 00_blinky and 01_state_machine wire an ecp5_synthesis target, 02-05 are ice40-only (LPF: TinyFPGA-BX (primary); ULX3S support/ulx3s_pins.lpf (revision unspecified, covers GPIO/esp32/oled etc.))
• Reuse: cmake/yosys_ecp5.cmake + yosys_ice40.cmake: portable CMake synth/PnR/pack macros (dual ECP5/iCE40), reusable pattern for any small Verilog project; lib/ shared Verilog modules
• Tests: none found
• Notes: last commit 2026-02-28. Docker/Podman based build container. ULX3S is a secondary target (README calls TinyFPGA-BX "our target here"); only 2 of 6 examples have an ecp5_synthesis target (grep CMakeLists.txt).

stefanhaslhofer__hardwaredesign

• Functions: board-hw, esp32, examples, education, soc-cpu
• ULX3S build: blinky.v / blinky.vhd / rtl/top.vhd + ulx3s_v20.lpf, built via deploy*.sh scripts (LPF: ulx3s_v20.lpf)
• Reuse: none clearly reusable (learning exercises, README documents personal debugging journey)
• Tests: none found
• Notes: README is a first-person learning diary (‘my knowledge…is limited’); mixes Verilog and VHDL blinky variants; LedCounter/ subdir looks like a separate RISC-V assembly exercise not obviously wired to the ULX3S build

stereoninja__stereoninjafpga

• Functions: video-input, video-dvi, camera, board-hw, constraints
• ULX3S build: src/{LPF/ulx3s_v20.lpf,TOPFILES/ulx3s_.v,ulx3s_pass_through_sim}; old/ULX3S_Projects/* (many earlier HDMI test iterations); DOCS_ULX3S/ (LPF: ulx3s_v20.lpf)
• Reuse: src/TOPFILES/ulx3s_pass_through*.v MIPI passthrough tops; many old/ variants are incremental HDMI/MIPI test cores
• Tests: tools: verilator
• Notes: experimental/WIP repo with an old/ dir of many earlier one-off test projects; no license = default all-rights-reserved; messy/duplicated structure

stnolting__neorv32

• Functions: soc-cpu, bootloader, uart, flash-spi, jtag, education
• ULX3S build: NO ULX3S in repo (see neorv32-setups) (LPF: none)
• Reuse: neorv32_top.vhd, debugger, peripherals, rtl/verilog wrapper
• Tests: dirs: ./sim;2 tb/test files;tools: verilator,iverilog,ghdl-sim
• Notes: point to neorv32-setups; active 2026

stnolting__neorv32-setups

• Functions: soc-cpu, uart, board-hw, constraints, examples
• ULX3S build: osflow/{constraints/ULX3S.lpf,boards/ULX3S.mk,board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd} (LPF: ULX3S.lpf (notes v2.x.x and v3.0.x supported))
• Reuse: osflow/ generic open-toolchain build harness reusable for any BOARD; NEORV32 core is not vendored here
• Tests: none found
• Notes: companion ‘community setups’ repo to the main neorv32 core (core not vendored in this clone)

stuij__odyssey

• Functions: oled-lcd, ps2, video-composite, board-hw
• ULX3S build: verilog/odyssey_top.v + ulx3s_v20_segpdi.lpf, via Makefile including scripts/trellis_main.mk (open) or scripts/diamond_main.mk (Diamond) (LPF: ulx3s_v20_segpdi.lpf (non-standard v20 variant, board pin-mux for SPI LCD add-on))
• Reuse: verilog/ecp5pll.sv, verilog/lcd_video.v, verilog/ps2kbd.v, verilog/emhard-vga.v (reusable PLL/LCD/PS2/VGA-gen modules)
• Tests: none found
• Notes: README itself says ‘what: tbd’ — purpose/name undocumented; dual build-system scaffolding (Trellis+Diamond) but only Trellis stated as tested; st7789_linit.mem suggests ST7789 LCD init sequence data

sylefeb__a5k

• Functions: retro-arcade, examples
• ULX3S build: BITSTREAMs/ulx3s/bitstream.bit (prebuilt bitstream only, no ULX3S build sources in this repo) (LPF: none (no ULX3S lpf/constraints present))
• Reuse: VM/blitter/rasterizer Silice design is a reusable core, but built primarily for the UP5K, not ULX3S
• Tests: tools: verilator
• Notes: NO ULX3S build present, only a prebuilt HDMI bitstream ships; needs copyrighted Another World data (excluded) to run; primary board is iCEBreaker+VGA PMOD

sylefeb__silice

• Functions: hdl-language, examples, education, video-dvi, sdram, sdcard, oled-lcd, audio-i2s, audio-dac, flash-spi, uart, soc-cpu, retro-computer, gpu
• ULX3S build: frameworks/boards/ulx3s/, ~23 projects (LPF: ulx3s.lpf (from v20))
• Reuse: common/hdmi.si, sdram_.si, sdcard.si, oled.si, fire-v/ice-v RISC-V, ULX3S board framework; projects/tinygpus/hardware/GPUs/dmc-1/dmc-1.si (DMC-1 tiny GPU rasterizer, CERN-OHL-S) - built for ice40/mch2022, portable to ULX3S via the existing Silice board framework, no ULX3S target in this submodule itself
• Tests: dirs: ./python/tests ./tests;tools: verilator,iverilog
• Notes: ULX3S first-class; active 2026. Submodules fetched 2026-09-27: projects/tinygpus@498be1b.

sylefeb__tinygpus

• Functions: retro-arcade, gpu, board-hw
• ULX3S build: none - no ULX3S SOC/build directory exists; hardware/SOCs/ only has ice40-dmc-1 and ice40-dmc-1-standalone (iCE40) (LPF: ice40-dmc-1 board (not ULX3S))
• Reuse: hardware/GPUs/dmc-1/dmc-1.si: dmc-1 GPU core in Silice HDL; iCE40-SOC-oriented wiring, portability to ECP5/ULX3S not verified
• Tests: tools: verilator
• Notes: Last commit 2024-01-25. Submodule demos/q5k/qrepack/LibSL-small not fetched. The ULX3S mention (README.md:149) is a passing personal remark, not a build target - a marginal fit for the group-C survey.

tadeoroboticsgroup__axiomacore-328

• Functions: soc-cpu, uart, timer, gpio, adc, flash-spi, NEW:avr-core
• ULX3S build: Makefile (fpga-ulx3s target) + rtl/fpga/ecp5/{axioma_ulx3s_top.v,axioma_pll.v,axioma_ulx3s.lpf,ulx3s_v20_reference.lpf} (LPF: ulx3s_v20_reference.lpf (v2.0) / axioma_ulx3s.lpf)
• Reuse: rtl/core/{axioma_alu.v,axioma_sreg.v}: self-checking, oracle-verified ALU and status-register cores (sim/alu/tb_alu.cpp); rtl/periph/axioma_spi.v: SPI peripheral with its own verilator tb; axioma_pll.v instantiates EHXPLLL (ECP5-specific)
• Tests: dirs: ./legacy/scripts/verification ./legacy/testbench ./sim ./sim/tb ./sim/diff/tests;12 tb/test files;tools: cocotb,verilator,iverilog
• Notes: last commit 2026-09-26, very active. Explicitly self-corrected in its own README: header used to say it was "validado en FPGA… preparado para tape-out", now truthfully states it "synthesizes and closes timing" but "has never run on a board", and ASIC tape-out (phase 6) has not started - a strong honesty signal.

tallenintegsys__hdmi-orangecrab

• Functions: video-dvi, audio-i2s, board-hw
• ULX3S build: ./ (Makefile, orangecrab_r0.2.pcf) (LPF: OrangeCrab r0.2 (not ULX3S))
• Reuse: verilog/tmds_channel.sv, serializer.sv, hdmi.sv - HDMI TMDS/serializer stack, portable to other ECP5 boards incl. ULX3S with pin remap
• Tests: 1 tb/test files;tools: iverilog
• Notes: Early-stage port per README (“porting…”); requires the synlig yosys plugin, not stock oss-cad-suite yosys; no prebuilt bitstream in repo

tarik-hamedovic__sdr-hls

• Functions: dsp-sdr, radio-rx, adc, uart, hdl-language, examples
• ULX3S build: 1.RTLImplementation/4.lattice/{Version0,Version0-modified,Version1,Version2}/ and 3.build/ (ulx3s_85f_onebitsdr.ldf/.bit) (LPF: many ulx3s_v316*.lpf variants across per-module test projects)
• Reuse: 5.NewModules/{MyCIC,SquareRoot}/ reusable DSP blocks; 2.HLSImplementation Amaranth-HLS methodology examples
• Tests: dirs: ./3.Testing/1bitADCLattice/Testbench ./5.NewModules/MyCIC/Testbench;2 tb/test files;tools: cocotb,verilator,iverilog
• Notes: HUGE repo (323MB) — mostly Diamond synthesis logs/tmp artifacts committed (185 .log, 182 .html, 93 .db, many synplify tmp .lpf copies); genuine academic thesis project, real ULX3S 85F target confirmed via .ldf device string

td0034__fpga

• Functions: examples, board-hw, sdcard, audio-i2s, oled-lcd
• ULX3S build: ulx3s/examples/{blinky,buttons,sdcard,i2s_tone,i2s_passthrough,sdcard_i2s,oled_wave}/ + ulx3s/Makefile.inc + doc/constraints/*.lpf (LPF: doc/constraints/ulx3s_v20.lpf (+ prototype v314/v316/v17patch variants); each example has its own small .lpf)
• Reuse: ulx3s/examples/* (small self-contained example cores: blinky, buttons, sdcard WAV player, i2s tone/passthrough, oled_wave)
• Tests: tools: iverilog
• Notes: Repo mostly reproduces the official ULX3S board KiCad hardware plus a “synth-fpga-module” custom PCB derivative; the actual original gateware is just the small examples/ set.

techprototyper__trs80-rev-z

• Functions: retro-computer, video-dvi, ps2, sdcard, uart, esp32, board-hw, logic-analyzer
• ULX3S build: boards/ulx3s/ (Makefile, rtl/ulx3s_top.v, synth.ys, ulx3s_v20.lpf) using shared rtl/*.v core (LPF: ulx3s_v20.lpf)
• Reuse: rtl/m1core.v + full m1*.v module set (address decode, FDC, keyboard, video timing, VRAM), rtl/vendor/tv80 (Z80 core), boards/ulx3s/rtl/usb_hid_host (USB HID host); design-decision docs under docs/decisions/ are themselves reusable reference material
• Tests: dirs: ./boards/ulx3s/sim ./sim;46 tb/test files;tools: verilator
• Notes: Exceptionally mature/organized repo (ADR log, ROADMAP, GOVERNANCE, CONTRIBUTING, per-chapter docs) for a 0-star fresh repo; explicitly refuses to ship copyrighted ROM images; not an emulator, claims cycle-accurate RTL verified against real schematics

thata__td4-ulx3s

• Functions: education, retro-computer
• ULX3S build: root (ulx3s_v20.lpf, ulx3s_top.sv, Makefile) (LPF: ulx3s_v20.lpf)
• Reuse: cpu.v (TD4 4-bit toy CPU, tiny reference core)
• Tests: tools: iverilog
• Notes: Tiny/minimal toy CPU project (2 HDL files total); Japanese-language README.

thata__ulx3s-playground

• Functions: board-hw, examples
• ULX3S build: blinky/, bram_controller/ (root) (LPF: blinky/ulx3s_v20.lpf, bram_controller/ulx3s_v20.lpf)
• Reuse: bram_controller/bram_controller.sv (simple memory-mapped BRAM controller w/ testbench)
• Tests: tools: iverilog
• Notes: tiny personal playground, only 2 toy examples

thata__ulx3s-uart-loopback

• Functions: uart, board-hw, examples
• ULX3S build: top.sv + uart.v + ulx3s_v20.lpf, Makefile target ulx3s.bit (LPF: ulx3s_v20.lpf)
• Reuse: uart.v (small reusable UART core)
• Tests: none found
• Notes: No README content; Japanese-language repo name/description implied (‘UART loopback test’); very small single-purpose repo

theperfectcomputer__learn-clash

• Functions: education, hdl-language, uart
• ULX3S build: ulx3s/ (makefile, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: src/Blinky.hs, src/UARTTx.hs, src/Loopback.hs, src/SimpleCPU.hs (small independent Clash examples)
• Tests: dirs: ./tests ./tests/Tests
• Notes: “My first efforts to use clash lang”; a collection of small independent examples, not one integrated design.

theperfectcomputer__mannachip

• Functions: uart, hdl-language
• ULX3S build: ulx3s_fpga/ (makefile, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: bs/Bus/TagEngine.bs, TransactionToSubtransaction.bs (bus transaction-splitting IP)
• Tests: dirs: ./tests;1 tb/test files;tools: iverilog
• Notes: “More coming later” - early WIP, survey description is empty; Bluespec sim uses a BDPI C stub for UART.

thewbi__ulx3s

• Functions: board-hw, sdram, examples, education
• ULX3S build: blinky_lattice_diamond/ (blinky.v + .ldf/.lpf); sdram/ (testbench only, no top) (LPF: blinky_lattice_diamond/blinky.lpf, constraints_full.lpf)
• Reuse: none
• Tests: 1 tb/test files
• Notes: mostly a personal "how to set up Lattice Diamond for ULX3S" README with vendor PDFs; sdram/ has only a testbench and memory model, no working controller or top-level build

thezoq2__tinytapeout02

• Functions: hdl-language, gpio, education
• ULX3S build: top.sv (root, wraps Spade-compiled e_main), ulx3s_v20.lpf, swim.toml (build via the swim tool) (LPF: ULX3S (ulx3s_v20.lpf, LFE5U-85F CABGA381 per swim.toml); primary target is the TT02 ASIC shuttle (Sky130))
• Reuse: smolfpga/ submodule (TheZoq2/smolfpga, FETCHED@19076d84): reconfigurable cell/routing fabric, Spade+Verilog wrapper, cocotb-tested (smolfpga/src/test.py, self-checking assert on 7-seg segments); src/*.spade (main/cell/config_chain/routing): Spade-language reconfigurable logic cells, portable HDL, needs the (unfetched) spade compiler + swim to build
• Tests: dirs: ./test;tools: cocotb
• Notes: Last commit 2024-02-13 (git log -1). Hosted on GitLab (gitlab.com/TheZoq2/tinytapeout02), not GitHub. Submodules: smolfpga FETCHED@19076d84 (2022-11-13); spade and plugins/yosys_flamegraph NOT fetched, so the Spade top-level sources (src/*.spade) cannot actually be compiled from this clone. The repo’s own test/{cell,feedback,full,layer}.py are cocotb tests run via swim test (not a Makefile), self-checking with assert_eq (e.g. test/full.py:63); scan_make_tests.py only sees the smolfpga submodule’s Makefile since it looks for Makefiles, not swim.toml.

thorkn__layr_audio

• Functions: sound-chips
• ULX3S build: src/Makefile, src/ulx3s_v20_constraints.lpf, src/pll.v (LPF: src/ulx3s_v20_constraints.lpf (“ULX3S v20”))
• Reuse: src/sid.v: single-file behavioral SID6581 core (sid_voice/sdadc/filter submodules, top module sid), portable Verilog, no vendor primitives; src/pll.v: 25MHz->10MHz ECP5 PLL wrapper (EHXPLLL, needs porting off ECP5).
• Tests: none found
• Notes: Last commit 2026-05-14. README states main clock domain runs at 40MHz while pll.v divides 25MHz down to 10MHz (README wording is internally inconsistent). No LICENSE file in this repo; upstream CornN64/C64-SID-on-a-FPGA license not checked.

thorkn__spinalsynth_ulx3s

• Functions: board-hw, audio-dac, synth-audio, dsp-sdr, constraints
• ULX3S build: src/ (SpinalSynth.v generated top + Synth.v + pll_1.v/pll_2.v + ulx3s_v20.lpf; prebuilt .bit/.config committed) (LPF: src/ulx3s_v20.lpf)
• Reuse: src/Synth.v core (envelope generator + SVF filter ROMs) — reusable synth core, generated Verilog only (no SpinalHDL .scala source present)
• Tests: none found
• Notes: Only the generated Verilog is committed, not the SpinalHDL source that produced it, so the ‘spinalHDL’ claim can’t be verified from this clone; README explicitly notes most of it was AI-generated; a working bitstream is nonetheless committed.

thorkn__vexriscv-ulx3s-helloworld

• Functions: soc-cpu, uart, examples
• ULX3S build: ulx3s/ (Makefile, ulx3s_v20_constraints.lpf) (LPF: ulx3s_v20_constraints.lpf)
• Reuse: vexriscv/ (whole vendored VexRiscv/Murax SoC generator), hello_world/ (minimal C firmware + linker script)
• Tests: dirs: ./vexriscv/src/test;tools: verilator
• Notes: vexriscv/ is a large vendored copy of SpinalHDL’s VexRiscv project (1912 .class, 81 .scala); most repo bulk is upstream, not original.

thorkn__vexriscv-ulx3s-simple-plugin

• Functions: soc-cpu, jtag, uart, education, examples, board-hw, constraints
• ULX3S build: ulx3s/ (Makefile, ulx3s_v20_constraints.lpf) (LPF: ulx3s_v20_constraints.lpf)
• Reuse: vexriscv/ (VexRiscv CPU generator + custom instruction plugin), c_project/ (test firmware + GDB/JTAG flow)
• Tests: none found
• Notes: Tutorial-style repo walking through custom instruction + JTAG debug workflow end-to-end

thorkn__vga_clock_1

• Functions: video-composite, board-hw, hdl-language
• ULX3S build: ulx3s/ (Makefile + ulx3s.lpf), consumes generated VgaClock.v copied in from spinalHDL/ build output (LPF: ulx3s.lpf)
• Reuse: spinalHDL/src/spinal/vgaclock/VgaSyncGen.scala, ClockCounters.scala (reusable VGA timing generator components)
• Tests: none found
• Notes: Two-stage manual build (sbt generates Verilog, then must be manually copied into ulx3s/ before running make); README marks pin-wiring steps as ‘ToDo: Explain further’

thorkn__vga_pong

• Functions: video-composite, board-hw, hdl-language, examples
• ULX3S build: ulx3s/ (Makefile + ulx3s.lpf + committed VgaPong.v/VgaPong.bit/VgaPong.config build outputs) (LPF: ulx3s.lpf)
• Reuse: spinalHDL/src/spinal/vgapong/VgaSyncGen.scala, ClockCounters.scala (shared with vga_clock_1, reusable VGA timing gen)
• Tests: none found
• Notes: Prebuilt VgaPong.bit and .config committed alongside source; same two-stage manual build caveat as vga_clock_1

tinyfpga__tinyfpga-bootloader

• Functions: usb-device, bootloader, flash-spi
• ULX3S build: no ULX3S dir in this repo; nearest analogs boards/TinyFPGA_BX/{bootloader.v,Makefile} (iCE40) and boards/TinyFPGA_EX/{bootloader.v,diamond.ldf} (ECP5 12F, Diamond) (LPF: TinyFPGA BX/B2/EX, ICEBreaker_bitsy, Tomu/Fomu, Digilent Arty (boards/); not ULX3S)
• Reuse: common/{usb_fs_rx.v,usb_fs_tx.v,usb_fs_pe.v,usb_fs_in_pe.v,usb_fs_out_pe.v,usb_serial_ctrl_ep.v,usb_spi_bridge_ep.v,tinyfpga_bootloader.v}: portable full-speed USB device MAC/PHY + virtual-serial-to-SPI-flash bridge, no vendor primitives (per-board top e.g. boards/TinyFPGA_BX/bootloader.v uses SB_PLL40_CORE/SB_WARMBOOT/SB_IO; boards/TinyFPGA_EX/usb_pll_inst.v uses EHXPLLL for ECP5)
• Tests: dirs: ./tests;tools: iverilog
• Notes: last commit 2020-01-14 (git log); 29 self-checking tests; this is the ancestor lineage cited by emard__tinyfpga-bootloader-ulx3s, not a direct fork

tinyvision-ai-inc__pico-ice-sdk

• Functions: board-hw, soc-cpu, usb-device, flash-spi, uart, examples, bootloader
• ULX3S build: examples/ice_makefile_blinky/ (Makefile, top.sv, pico_ice.pcf); rtl/ (i2c_target.v, i2c_target_mac.v, pico_ice.pcf, pico2_ice.pcf) (LPF: pico-ice (RP2040+iCE40 UP5K) and pico2-ice (RP2350+iCE40 UP5K) (not ULX3S))
• Reuse: rtl/i2c_target.v + i2c_target_mac.v (portable iCE40 I2C-target core, plain Verilog, no SB_* primitives); examples/ice_makefile_iverilog_counter/ shows verilator+iverilog sim harness pattern reusable elsewhere
• Tests: tools: verilator,iverilog
• Notes: Repo is predominantly RP2040/RP2350 C SDK (pico-sdk based) for the host MCU; gateware is a thin slice (2 rtl/ cores + example FPGA projects), all targeting the on-board iCE40 UP5K, none ECP5. Uses pico-sdk and tinyuf2 submodules (frameworks, skipped per batch rule).

titouanc__fpga-scratchpad

• Functions: gpio, soc-cpu, board-hw
• ULX3S build: fpga_platform.py (litex_boards.platforms.ulx3s Platform, device=LFE5U-12F) + 01-HelloWorld.py/02-BinaryClock.py/03-CSR.py (call plat.build()) (LPF: ULX3S (LFE5U-12F, via litex_boards platform, revision unspecified))
• Reuse: fpga_platform.py: minimal ULX3S LiteX Platform wrapper adding user_button/user_led IO extensions on top of litex_boards’ own ulx3s.py - useful reference, but depends entirely on the external litex_boards package
• Tests: none found
• Notes: last commit 2021-03-25, stale (5+ years). Single-board project (ULX3S only, LFE5U-12F). Uses f32c-tools/ujprog for programming.

toasterllc__mdccode

• Functions: camera, sdram, sdcard, i2c, spi, board-hw
• ULX3S build: Code/ICE40/Pins.pcf, Code/ICE40/Synth.py + Synth.ys drive per-project Top.v under Code/ICE40/ICEApp*/ (e.g. ICEAppMSP, ICEAppSDReadoutSTM, ICEAppImgCaptureSTM); not ULX3S/ECP5 (LPF: Photon camera custom PCB “board/Rev5” (Code/ICE40/Pins.pcf comment: “Updated for board/Rev5 tag”; not ULX3S))
• Reuse: Code/ICE40/Shared/RAMController.v (701 lines): SDRAM controller FSM, uses SB_* iCE40 primitives - needs ECP5 port; SDController.v + ImgController.v/ImgI2CMaster.v: SD-card and image-sensor (parallel bus + I2C) controllers, SB_IO instantiations, mostly portable logic; AFIFO_zipcpu.v: vendored async FIFO from the ZipCPU project; Other/ExampleSDRAMControllers/*.v (3 files, incl. opencores Next186 sdram.v): reference-only, unused in build
• Tests: dirs: ./Sim;tools: iverilog
• Notes: Last commit 2026-03-20 (git log -1). Root Sim/ is LTspice analog power-circuit sim (.asc/.plt, 0 Verilog), not gateware - scan_tests.sh false positive; real sim is per-project Code/ICE40/Sim.sh (iverilog script), not a Makefile target. Code/ also holds MSP430 (MSPApp) and STM32 (STMApp/STMLoader) firmware, not catalogued in detail. Tools/, Other/ (except ExampleSDRAMControllers) deleted from clone intentionally. Img sensor clock 16 MHz.

tom7980__ulxws

• Functions: soc-cpu
• ULX3S build: NO ULX3S (LPF: none)
• Reuse: components/ (address_decoder, barrel_shifter, axi4 interfaces, skid_buffer), riscv/ (fetch/decode/execute pipeline stages)
• Tests: tools: verilator
• Notes: despite the name, no ULX3S board files, no .lpf, no README, no license; survey’s "unverified" flag was correct: bare RISC-V RTL sandbox, not an ULX3S build

tommythorn__bluespec_blink

• Functions: board-hw, examples, hdl-language
• ULX3S build: blink.bsv (compiled by bsc to mkBlink.v, committed) + ulx3s_v20.lpf, Makefile target ulx3s.bit (LPF: ulx3s_v20.lpf)
• Reuse: none (trivial blink demo, but useful as minimal Bluespec-on-ULX3S reference)
• Tests: none found
• Notes: Author notes design is ‘terrible at showing the strength of Bluespec’ but useful as a minimal working example; generated Verilog deliberately committed for people without the Bluespec toolchain

tomverbeure__ecp5_jtag

• Functions: jtag, board-hw, logic-analyzer
• ULX3S build: colorlight_i5/ (Makefile, ecp5_jtag.lpf); verilog/top.v is an alt hand-written top, commented out in the Makefile in favor of SpinalHDL-generated verilog/Ecp5JtagDemo.v (LPF: Colorlight i5 (ECP5-25F, CABGA381; not ULX3S). README links a ULX3S jtag_slave example (emard/ulx3s-misc) only as an external reference, no ULX3S code in this repo)
• Reuse: tb/src/JTAGG.v (JTAGG primitive testbench model), verilog/top.v (hand-written JTAGG instantiation) - ECP5 primitive usage, portable to ULX3S with pin remap
• Tests: dirs: ./tb;tools: iverilog
• Notes: Reverse-engineering write-up (JTDI registered on JTCK posedge, TDO on JTCK negedge); traces/ holds Saleae logic-analyzer capture files (.sal) as evidence, not simulation output

toni3141__rastericer

• Functions: gpu, oled-lcd
• ULX3S build: rtl/top/iCE40up5k/ (Makefile, rasterizer_up5k.pcf, topUP5k.v); also rtl/top/Xilinx/ (Vivado, Arty A7) and rtl/top/Verilator/ (simulation) (LPF: iCEBreaker (iCE40 UP5K, SG48) + Digilent Arty A7-35 (Xilinx Artix-7), PMOD command/display interface (not ULX3S))
• Reuse: rtl/RasteriCEr/.v (Rasterizer, FragmentPipeline, CommandParser, Serial2AXIS, TextureBuffer - mostly portable Verilog), rtl/Display/DisplayControllerSpi.v + rtl/3rdParty/SPI_Slave.v,sfifo.v (generic SPI IP, portable); lib/gl/.hpp (portable C++ driver)
• Tests: tools: verilator
• Notes: Verified GPLv3 from LICENSE + file headers. Mature, documented (spec PDFs, Qt unit test viewer, working Tuxracer demo screenshots). No prebuilt bitstream. FragmentPipelineIce40Wrapper.v (SB_MAC16), SinglePortRam32k.v (SB_SPRAM256KA), topUP5k.v (SB_HFOSC) need ECP5 substitutes for ULX3S.

trabucayre__openfpgaloader

• Functions: programmer-tool, bootloader
• ULX3S build: src/board.hpp (ulx3s, ulx3s_dfu, ulx3s_esp, ulx4m_dfu) (LPF: n/a)
• Reuse: -b ulx3s / ulx3s_dfu
• Tests: none found
• Notes: recommended programmer

tristanitschner__ulx3s-examples

• Functions: uart, audio-dac, synth-audio, examples
• ULX3S build: hello-world/, sound-dds/, sound-wave/ (root) (LPF: ulx3s_v20.lpf (each example))
• Reuse: sound-wave/delta_sigma.v (delta-sigma DAC), sound-dds/sound.v (DDS waveform generator)
• Tests: 1 tb/test files;tools: iverilog
• Notes: clean small independent examples, nothing surprising

tucanae47__litex_etpu

• Functions: soc-cpu, ml-accelerator, bus-fabric, wishbone-bus
• ULX3S build: fpga/litex/etpu_soc.py, fpga/litex/Makefile (litex_boards.platforms.radiona_ulx3s; upload via openFPGALoader –board=ulx3s) (LPF: radiona_ulx3s LiteX platform (revision unspecified))
• Reuse: design/etpu/sysa_pe.v: 8x8->16-bit systolic-array multiply-accumulate PE (pe module); design/etpu/{npu_wb,edu_tpu}.v: Wishbone-attached NPU wrapper (CERN-OHL-P-2.0 on npu_wb.v). Plain Verilog, no vendor primitives, ported from a Caravel/Wishbone ASIC context.
• Tests: tools: cocotb
• Notes: Last commit 2022-12-23. requirements.txt lists cocotb/cocotbext-wishbone as LiteX deps but no testbenches for edu_tpu/npu_wb/sysa_pe are present in this pruned clone; firmware/build.make referenced by the Makefile is also absent.

tucanae47__ulx3s-experiments

• Functions: camera, oled-lcd, video-input, board-hw, constraints
• ULX3S build: cam/ (ov7670_top_ctrl.v, ulx3s_v20.lpf, apio.ini board=ulx3s-85f), oled1351/ (ulx3s_v20.lpf) (LPF: cam/ulx3s_v20.lpf, oled1351/ulx3s_v20.lpf)
• Reuse: cam/ov7670_capture.v + sccb_master.v camera-capture pipeline; oled_sdd1331.v OLED driver
• Tests: 1 tb/test files;tools: cocotb,verilator,iverilog
• Notes: small personal-experiment quality repo (few files, one-line README)

tvelliott__dsp_ice

• Functions: audio-dac, audio-i2s, synth-audio, adc, spi, ethernet, dsp-sdr, board-hw
• ULX3S build: NOT ULX3S: firmware/fpga/src/Makefile, firmware/fpga/src/fpga_top.v, firmware/fpga/src/pinout.pcf (LPF: custom “DSP_ICE” board (iCE40HX8K-CT256 + STM32F417, not ULX3S))
• Reuse: firmware/fpga/src/spi_master.v (SPI master core), firmware/fpga/src/fpga_top.v (FSMC 16-bit MCU<->FPGA memory-mapped bus + 8-channel audio synth + LTC1420 ADC glue) – plain Verilog, no vendor primitives seen; hw_modules/ltc1420_adc/ (ADC daughtercard schematic+BOM)
• Tests: none found
• Notes: last commit 2017-10-03; goal was an SDR with swappable RF front-ends per README; prebuilt firmware/build_image/main_image_0x8000000.bin and fpga_image.h (compressed FPGA config baked into MCU firmware) checked in; eagle/+gerber/+BOM/ hold the full 4-layer PCB; no ULX3S relevance beyond same iCE40 HX8K family

ulixxe__usb_cdc

• Functions: usb-device, examples
• ULX3S build: examples/Fomu/OSS_CAD_Suite/ (Makefile, pcf/fomu-*.pcf); examples/TinyFPGA-BX/OSS_CAD_Suite/ (Makefile, pins.pcf); core in usb_cdc/ (LPF: Fomu evt1/evt2/evt3/hacker/pvt and TinyFPGA-BX (not ULX3S))
• Reuse: usb_cdc/*.v (bulk_endp.v, ctrl_endp.v, in_fifo.v, out_fifo.v, phy_rx.v, phy_tx.v, sie.v, usb_cdc.v): plain Verilog FS USB CDC-ACM core, README claims no EBR use, portable
• Tests: tools: verilator,iverilog
• Notes: README claims the core avoids vendor primitives/EBR so should be portable; only verified built against iCE40 examples here; ULX3S lacks a native USB device PHY so would need external bit-bang wiring/level shifting

ultraembedded__core_ddr3_controller

• Functions: ddr3, constraints
• ULX3S build: not ULX3S; examples/ecpix_ecp5/ (top.v, fpga.lpf, ecp5pll.sv, reset_gen.v), no build script; also examples/arty_a7/ (LPF: LambdaConcept ECPIX-5 (examples/ecpix_ecp5, revision unstated); Digilent Arty A7 Rev B (examples/arty_a7/arty_revb.xdc))
• Reuse: examples/ecpix_ecp5/ecp5pll.sv (EMARD parametric ECP5 PLL, BSD-2-Clause header, portable, reused by many ULX3S projects); src_v/{ddr3_core.v,ddr3_axi.v,ddr3_axi_pmem.v,ddr3_dfi_seq.v,ddr3_axi_retime.v} (vendor-agnostic AXI4 DDR3 core, DFI interface) + src_v/phy/ecp5/ddr3_dfi_phy.v (ECP5-specific PHY)
• Tests: dirs: ./tb
• Notes: Last commit 2021-10-10. README claims tested on ECPIX-5 + Arty A7, boots Linux with the core stressed by video framebuffer accesses. No Makefile for either example (source distribution). Caveat (README): ECP5 PHY read-capture aligned to internal clock, not DQS - “could do with fixing”. 637 GitHub stars. maxhpc/ecpix-5 vendors the same upstream via its own submodule (not fetched there since this slug is cloned).

ultraembedded__ecpix-5

• Functions: soc-cpu, video-dvi, uart, constraints, board-hw, gpio, spi, timer, debug-bridge
• ULX3S build: src/top/ (top.v, fpga.lpf); src/soc/ (fpga_top.v, riscv_tcm_top.v); src/video/ (dvi_fb_it6613.v); no Makefile; prebuilt bitstream/fpga.bit (LPF: ECPiX-5 (not ULX3S; revision unstated in source))
• Reuse: src/top/ecp5pll.sv (portable PLL, EMARD source used on ULX3S); src/video/dvi_framebuffer_fifo.v (board-agnostic FIFO; IT6613 driver itself not reusable); src/core_soc/src_v/{gpio,spi_lite,timer,irq_ctrl,uart_lite}.v (small peripherals, portable); src/dbg_bridge/src_v/dbg_bridge*.v (UART-to-AXI debug bridge, portable); src/riscv/core/riscv/ (biriscv-family RISC-V core, needs AXI wrapper)
• Tests: none found
• Notes: No LICENSE file and no build script in own repo. Only prebuilt bitstream/fpga.bit included. clk is 100MHz per fpga.lpf, not ULX3S’s 25MHz; IT6613 HDMI encoder is board-specific hw ULX3S lacks. Submodules fetched 2026-09-27: src/core_soc@9fceff0 (GPL-2.0), src/dbg_bridge@a601c65 (LGPL-2.1), src/riscv@c17cfba (BSD-style, ultraembedded).

ultraembedded__orangecrab

• Functions: ddr3, board-hw, constraints
• ULX3S build: ddr_test/src_v/ (top.v, orangecrab_r0_2.lpf); no Makefile; prebuilt ddr_test/bitstreams/ddr_test_r0_2.dfu (LPF: OrangeCrab r0.2 (not ULX3S))
• Reuse: ddr_test/src_v/ecp5pll.sv (by EMARD, same author as ULX3S board files - portable PLL wrapper, drop-in); ddr3axi*.v + ddr3_dfi*.v DDR3 AXI controller (Apache-2.0; ECP5 DDR3 PHY logic, NOT usable for ULX3S’s SDR SDRAM - only for DDR3 ECP5 boards/add-ons)
• Tests: none found
• Notes: Verified: Apache-2.0 headers in .v files, LPF targets OrangeCrab r0.2. No build script (no Makefile) in this shallow clone - only prebuilt bitstreams/ddr_test_r0_2.dfu included, toolchain invocation unconfirmed. Single-project repo.

ulx3s__anotherworld_fpga

• Functions: examples
• ULX3S build: NO ULX3S (iCE40 Go Board) (LPF: goboard.pcf)
• Reuse: none
• Tests: 1 tb/test files
• Notes: no ULX3S build despite ulx3s org

ulx3s__apple2fpga

• Functions: retro-computer, video-dvi, usb-host, ps2, esp32
• ULX3S build: proj/lattice/ulx3s/ (LPF: ulx3s_v20_difgpdi.lpf)
• Reuse: same, older
• Tests: none found
• Notes: use emard copy

ulx3s__blink

• Functions: board-hw, constraints, examples
• ULX3S build: repo root: blinky.v, blinky.ys, Makefile, ulx3s_v20.lpf (LPF: ulx3s_v20.lpf)
• Reuse: blinky.v minimal LED blink top
• Tests: tools: verilator
• Notes: Prebuilt bitstreams for 12f/45f/85f shipped; simplest possible starting point

ulx3s__fpga-odysseus

• Functions: education, examples, video-dvi, audio-dac, uart, oled-lcd, soc-cpu, retro-computer, retro-arcade, led-matrix
• ULX3S build: tutorials/NN-*/ (apio), projects/LedPanel (LPF: tutorials/ulx3s.lpf)
• Reuse: 04-Video vga2dvid/tmds, uart_rx/tx, grom_cpu, i8080 altair, picorv32 attosoc
• Tests: 1 tb/test files
• Notes: slides in presentation/

ulx3s__galaksija

• Functions: retro-computer, video-dvi, uart
• ULX3S build: proj/lattice/ulx3s-universal-make/ (LPF: ulx3s_v20_segpdi.lpf)
• Reuse: tv80
• Tests: none found
• Notes: only reason: GateMate port

ulx3s__hazard3

• Functions: soc-cpu, board-hw, jtag, uart, sdram, video-dvi, ulx4m, spi, bus-fabric
• ULX3S build: example_soc/synth/ULX3S.mk, ULX3S_12F.mk, fpga_ulx3s.lpf; ULX4M_LD_85F.mk, ULX4M_LS_85F.mk, fpga_ulx4m_ld*.lpf (LPF: example_soc/synth/fpga_ulx3s.lpf, fpga_ulx4m_ld.lpf/_v002.lpf, fpga_ulx4m_ls.lpf)
• Reuse: hdl/ (whole Hazard3 CPU core: core.v, csr.v, pmp.v, debug/), example_soc/soc (SoC integration), doc/ulx3s-ulx4m-build-and-validation.md; example_soc/libfpga/busfabric/ (AHB-Lite crossbar/arbiter/APB bridge), video/dvi_tx_parallel.v+tmds_encode.v, peris/uart/, peris/spi/ (WTFPL, standalone reusable)
• Tests: dirs: ./test ./test/sim ./example_soc/libfpga/test;tools: verilator
• Notes: well-documented, actively maintained fork with an explicit ULX3S/ULX4M-LD support matrix (bitstream IDCODE table, clock/memory profile); sibling ulx3s__hazard3-doom repo builds Doom on top of this. Submodules fetched 2026-09-27: example_soc/libfpga@2c43024.

ulx3s__hazard3-doom

• Functions: soc-cpu, bootloader, video-dvi, uart, jtag, multi-board, ulx4m, examples
• ULX3S build: bootloader/data/*.lpf (top-ulx3s-v20/v314/v317.lpf, top-ulx4m-v002.lpf); prebuilt bin/fpga_ulx3s_{12f,85f}.bit, bin/fpga_ulx4m_ld.bit (LPF: bootloader/data/top-ulx3s-v20.lpf, top-ulx3s-v314.lpf, top-ulx3s-v317.lpf, top-ulx4m-v002.lpf, top-had2019-badge.lpf)
• Reuse: bootloader/ resident monitor + UART image/WAD loaders (reusable loader for other ULX3S/ULX4M RISC-V projects); doom/upload-doom-image.py, upload-wad.py host tools
• Tests: dirs: ./tests;2 tb/test files;tools: verilator,iverilog
• Notes: actively maintained (pushed 2026-09-21, days before this survey); CI-built bitstreams for both ULX3S 12F/85F and ULX4M-LD; well-documented multi-license project with its own docs site

ulx3s__tt-support-tools

• Functions: toolchain, constraints, education
• ULX3S build: fpga/ulx3s/{tt_fpga_top_ulx3s.v,ulx3s_v20.lpf,ulx3s_v17patch.lpf,ulx3s_v314.lpf,ulx3s_v316.lpf}; used by a GitHub Action, not built by a Makefile in this repo (LPF: ULX3S v1.7/v2.0/v3.14/v3.16-3.18 and ULX4M-LD/ULX4M-LS (fpga/ulx3s/, fpga/ulx4m/); not itself a board, this is Tiny Tapeout’s shuttle-building/precheck toolchain)
• Reuse: fpga/ulx3s/{tt_fpga_top_ulx3s.v,ulx3s_v20/v314/v316/v17patch.lpf}: portable ULX3S top-module wrapper + constraint set for any Tiny Tapeout/Wokwi project (consumed by the fpga GH Action, fpga/ulx3s/README.md); testing/src-tpl/{Makefile,test.py,lib/testutils/truthtable.py}: reusable cocotb markdown-truth-table test harness template
• Tests: 2 tb/test files;tools: cocotb
• Notes: Last commit 2026-09-03 (git log -1). Fork of TinyTapeout/tt-support-tools on branch experimental (log: “Merge with upstream”), adding fpga/ulx3s and fpga/ulx4m board support plus the fpga GH Action. This is a Python tooling repo (config.py/precheck/documentation.py), not itself a gateware design; no submodules found.

ulx3s__ulx3s-adda

• Functions: adc, audio-dac, adapter-board
• ULX3S build: root (LPF: ulx3s_v20.lpf)
• Reuse: same
• Tests: none found
• Notes: duplicate

ulx3s__ulx3s-examples

• Functions: examples, education, esp32, constraints, toolchain
• ULX3S build: blinky/OpenSource, passthru/{OpenSource,Diamond,DiamondVerilog}, doc/constraints (LPF: ulx3s_v20.lpf)
• Reuse: passthru.v/.vhd, blinky.v, WSL toolchain script
• Tests: tools: verilator
• Notes: mostly docs; 2020

ulx3s__ulx3s-saxonsoc

• Functions: soc-cpu, linux, sdram, bootloader, toolchain
• ULX3S build: scripts/build.sh (LPF: SaxonSoc Ulx3s BSP)
• Reuse: build.sh recipe
• Tests: none found
• Notes: stale 2020; dead bintray

ulx3s__ulx3s_zx81

• Functions: retro-computer, video-dvi, ps2
• ULX3S build: ulx3s/ (LPF: ulx3s_zx81.lpf)
• Reuse: use lawrie copy
• Tests: none found
• Notes: 2020

uttamcoomar__mac-units-for-various-number-formats

• Functions: uart, dsp-sdr, NEW:mac-unit
• ULX3S build: int8/{Makefile,top.v,uart_rx.v,uart_tx.v,ulx3s.lpf,mac_int8.v} (same layout repeated in bf16/,fp16/,lns8/,mxfp8/,posit8/) (LPF: ULX3S v3.x (README: "ulx3s.lpf: Pin constraints for ULX3S v3.x (ECP5 85F)"))
• Reuse: int8/{uart_rx.v,uart_tx.v}: small self-contained 115200-8N1 UART pair, portable, reused identically across all six number-format subprojects; each mac_.v is MyHDL-generated and format-specific, not generically reusable
• Tests: 12 tb/test files
• Notes: last commit 2026-03-13. Single-board project (ULX3S only, no second board found despite the multi-board survey group); each subdirectory has a tb_mac_.v testbench and test_mac_.py UART host-side functional test.

uttamcoomar__nn_digits

• Functions: ml-accelerator, uart
• ULX3S build: rtl/{top.v,mlp_accel.v}, syn/{synth.ys,ulx3s.lpf} (LPF: syn/ulx3s.lpf)
• Reuse: rtl/mlp_accel.v: self-contained MLP inference core (weights loaded from tests/sim/infer/hex/*.hex); self-checking cocotb test (tests/test_inference.py) compares HW output to a Python reference
• Tests: dirs: ./tests ./tests/sim;2 tb/test files;tools: cocotb,iverilog
• Notes: Last commit 2026-03-23. Listed in the multi-board group-C survey but this clone appears to be ULX3S-only (no other board target found) - flagged as odd, catalogued as given.

victor-fisyuk__voodoo-fpga-public

• Functions: video-dvi, sdram, retro-console, gpu
• ULX3S build: NO ULX3S — repo contains only README.md and a screenshots/ folder (one photo ulx3s.jpg of the board); no HDL/RTL source, no .lpf, no build files at all (LPF: none (no constraint files present))
• Reuse: none - no source code available in this clone to reuse
• Tests: none found
• Notes: This ‘public’ repo is source-free: it exists to show YouTube demo videos/screenshots of a Voodoo-1 FPGA reimplementation running on ULX3S, but ships no gateware; likely a promotional mirror of a private repo

vladov3000__ulx3s

• Functions: video-dvi, soc-cpu, board-hw, toolchain
• ULX3S build: modules/Top.sv + ulx3s.lpf, built via build.py (yosys scripts/synthesize.ys -> nextpnr-ecp5 –85k -> ecppack) (LPF: ulx3s.lpf)
• Reuse: modules/Cpu.sv, modules/Dvi.sv, modules/TmdsEncoder.sv, modules/Memory.sv (custom CPU+DVI core), code/assembler/ (standalone assembler for the custom ISA), code/cxxrtl (vendored YosysHQ cxxrtl headers)
• Tests: none found
• Notes: No README content; project quality only inferable from code structure; includes a full custom assembler and cxxrtl simulator built from scratch, unusually complete tooling for a tiny/unstarred repo

vmware-archive__cascade

• Functions: uart, board-hw, hdl-language
• ULX3S build: share/cascade/ulx3s/{harness.v,root32.v,uart.v,uart_tx.v,uart_rx.v,build_ulx3s_32.sh,ulx3s_v20.lpf} (LPF: share/cascade/ulx3s/ulx3s_v20.lpf)
• Reuse: share/cascade/ulx3s/{uart.v,uart_tx.v,uart_rx.v}: small self-contained UART used as the ULX3S host link; root32.v/harness.v: fabric harness wrapper mapping Cascade’s virtual compute/LEDs onto the board
• Tests: dirs: ./share/cascade/test ./test;tools: verilator
• Notes: Last commit 2021-07-01 (VMware archived the project, repo renamed vmware-archive). README.md:419: ‘Cascade does not currently support any of the I/O peripherals on the ULX3S’. No submodules.

volnirr__verilog-uart

• Functions: uart, examples
• ULX3S build: rtl/uart_rx.v, rtl/uart_tx.v + ulx3s.lpf (no synth Makefile/script found; README documents build with yosys/nextpnr/openFPGALoader in prose) (LPF: ulx3s.lpf)
• Reuse: rtl/uart_rx.v, rtl/uart_tx.v (clean, well-specified, board-independent UART core — good reuse candidate)
• Tests: dirs: ./tb;2 tb/test files
• Notes: Well-specified README (exact baud error, framing/noise handling) despite no committed build script; small focused reusable core

voltcyclone__hurra-fpga

• Functions: usb-host, usb-device, spi
• ULX3S build: src/hurra_cynthion/gateware.py (“Cynthion r1.4 top level for the bounded mouse host”; built via the Amaranth/oss-cad-suite flow in docker/synth.sh + docker/pnr.sh) (LPF: Cynthion r1.4 only (per gateware.py docstring; platform class comes from the external cynthion package))
• Reuse: src/hurra_cynthion/{host.py,device.py,injection.py,injection_map.py,descriptor_export.py,debug_block.py,spi_link.py} (bounded USB1.1/FS host + device-clone Amaranth core, ~1057-line single-file gateware.py top level, portable, no ECP5 primitives seen). firmware/{ch32h417,mcxn947,teensy_hs_mouse}/ are MCU firmware, not FPGA gateware - mention only.
• Tests: dirs: ./firmware/ch32h417/test ./firmware/mcxn947/test ./tests;31 tb/test files
• Notes: Verified from source. Last commit 2026-09-19 (per survey; clone @0a050ad254). usb domain = 60MHz (aux_phy ULPI clock, per build_env.py docstring). Active development with detailed timing-closure notes in build_env.py about the mandatory nextpnr --placer-heap-timingweight 60 flag. Bulk of the repo by file count is MCU firmware for three chips (CH32H417, MCXN947, Teensy/imxrt) - mention only. No submodules found.

voltcyclone__hurricanefpga

• Functions: usb-host, debug-bridge, uart
• ULX3S build: HDL/Makefile + HDL/hardware/rtl/top.v + HDL/hardware/constraints/cynthion_pins.lpf (make all -> yosys/nextpnr-ecp5/ecppack); legacy/src/backend/top.py is an older Amaranth version of the same idea (LPF: Cynthion r1.4 only (HDL/hardware/constraints/cynthion_pins.lpf, LFE5U-12F-8BG256C))
• Reuse: HDL/hardware/rtl/usb_interface/ (usb_host_arbiter.v, usb_enumerator.v, usb_transaction_engine.v, usb_token_generator.v, usb_sof_generator.v, usb_reset_controller.v - plain synthesizable Verilog, no vendor primitives); usb_engines/{usb_hid_keyboard_engine.v,usb_hid_mouse_engine.v} (HID report injection); usb_proxy/ (sniffer/passthrough: usb_monitor.v, packet_proxy.v, usb_injection_mux.v). CAVEAT: top.v’s PLL (pll_60_to_240) is an unimplemented placeholder and the lpf’s own comment admits its USB pin LOCATEs are provisional, not the real ULPI pins.
• Tests: dirs: ./HDL/hardware/testbenches;11 tb/test files;tools: iverilog
• Notes: Verified from source. Last commit 2026-04-23 (per survey; this clone @6f0b109cf0). 60MHz oscillator (A8). Two source-verified caveats: (1) HDL/hardware/constraints/cynthion_pins.lpf comment admits its USB pin LOCATEs are placeholders mapped to ULPI data pins, not real D+/D-; (2) top.v’s pll_60_to_240 module is an explicit unimplemented placeholder (assign clkout1 = clkin; // Would normally be 120 MHz), so the 120/240MHz fast-path domains used throughout the design do not actually exist in this build - README claims of a working USB sniffer/host are unverified against this. legacy/ holds an older Amaranth (Python) version. No submodules.

vyges__fast-fourier-transform-ip

• Functions: dsp, NEW:fft, bus-fabric
• ULX3S build: flow/fpga/Makefile + flow/fpga/openfpga/Makefile (TOP_MODULE=fft_top); flow/fpga/openfpga/constraints/hx8k-ct256.pcf (default ice40); ecp5_synth/ecp5_pnr targets use nextpnr-ecp5 –25k, no lpf file (LPF: generic iCE40 HX8K CT256 breakout (default) + generic ECP5 25F (nextpnr-ecp5 –25k, no lpf) + Xilinx 7-series (unconstrained); not ULX3S)
• Reuse: rtl/fft_fft_{top,engine,control}.sv + fft_rescale_unit.sv + fft_scale_factor_tracker.sv + fft_twiddle_rom.sv: configurable 256-4096-pt radix-2 DIF FFT accelerator (APB/AXI register interface + optional bus-master DMA mode), automatic BFP rescale; pure SV, no vendor primitives; open iCE40/ECP5/Xilinx flows provided but several test Makefiles are broken (see notes)
• Tests: dirs: ./test ./tb ./simulation;18 tb/test files;tools: cocotb,verilator,iverilog
• Notes: Last commit 2026-08-08. Apache-2.0. Default flow target is iCE40 hx8k-ct256; ecp5synth/ecp5_pnr targets exist (nextpnr-ecp5 –25k). Root Makefile.test and tb/cocotb/Makefile hardcode stale unprefixed filenames (memory_interface.sv, twiddle_rom.sv, fft_top.sv, fft_engine.sv) that no longer exist in rtl/ after a rename to fft-prefixed files (e.g. fft_fft_engine.sv) - those specific test targets fail before simulating; tb/sv_tb/Makefile (glob $(RTL_DIR)/*.sv) is unaffected.

w531t4__fpga_led_display

• Functions: led-matrix, uart, multi-board, board-hw, constraints
• ULX3S build: src/top_ulx3s.sv + src/constraints/ulx3s_v316.lpf (BOARD=ulx3s make target) (LPF: src/constraints/ulx3s_v316.lpf (LICENSES/LicenseRef-EMARD.txt notes the file is derived from EMARD’s ULX3S constraint file))
• Reuse: src/main.sv board-agnostic display_core logic (reusable across boards); gamma/double-buffer/watchdog features
• Tests: dirs: ./src/testbenches;39 tb/test files;tools: verilator
• Notes: professionally engineered repo (pre-commit hooks, verible lint, AGENTS.md, REUSE.toml SPDX compliance); ULX3S is the secondary board — “panelith” (a custom board) is the default BOARD target

whitequark__yumewatari

• Functions: serdes-pcie-sata, NEW:pcie
• ULX3S build: yumewatari/gateware/platform/lattice_ecp5.py (LatticeECP5PCIeSERDES wrapper), yumewatari/gateware/phy.py (PCIePHY top), yumewatari/testbench/ltssm.py (simulation top). No .lpf or top-level build script in this repo; ispclock/.jed configure the board’s PCIe clock synthesizer. (LPF: Lattice ECP5-5G Versa (via external migen versaecp55g platform + ispclock/.jed; no local .lpf/constraint file))
• Reuse: yumewatari/gateware/serdes.py (PCIeSERDESInterface/Aligner, 8b10b K/D helpers) and phy.py (PCIePHY, PIPE-like) are board-agnostic Migen, later reused (0BSD) inside katsuo-pcie’s ecp5_serdes.py. yumewatari/gateware/platform/lattice_ecp5.py: DCUA/EXTREFB wrapper, portable to any LFE5UM/LFE5UM5G part.
• Tests: dirs: ./yumewatari/test ./yumewatari/testbench;4 tb/test files
• Notes: Dormant since 2019-04-02 (last commit; confirmed by git log). No README in this clone. whitequark’s litepcie issue #20 comment says the ECP5 SERDES was made to lock onto the PCIe bit stream; predecessor of the (also experimental) ECP5-PCIe project. No submodules, no setup.py/pyproject (not packaged as a library).

wifiboy__ok-ice40pro

• Functions: education, soc-cpu, retro-computer, video-vga, uart, flash-spi, oled-lcd, audio-dac, gamepad, jtag
• ULX3S build: ok-j1a-forth-soc-src/ (Makefile, okice40pro.pcf); ok-nes-vga-src/ (Makefile, okice40_pro.pcf); ok-rv32-soc-src/ (Makefile, okice40pro.pcf); ok-tutorials-src/01..10 (apio.ini + Makefile each) (LPF: OK:iCE40Pro custom console PCB v1.3 (iCE40 UltraPlus 5K, SG48), documented via docs/hw/okice40-pro-v1.3.pdf only, no schematic/KiCad source (not ULX3S))
• Reuse: ok-rv32-soc-src/picorv32.v (portable RV32 core), wb_bus.v/wb_master.v (Wishbone, portable), c-src/* firmware; ok-nes-vga-src/nes.v,cpu.v,ppu.v,apu.v (portable NES core logic); ok-j1a-forth-soc-src/j1.v (J1 CPU, mostly portable; j1a.v embeds SB_RAM2048x2 iCE40 BRAM model)
• Tests: tools: iverilog
• Notes: Verified MIT root license; NES core files carry Strigeus/Shah GPL headers and picorv32.v its own ISC-style license - mixed licensing vs repo’s MIT. Prebuilt .bin bitstreams included for all 3 SoCs + demo ROMs. SB_SPRAM256KA/SB_RGBA_DRV/SB_SPI/SB_RAM40_4K/SB_RAM2048 need ECP5 substitution.

williamsharkey__pruned-sha256-miner

• Functions: crypto
• ULX3S build: constraints/ulx3s-miner-v20.lpf, rtl/factory75_pruned.sv (module ulx3s_factory75); run.py drives the flow but is NOT runnable as cloned (see notes) (LPF: constraints/ulx3s-miner-v20.lpf)
• Reuse: rtl/factory75_pruned.sv: pruned 64-round unrolled double-SHA256 pipeline (H0-H6 dropped in the final round, single hit output bit), portable SV, no vendor primitives; rtl/formal75.sv: per-stage miter for SAT-based equivalence checking against the unpruned factory75.sv.
• Tests: 5 tb/test files
• Notes: Last commit 2026-08-13. README claims 46.7MHz/46.7MH/s post-PnR and 61,830 LUTs, but run.py (the only flow driver) references a sibling toolchain directory and scripts/copies/logs/mapped/routes/ paths that do not exist in this clone – no logs, bitstream, or report are committed. These numbers are claimed, not reproducible or evidenced in this clone.

wren6991__hazard3

• Functions: soc-cpu, uart, jtag, board-hw, constraints
• ULX3S build: example_soc/synth/{ULX3S.mk,fpga_ulx3s.lpf}; example_soc/fpga/fpga_ulx3s.v(+.f) (LPF: fpga_ulx3s.lpf)
• Reuse: rtl/ Hazard3 core itself is a reusable RV32 processor (also used in Wren6991/Hazard3-SWD-SoC)
• Tests: dirs: ./test ./test/sim;tools: verilator
• Notes: companion repo Wren6991/Hazard3-SWD-SoC (ULX3S SWD variant) not cloned here; DEVICE targets ECP5-5G

wren6991__hazard3-swd-soc

• Functions: soc-cpu, jtag, uart, programmer-tool, sdram, bus-fabric, swd-debug
• ULX3S build: synth/ (Makefile, fpga_ulx3s.lpf) + hdl/fpga/fpga_ulx3s.v (LPF: synth/fpga_ulx3s.lpf)
• Reuse: lib/libfpga/busfabric/ (AHB-Lite crossbar/arbiter), lib/libfpga/sdram/ahbl_sdram.v (AHB SDRAM ctrl, WTFPL), lib/opendap/hdl/opendap_sw_dp.v + opendap_mem_ap_apb.v (ADIv5.2 SW-DP + Mem-AP, CC0) - both standalone reusable IP blocks
• Tests: dirs: ./lib/libfpga/test ./lib/opendap/test
• Notes: README literally says “How do I program it: No idea, good luck, have fun” - experimental/WIP debug testbench, not a finished product. Submodules fetched 2026-09-27: lib/libfpga@061d96d, lib/opendap@0fdf995.

wren6991__riscboy

• Functions: soc-cpu, gpu, video-vga, audio-dac, uart, gpio, bus-fabric, sram, bootloader, constraints, board-hw
• ULX3S build: synth/riscboy_ulx3s.lpf, synth/ULX3S.mk (DEVICE=um5g-85k PACKAGE=CABGA381), synth/Makefile, hdl/riscboy_fpga/riscboy_fpga_ulx3s.f, hdl/riscboy_fpga/ (also has *_hx8kevn and *_icebreaker variants) (LPF: ULX3S (25F/45F/85F board family, built here for 85F um5g-85k CABGA381); iCE40-HX8K-EVN (Lattice eval board, not ULX3S); iCEBreaker (UP5K, not ULX3S))
• Reuse: hdl/hazard5/ (fetched submodule, Wren6991/Hazard5): standalone RV32IMC CPU core with AHB-Lite bus, board-agnostic Verilog, reusable on ECP5 as-is; hdl/libfpga/ (fetched submodule, Wren6991/libfpga): busfabric/cdc/mem/sdram/peris building blocks, portable (has its own sdram/ AHB controller); hdl/sram_ctrl/*.v: async 16-bit SRAM controller for the PPU/CPU, portable design note in-file
• Tests: dirs: ./hdl/hazard5/test ./hdl/libfpga/test ./test ./test/ppu/tb ./test/system_cxxrtl/tb;2 tb/test files
• Notes: Last commit 2025-12-01 (repo active); submodules hdl/hazard5@b402a6b and hdl/libfpga@9e39280 are fetched/populated (16+66 .v files); test/execution/riscv_compliance/riscv-compliance, test/riscv-formal, and top-level scripts (fpgascripts, holds synth_ecp5.mk/synth_ice40.mk/sim.mk) are NOT fetched (empty dirs) - so neither the ULX3S/HX8k build flow nor the riscv-compliance/riscv-formal test targets can actually run from this clone without fetching scripts

wren6991__smoldvi

• Functions: video-dvi
• ULX3S build: synth/Icebreaker.mk (+ smoldvi_icebreaker.pcf), synth/Icestick.mk, synth/Icesugar.mk, synth/TinyFPGA_BX.mk; core in hdl/smoldvi/ (LPF: iCEBreaker, iCEstick, iCESugar, TinyFPGA BX (not ULX3S))
• Reuse: hdl/smoldvi/*.v (smoldvi.v top, smoldvi_tmds_encode.v TMDS encoder ~20 LUTs/lane, smoldvi_timing.v, smoldvi_serialiser.v, smoldvi_fast_gearbox.v, smoldvi_clock_driver.v): author states plain, portable Verilog
• Tests: none found
• Notes: author explicitly says the hdl/smoldvi files are portable; needs an external ddr_out DDR-output module per platform (currently SB_IO/FPGA_ICE40 via libfpga submodule, not fetched here); ULX3S/ECP5 port needs an ODDRX1F-based ddr_out and a 25.2MHz-derived PLL

wuxx__colorlight-fpga-projects

• Functions: soc-cpu, video-dvi, oled-lcd, uart, sdram, ethernet, jtag, constraints
• ULX3S build: varies per example, e.g. src/i5/blink/ (Makefile, blink.lpf), src/i9/blink/ (Makefile, blink.lpf); several i5 examples reuse ulx3s_v20_segpdi.lpf / ULX3S_25F.ys from the ULX3S-Blinky project (LPF: Colorlight i5-v7.0, i9-v7.1/7.2, i9plus-v6.1, 5a-75b-v7.0 breakout boards (not ULX3S; i5/i9/5a-75b are ECP5, i9plus is Xilinx))
• Reuse: src/i5/hdmi_test_pattern/llhdmi.v + pattern.v (ECP5 DVI test-pattern generator, already paired with a ULX3S LPF variant); src/i5/picosoc/*.v (picorv32 attosoc SoC, portable); src/i5/oled_ssd1331/oled_video.v (SSD1331 OLED driver)
• Tests: tools: verilator,iverilog
• Notes: Verified from source (Makefiles, README). Large fraction of demo/ is prebuilt .bit/.svf bitstreams, not source. Board pin sets are Colorlight-specific (25MHz osc, different LPF); the i5 hdmi_test_pattern example is a direct fork of DoctorWkt/ULX3S-Blinky so is near-drop-in for ULX3S.

wuxx__icesugar

• Functions: board-hw, uart, soc-cpu, retro-computer, video-vga, audio-dac, oled-lcd, flash-spi, dsp-sdr, usb-device
• ULX3S build: src/basic/verilog// (per-example Makefile + shared src/common/io.pcf); src/advanced/{picorv32,icicle,up5k_6502,up5k-demos,iceZ0mb1e}/; prebuilt demo/*.bin bitstreams (LPF: iCESugar v1.5 (not ULX3S, iCE40 UP5K; schematic/iCESugar-v1.5.pdf))
• Reuse: src/basic/verilog/{uart_echo,ws2812,pll,bram,spram,dsp}/.v: small self-contained portable peripheral examples; src/advanced/picorv32/{picorv32.v,picosoc/picosoc.v}: portable RISC-V core/SoC (board .v wrappers use SB_ SPRAM, swap for ECP5)
• Tests: tools: verilator,iverilog
• Notes: 133 MB tree, many prebuilt demo/*.bin, no single top Makefile. Submodules fetched 2026-09-27: up5k_6502@28862a7, up5k-demos@93e942e, iceZ0mb1e@5a5d25e. litex-buildenv/VexRiscv/usb not fetched. icicle/picorv32 vendored directly. Uses SB_HFOSC/SB_PLL40/SB_SPRAM; clock 12 MHz vs ULX3S 25 MHz.

wuxx__icesugar-pro

• Functions: soc-cpu, video-dvi, uart, sdram, jtag, linux, constraints
• ULX3S build: src/blink/ (Makefile, blink.lpf); src/uart_tx/ (Makefile, top.lpf); src/hdmi_test_pattern/ (Makefile, ulx3s_v20_segpdi.lpf, reused verbatim from ULX3S-Blinky); src/litex_linux/ (build_top.sh, top_bg256.lpf) (LPF: iCESugar-pro (Muse Lab), DDR2-SODIMM form factor ECP5-25F board (not ULX3S))
• Reuse: src/hdmi_test_pattern/llhdmi.v + pattern.v (identical ECP5 DVI generator credited to DoctorWkt/ULX3S-Blinky, directly reusable on ULX3S); src/litex_linux/ build scripts (LiteX+VexRiscv Linux SoC flow, portable with a new LPF)
• Tests: tools: verilator
• Notes: Verified from source (Makefiles, README Copyright Statement). demo/ is mostly prebuilt .bit/.svf; README explicitly states the HDMI demo source is copied from a ULX3S project, so it is already ULX3S-compatible logic, just needs the ULX3S LPF (which the repo also happens to ship).

x653__xv6-riscv-fpga

• Functions: gateware, soc-cpu, uart, spi, sdcard, bootloader, linux, education
• ULX3S build: not ULX3S; fpga/top.v, fpga/ice40hx8k_evb.pcf, fpga/Makefile (also fpga/boot/ bootloader firmware in C) (LPF: Olimex iCE40HX8K-EVB + Olimexino 32u4 (programmer/UART bridge) + MOD-SDMMC (not ULX3S))
• Reuse: fpga/{clint.v,plic.v,uart.v,spi.v,sram.v,vma.v,rv32.v}: from-scratch RV32IA_Zicsr core + peripherals, portable RTL (no SB_* seen in these files); fpga/pll.v likely uses SB_PLL40 for the 32 MHz system clock (needs check before ECP5 port)
• Tests: 1 tb/test files;tools: iverilog
• Notes: Last commit 2023-03-05 (git log). CPU runs at 32MHz per README boot banner (“Processor: rv32ia @32MHz”). No overlap with catalogued lawrie__* repos (different author/board). LICENSE text is MIT despite hx-boards-survey.md listing license as “NOASSERTION” (no SPDX id string in file, but license body is verbatim MIT).

xtrinch__fpga-bitcoin-miner

• Functions: board-hw, uart, jtag, NEW:sha256
• ULX3S build: Makefile, src/top.v, src/ecp5evn.lpf (LPF: Lattice ECP5-EVN evaluation board (LFE5UM5G-85F-8BG381) (not ULX3S))
• Reuse: src/sha256_transform.v + sha256_functions.v (pipelined double-SHA256 unrolled hasher, pure portable Verilog); src/uart_comm.v + uart.v + crc32.v (UART command/packet protocol w/ CRC32 framing, portable); src/ecp5pll.py (yosys connect_rpc ECP5 EHXPLLL PLL generator, ECP5-specific)
• Tests: dirs: ./testbenches;1 tb/test files;tools: iverilog
• Notes: Verified from source (Makefile, testbenches/, LICENSE). Last commit 2022-04-01. Board CLK pin A10 (ecp5evn.lpf), PLL to 50MHz (Makefile –freq 50). No submodules. test-uart/test-top self-check via PASS/FAIL $display+$finish; test-miner only prints found nonce (compare by hand to genesis_block.txt).

yope__cpuv2

• Functions: soc-cpu, video-dvi, uart, ethernet, dsp-sdr, board-hw
• ULX3S build: top.v + ulx3s_v20.lpf, Makefile target(s) via cpuv2.ys yosys script and nextpnr-ecp5 –85k (LPF: ulx3s_v20.lpf)
• Reuse: cpu.v, alu.v (simple no-MMU/no-pipeline 32-bit CPU core), hdmi/*.v (ecp5pll/tmds_encoder/vga2dvid HDMI stack, widely-reused ULX3S HDMI boilerplate pattern), enet/mac.v + enet/pls.v (experimental Ethernet MAC/PHY, TX-only)
• Tests: 1 tb/test files
• Notes: README frames it explicitly as ‘just a learning project’; Ethernet MAC is experimental/TX-only (‘only able to transmit a test frame right now’)

yosyshq__picorv32

• Functions: soc-cpu, uart, flash-spi, constraints, board-hw
• ULX3S build: picosoc/hx8kdemo.v, picosoc/hx8kdemo.pcf, picosoc/Makefile (also picosoc/icebreaker.v/.pcf); no ULX3S/ECP5 support found (LPF: iCE40-HX8K Breakout Board (picosoc/hx8kdemo, CT256, not ULX3S); iCEBreaker (picosoc/icebreaker, UP5K SG48, not ULX3S); Xilinx 7-series and Intel/Altera devices via scripts/vivado, scripts/quartus (generic, no board))
• Reuse: picorv32.v: the CPU core itself, portable synthesizable Verilog-2005, board-agnostic, no vendor primitives, directly reusable on ECP5; picosoc/picosoc.v + spimemio.v + simpleuart.v: portable SoC peripherals, picosoc/ice40up5k_spram.v (SB_SPRAM256KA) and the board tops picosoc/hx8kdemo.v, icebreaker.v (SB_IO tristate flash IO) are iCE40-specific: replace with DP16KD/BB on ECP5
• Tests: dirs: ./tests;6 tb/test files;tools: verilator,iverilog
• Notes: Well-known, widely-forked RISC-V core; “no longer under active development” per README banner; last commit 2026-09-07 (likely CI/doc touch, not feature work); clock: hx8kdemo runs at 12 MHz (icetime -c 12), icebreaker synth at freq 13; no submodules

yowasp__toolchain-demo

• Functions: board-hw, constraints, examples, toolchain, programmer-tool, bootloader
• ULX3S build: repo root: top.py, top.lpf (LPF: top.lpf)
• Reuse: top.py minimal Amaranth blinky pattern reusable as a YoWASP starting template
• Tests: none found
• Notes: Explicitly portable to iCE40/ECP5/MachXO2/MachXO3/Nexus - ULX3S is just the default target board, not ULX3S-specific

zeldin__icegdrom

• Functions: soc-cpu, ide, sdcard, audio-dac, retro-console, constraints, board-hw
• ULX3S build: fpga/source/top.v, fpga/source/top.pcf, fpga/GNUmakefile (DEVICE=–hx8k –package ct256); no ULX3S/ECP5 support (LPF: Lattice iCE40-HX8K Breakout Board + custom “riser board” to a Sega Dreamcast motherboard (pcb/riser), not ULX3S)
• Reuse: fpga/source/vexriscv/core/VexRiscv.v: vendored full VexRiscv RV32 core (SpinalHDL-generated, portable Verilog); fpga/source/ide/ide_interface.v + ide_reset_generator.v: standalone parallel-ATA/IDE target interface, portable but ide_reset_generator.v depends on fpga/source/ide/tech (iCE40-specific, needs check before ECP5 reuse); fpga/source/tech/ice40/clkgen.v, tri_buf.v: thin iCE40 primitive wrappers (SB_* likely), must be re-targeted for ECP5
• Tests: dirs: ./test
• Notes: Last commit 2023-02-18; project targets real Sega Dreamcast hardware, not a generic dev board; clock/PLL config not checked beyond tech/ice40/clkgen.v; no gateware submodules (only avr/cdda/ide/sdcard/tech/vexriscv source dirs, all vendored in-tree)

zipcpu__dblclockfft

• Functions: toolchain, dsp, NEW:fft
• ULX3S build: Makefile (sw/+bench only, no FPGA build in this repo); sw/fftgen.cpp generator; rtl/fftmain.v demo top (LPF: none (vendor-neutral core generator; no board in this repo); not ULX3S)
• Reuse: sw/fftgen.cpp (+fftlib/bldstage/butterfly/bitreverse/rounding/softmpy .cpp/.h): portable C++ generator emitting a customizable pipelined radix-2 FFT/IFFT core (rtl/fftmain.v demo: 512-pt fixed 16-bit forward FFT built from fftstage/hwbfly/butterfly/bitreverse/laststage.v); no vendor primitives; used (regenerated/instantiated) unmodified by mb-sat__ulx3s-longwave-sdr (ECP5 85F, 512-pt) and C-Elegans__single_sdr (ECP5 45F, 256-pt)
• Tests: 1 tb/test files;tools: verilator
• Notes: Last commit 2024-04-18 (267 stars, the most-reused FFT core in this survey). No repo LICENSE file; GPL-3.0 headers on the sw/ generator and Makefiles, LGPL-3.0 headers on the rtl/ demo Verilog. rtl/ is an example generator OUTPUT per rtl/README.md, not hand-written IP - regenerate with sw/fftgen for other sizes/widths. Formal (SymbiYosys) and C++ (vs. Octave-generated golden vectors) test suites both present.

zipcpu__icozip

• Functions: soc-cpu, uart, flash-spi, sram, gpio, bus-fabric, wishbone-bus, debug-bridge
• ULX3S build: rtl/icozip/{toplevel.v,main.v,icozip.pcf,Makefile}; no ULX3S/ECP5 support (LPF: ICO board (iCE40 HX8K CT256 + Raspberry Pi, not ULX3S))
• Reuse: rtl/icozip/cpu/ vendored ZipCPU RISC core (portable Wishbone CPU, no iCE40 primitives seen); rtl/basic/, rtl/debouncer/ (incl. wbscope Wishbone logic analyzer) are small self-contained Wishbone peripherals reusable on any board with a new PCF; bench/formal/*.sby SymbiYosys formal specs (fwb_master/slave.v Wishbone formal properties) for several peripherals
• Tests: dirs: ./sim;tools: verilator
• Notes: Last commit 2021-05-05; part of ZipCPU/Gisselquist demo-board series (also NexysDemo, S6SoC etc.); no submodules

zipcpu__sdr

• Functions: dsp-sdr, radio-rx, radio-tx, dsp, audio-dac
• ULX3S build: rtl/toplevel.v, rtl/sdr.pcf, Makefile (AutoFPGA-generated top; make rtl builds it) (LPF: iCEBreaker + SX1257 Radio PMod + Digilent MIC3 (mic) / AMP2 (amp) PMods (rtl/sdr.pcf); not ULX3S)
• Reuse: rtl/cicfil.v: CIC integrate-and-dump decimator with programmable stage/downsample shift-gain compensation, portable Verilog, no vendor primitives; rtl/subfildown.v: generic FIR-filter-then-1/M-downsampler; rtl/seqcordic.v: sequential (1 value/cycle) CORDIC vector rotator; rtl/{amdemod.v,fmdemod.v,amxmit.v,fmxmit.v,qpskrcvr.v,qpskxmit.v}: AM/FM/QPSK demod and modulator tops built on the above
• Tests: dirs: ./sim;tools: verilator
• Notes: Last commit 2024-01-18 (git log -1). iCEBreaker 12MHz onboard oscillator (rtl/sdr.pcf: i_clk_12mhz). rtl/toplevel.v, rtl/sdr.pcf and sim/main_tb.cpp are AutoFPGA-generated build products (make autodata), not hand-written. Simulation has no RF channel model (README): outputs are simply fed back into the sim receiver. No submodules.

zipcpu__sdspi

• Functions: sdcard, spi, wishbone-bus, dma
• ULX3S build: vendor-neutral core, no board top/constraints shipped; rtl/spi/{llsdspi.v,sdspi.v}, rtl/sdio/{sdio.v,sdio_top.v,…}, rtl/sdslave/*; autodata/{sdio,sdspi}.txt (autofpga Wishbone glue); sdspi.core (FuseSoC); bench/formal, bench/cpp (verilator) (LPF: none (core only, no reference board); README cites XuLA2-LX25 (Xilinx Spartan-6, not ULX3S) as the original integration target)
• Reuse: rtl/spi/{llsdspi.v,sdspi.v}: portable low-level SPI-mode SD controller, pure Verilog, no vendor primitives - drop-in for ECP5; rtl/sdio/{sdio.v,sdio_top.v,sdfrontend.v}: full SDIO/eMMC controller, portable in default SDR mode; OPT_DDR/OPT_SERDES pull in rtl/xsdddr.v / xsdserdes8x.v which hard-code Xilinx ODDR/IDDR (rewrite with ECP5 ODDRX1F/IDDRX1F); bench/formal/*.sby formal proofs cover nearly every submodule (SymbiYosys)
• Tests: 5 tb/test files;tools: verilator,iverilog
• Notes: Last commit 2026-08-01 (git log -1). Part of ZipCPU/Gisselquist Technology’s Wishbone SoC ecosystem (autofpga/FuseSoC integration files included). Heavily formally verified: ~60 SymbiYosys proof/cover targets in bench/formal/Makefile. No submodules.

zipotron__neorv32-complex-setups

• Functions: soc-cpu, sdram, board-hw
• ULX3S build: hardware_dependent/ulx3s/ (ulx3s_sdram.vhd) + top/neorv32_ULX3S_BoardTop_MinimalBoot.vhd, built via neorv32’s own osflow (no local .lpf/.mk found) (LPF: NO ULX3S .lpf file present in this clone (constraints live in the unfetched neorv32 submodule’s osflow dir))
• Reuse: hardware_dependent/ulx3s/ulx3s_sdram.vhd, wb_sdram.vhd, wb_intercon.vhd – reusable Wishbone SDRAM controller
• Tests: none found
• Notes: neorv32/ submodule is empty in this shallow clone (git submodule not initialized), so FPGA size, LPF, and toolchain details are only inferable, not directly observed

zipotron__ulx3s_sdram8

• Functions: sdram, board-hw, examples
• ULX3S build: testram.v (top) + sdram.vhd + ulx3s_v20.lpf, via Makefile/ulx3s.mk (LPF: ulx3s_v20.lpf)
• Reuse: sdram.vhd (VHDL SDRAM controller, translated from a known-good Verilog original — useful as a VHDL-flow reference)
• Tests: tools: iverilog
• Notes: README is a single line crediting the Verilog source; minimal test/experiment repo, not a full application

zipotron__ziposoc

• Functions: soc-cpu, uart
• ULX3S build: root (Makefile, ulx3s_v20.lpf) (LPF: ulx3s_v20.lpf)
• Reuse: zipocpu.v/alu.v/comparator.v/expander.v (small CPU core), memory_map.v
• Tests: 4 tb/test files;tools: iverilog
• Notes: Minimal SoC with several testbenches (*_tb.v) but only a 1-line README; no license header found.

zyedidia__riscinator

• Functions: soc-cpu, uart, gpio, timer, sram
• ULX3S build: tech/ulx3s/{top.v,ulx3s_v20.lpf}, Knitfile (knit synth tech=ulx3s) (LPF: tech/ulx3s/ulx3s_v20.lpf)
• Reuse: src/ - 3-stage RV32I Chisel core (<1000 lines), shared bus+arbiter; portable HDL (Chisel-generated Verilog, no vendor primitives seen in tech/ulx3s/top.v); CoreMark 1.00CM/MHz reported (README)
• Tests: dirs: ./tests ./src/test
• Notes: Last commit 2023-04-13. No submodules.

zyp__katsuo-pcie

• Functions: serdes-pcie-sata, NEW:pcie
• ULX3S build: katsuo/pcie/phy/ecp5_serdes.py (PHY), katsuo/pcie/mac/ltssm.py (LTSSM), katsuo/pcie/dll/.py, katsuo/pcie/tl/.py (DLL/TL). No top-level build script or board/platform file in this repo; tests/*.py are Amaranth-sim unit tests. (LPF: none in this repo (board-agnostic PHY/stack; tested via litepcie-katsuo-poc on Lattice Versa ECP5))
• Reuse: katsuo/pcie/phy/ecp5_serdes.py: ECP5SerDes (DCUA+EXTREFB, Amaranth wiring.Component), reuses code from Yumewatari (0BSD, credited in-file). katsuo/pcie/mac/ltssm.py, dll/.py, tl/.py: board-agnostic PCIe MAC/DLL/TL layers, reusable on any board once wired to an ECP5 PIPE-like PHY.
• Tests: dirs: ./tests;4 tb/test files
• Notes: Last commit 2026-04-28 (git log; survey’s last-push date is 2026-04-27). Author calls it a ‘working proof of concept’: Gen1 x1, no retransmit, no flow control, SERDES sometimes fails to lock (README). No submodules; depends on external ‘katsuo-stream’ package (not vendored, not present in original_sources).

zyp__litepcie-katsuo-poc

• Functions: serdes-pcie-sata, NEW:pcie
• ULX3S build: lattice_versa_ecp5.py (top, LiteX Builder), ecp5_pcie.py (LitePCIe ECP5PCIePHY wrapper), ecp5_pcie.v (pregenerated Verilog snapshot of katsuo.pcie). No .lpf in this repo; uses litex-boards’ lattice_versa_ecp5 platform (external). (LPF: Lattice Versa ECP5-5G (via litex_boards lattice_versa_ecp5 platform, no local .lpf))
• Reuse: ecp5_pcie.py: ECP5PCIePHY LiteXModule adapting katsuo.pcie’s PIPE datapath to LitePCIe’s PHYTXDatapath/PHYRXDatapath. ecp5_pcie.v is a pregenerated Verilog snapshot of katsuo.pcie (not built from source here). lattice_versa_ecp5.py: LiteX SoC integration example (DDR3, RGMII Ethernet, LiteScope) usable as a template for other ECP5-5G LitePCIe targets.
• Tests: none found
• Notes: Last commit 2026-04-28. README shows lspci enumerating the device at 2.5 GT/s x1 on real Versa ECP5 hardware; says to reload the FPGA a couple of times if the link LED doesn’t come on (SERDES lock flakiness inherited from katsuo.pcie). No submodules; heavy external deps (litex, litedram, liteeth, litescope, litepcie pinned to a commit).

Index by function

• adapter-board: gojimmypi__ulx3s-adda, ulx3s__ulx3s-adda
• adc: amin005__skywave_sdr, bonfireprocessor__bonfire-basic-soc, dangerousprototypes__buspirateultrahdl, emard__flearadio, emard__ulx3s-bin, emard__ulx3s-emi, emard__ulx3s-misc, emeb__iceradio, emeb__orangecrab-litex-adc, emeb__orangecrab_adc, emeb__rpi_rxadc, emeb__up5k_osc, f32c__f32c, fulig__tinyfpga_fft, glasgowembedded__glasgow, gojimmypi__ulx3s-adda, greatscottgadgets__hackrf, hdl4fpga__hdl4fpga, hoglet67__ice40beeb, hsa-ees__piconut, kelu124__lit3rick, kelu124__un0rick, lawrie__blackicemxbook, lcausevic__ulx3s_fpga_logic_structures, makisness__inductiq, mattvenn__fpga-sdft, mb-sat__ulx3s-longwave-sdr, mysteriouswolf__vna_fpga_dsp, nkrackow__singularitysurfer-fpga-lock-in-amplifier, pablogs9__rocketfpga, pietptr__ulx3s-dsp, romavis__lwdo-sdr-fw, secworks__cryptkey, tadeoroboticsgroup__axiomacore-328, tarik-hamedovic__sdr-hls, tvelliott__dsp_ice, ulx3s__ulx3s-adda
• advent-of-code: cgarryza__advent-of-camel-2025, gergoerdi__advent-of-clash-2025
• agc-cpu: mikeakohn__apollo11_fpga
• asic-prototyping: gojimmypi__ttgf-uart-fsm-trng-lab, gojimmypi__ttgf0p3-uart-fsm-trng-lab, gojimmypi__ttsky-uart-fsm-trng-lab
• async-fifo: dicethrow__amaram
• audio-dac: bit-hack__icesid, cheyao__nes_ecp5, cheyao__sega-sms, daglem__redip-sid, dan-rodrigues__ics-adpcm, danodus__ulx3s_68k, danodus__ulx3s_sms, daveshah1__up5k-demos, emard__apple2fpga, emard__flearadio, emard__galaksija, emard__jupiter_ace, emard__minimig_ecs, emard__nes_ecp5, emard__next186, emard__papilio-arcade, emard__synthowheel, emard__ulx3s-misc, emard__vhdl_c64_c1541_sd, emard__vhdl_phoenix, emeb__orangecrab-litex-adc, emeb__orangecrab_adc, emeb__up5k_osc, emeb__up5k_vga, f32c__f32c, fusetim__rusty-soc, gojimmypi__ulx3s-adda, hexagon5un__hackaday_supercon_2019_logic_noise_fpga_workshop, kbeckmann__tt08-flame, kost__ulx3s-ghdl-examples, lawrie__blackicemxbook, lawrie__ulx3s_acorn_atom, lawrie__ulx3s_examples, lawrie__ulx3s_gamegear, lawrie__ulx3s_sms, lawrie__ulx3s_vhdl_examples, lawrie__ulx3s_zx81, lawrie__verilog_examples, logoposeidon__ulx3sjukebox, lucasebskora__wav-player, machdyne__fpga-dac, machdyne__nes_ecp5, machdyne__zeitlos, markus-zzz__max9850-test, mmicko__fpga101-workshop, osresearch__up5k, pablogs9__rocketfpga, pietptr__ulx3s-dsp, rxrbln__picorv32, speccery__icy99, splinedrive__kianriscv, spritetm__hadbadge2019_fpgasoc, sylefeb__silice, thorkn__spinalsynth_ulx3s, tristanitschner__ulx3s-examples, tvelliott__dsp_ice, ulx3s__fpga-odysseus, ulx3s__ulx3s-adda, wifiboy__ok-ice40pro, wren6991__riscboy, wuxx__icesugar, zeldin__icegdrom, zipcpu__sdr
• audio-i2s: antoinevg__cynthion-tutorials, apfaudio__eurorack-pmod, bjonnh__ulx3s-synth, daglem__redip-sid, danodus__ecp5_hdmi_audio_video, datanoisetv__colorlight-i9-aes67, dylansebastianheredia__e155_tuner_project, emard__ulx3s-misc, emeb__rpi_rxadc, f32c__f32c, gage1999__fpga-sdr-receiver, kelu124__lit3rick, mangelajo__orangecrab-usb, mebner86__icesugar-pro_sound2fft, pablogs9__rocketfpga, sylefeb__silice, tallenintegsys__hdmi-orangecrab, td0034__fpga, tvelliott__dsp_ice
• audio-spdif: emard__minimig_ecs, emard__papilio-arcade, emard__synthowheel, emard__uk101onfpga, emard__ulx3s_c64, emard__vhdl_phoenix, f32c__f32c, linuxjedi__minimig_ecs
• avr-core: tadeoroboticsgroup__axiomacore-328
• benchmark: pepijndevos__litedhrystone
• bit-serial-cpu: michaelbell__nanov
• bitslice-cpu: msiddalingaiah__centurion
• board-hw: acairncross__clash-ulx3s-examples, ahamidi87__simpleblinky, alangarf__apple-one, angelojacobo__ulx3s_fpga_camera_streaming, angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670, antonblanchard__chiselwatt, asinghani__advent-of-hardcaml-2024, asinghani__advent-of-hardcaml-2025, badgeteam__mch2022-firmware-ice40, bjonnh__ulx3s-synth, bonfireprocessor__bonfire-ecp5-jtagg-led-demo, bornabiro__fpga_epaper, bqqbarbhg__blipv1, brunolevy__tordboyau, carlosedp__chisel-fpga-pinfinder, carlosedp__chiselv, carlraymond__ulx3s-container, cbalint13__e-verest, cheyao__icepi-zero, chipflow__example-socs, chiplet__acorechip-ulx3s, chiplet__ulx3s-blinky, circuit-killer__fpga-usbhid-host, damdoy__ice40_ultraplus_examples, dan-rodrigues__ics-adpcm, dan-rodrigues__mobile-fpga-bluetooth-demo, dan-rodrigues__ulx3s-bluetooth-gamepad, danodus__ecp5_hdmi_audio_video, darklife__darkriscv, daveshah1__prjtrellis-dvi, detegr__ulx3s-projects, diegob94__ulx3s_blink, dman2021__blink, dman2021__fpga_count, dpks2003__my_ulx3s_repo, dschaefer__fpga-template, dschaefer__ulx3s-ghdl-adder, dstrbad__janestreet-advent-fpga, dulatello08__ulx3s-tests, egorxe__openglory, emard__cortex, emard__had2019-playground, emard__snes_mister_ulx3s, emard__tinyfpga-bootloader-ulx3s, emard__ulx2s, emard__ulx3s, emard__ulx3s-emi, emard__ulx3s-jtagthru, emard__ulx3s_c64, emard__ulx3s_galaksija, emard__usb_host, emard__vhdl_c64_c1541_sd, embeddeddojo__ulx3s_examples, emeb__orangecrab_adc, emeb__up5k_osc, evansm7__arcdvi, fdarling__orangecrab-usb-cdc-demo, fedy0__neo, fedy0__zta, flyingoverclouds__flocs-ulx3s-samples, fpgawars__flix-v, fusesoc__blinky, fywc__ulx3s_rv32i_processor, gatecat__snes_mister_ulx3s, gatecat__trellisboard, ghaworth__ulx3s-bldc-foc, gmejiamtz__ulx3s-components, gojimmypi__nextpnr-issue235, gojimmypi__ttgf-uart-fsm-trng-lab, gojimmypi__ttgf0p3-uart-fsm-trng-lab, gojimmypi__ttsky-uart-fsm-trng-lab, gojimmypi__ulx3s-examples, gojimmypi__z80386-ulx3s-doom, goran-mahovlic__odysseus_sprites, goran-mahovlic__ulx3s-pmod, gtjennings1__hyperbus, heichips__heichips25-template, icebreaker-fpga__icebreaker-verilog-examples, icebreaker-fpga__icebreaker-workshop, icebreaker-fpga__icetwang, im-tomu__fomu-workshop, intergalaktik__ulx4m-ls, jadephilipoom__ulx3s-experiments, jamesrosssharp__1_bit_am, jamesrosssharp__ulx3s_mixer_pcb, jamon__jspcpu, jderobot__fpga-robotics, johnazoidberg__ulx3s-espi-analyzer, kholia__colorlight-5a-75b, krishkc5__trng-ring-oscillator, kulp__tenyr, l0r3m1psum__videogame_verilog, lawrie__fpga_pio, lawrie__jupiter_ace, lawrie__ulx3s_altair_8800, lawrie__ulx3s_atari_2600, lawrie__ulx3s_ay_3_8500, lawrie__ulx3s_bbc_micro, lawrie__ulx3s_cpm_z80, lawrie__ulx3s_ql, lawrie__ulx3s_vhdl_examples, lawrie__ulx3s_vic_20, lawrie__ulx3s_z80_template, lawrie__ulx3s_z80_trs80, lawrie__ulx4m_amaranth_examples, lawrie__ulx4m_examples, lcausevic__ulx3s_fpga_logic_structures, lfglabs-dev__lean-silicon, linuxjedi__minimig_ecs, litex-hub__litex-boards, machdyne__fpga-dac, machdyne__zeitlos, mangelajo__orangecrab-usb, marinsiric__ulx3s, markus-zzz__myc64, maxhpc__ecpix-5, mb-sat__ulx3s-longwave-sdr, mcejp__poly94, mithro__asus-d16-ulx3s-interface, mmicko__ulx3s-examples, mpardalos__clash-blinky, msinger__iceboy, msrraju07__iop, mystorm-org__blackice-ii, nh428__ulx3s-tft-display-sobel-object-detection, nullobject__counter-ulx3s, nullobject__m68k-ulx3s, nullobject__riscv-ulx3s, nusgreyhats__greybadge25, orangecrab-fpga__orangecrab-examples, osmocom__osmo-e1-hardware, osresearch__up5k, p-kraszewski__cs-ulx3s-03, pablogs9__rocketfpga, pcotret__ulx3s-examples, pietptr__ulx3s-dsp, pmezydlo__beaglewire, punchthatface__tinydma, q3k__ulx3s-foss-blinky, racerxdl__colorlight-picorv32, ranzbak__fpga-workshop, richardegeorge__ulx3s-chase, richardegeorge__ulx3s-flipflop, richardegeorge__ulx3s-passthru, riltonf__thermal_camera_ulx3s, rj45__vdp, robinsonb5__eightthirtytwodemos, ruebenschus__atari-fpcartridge, rxrbln__picorv32, saul-rodriguez__ulx3s, schlae__graphics-gremlin, sefbkn__versa-ecp5-demo, smunaut__mch2022-ice40, speccery__icy99, spinalhdl__saxonsoc, srjilarious__fpga_start, stefanhaslhofer__hardwaredesign, stereoninja__stereoninjafpga, stnolting__neorv32-setups, stuij__odyssey, sylefeb__tinygpus, tallenintegsys__hdmi-orangecrab, td0034__fpga, techprototyper__trs80-rev-z, thata__ulx3s-playground, thata__ulx3s-uart-loopback, thewbi__ulx3s, thorkn__spinalsynth_ulx3s, thorkn__vexriscv-ulx3s-simple-plugin, thorkn__vga_clock_1, thorkn__vga_pong, tinyvision-ai-inc__pico-ice-sdk, titouanc__fpga-scratchpad, toasterllc__mdccode, tommythorn__bluespec_blink, tomverbeure__ecp5_jtag, tucanae47__ulx3s-experiments, tvelliott__dsp_ice, ultraembedded__ecpix-5, ultraembedded__orangecrab, ulx3s__blink, ulx3s__hazard3, vladov3000__ulx3s, vmware-archive__cascade, w531t4__fpga_led_display, wren6991__hazard3, wren6991__riscboy, wuxx__icesugar, xtrinch__fpga-bitcoin-miner, yope__cpuv2, yosyshq__picorv32, yowasp__toolchain-demo, zeldin__icegdrom, zipotron__neorv32-complex-setups, zipotron__ulx3s_sdram8
• bootloader: businessmanraduc__doggo-v6, chipdesign-bv__cdriscv-32s-20, chriscamacho__yazsof, daveshah1__ulx3s, dok3r__ulx3s-saxonsoc, dulatello08__neocore-fx, emard__esp32ecp5, emard__had2019-playground, emard__prjtrellis-picorv32, emard__tinyfpga-bootloader-ulx3s, emard__ulx3s-bin, emard__ulx3s-misc, emard__ulx3s-passthru, emeb__up5k_osc, f32c__f32c, f32c__fpgarduino, im-tomu__foboot, intergalaktik__ulx4m-ls, john-k__spinose, lfglabs-dev__lean-silicon, litex-hub__linux-on-litex-vexriscv, machdyne__tinydfu-bootloader, machdyne__zeitlos, mystorm-org__blackice-ii, nklabs__libnklabs-ulx3s, no2fpga__no2bootloader, pablogs9__rocketfpga, punchthatface__tinydma, smunaut__had2019-playground, splinedrive__kianriscv, stnolting__neorv32, tinyfpga__tinyfpga-bootloader, tinyvision-ai-inc__pico-ice-sdk, trabucayre__openfpgaloader, ulx3s__hazard3-doom, ulx3s__ulx3s-saxonsoc, wren6991__riscboy, x653__xv6-riscv-fpga, yowasp__toolchain-demo
• bus-fabric: antoinevg__cynthion-tutorials, assured__ct-key, bhouvana__aegis-x86-processor, bonfireprocessor__bonfire-core, chiplet__acorechip-ulx3s, greatscottgadgets__luna-soc, pmezydlo__beaglewire, tucanae47__litex_etpu, ulx3s__hazard3, vyges__fast-fourier-transform-ip, wren6991__hazard3-swd-soc, wren6991__riscboy, zipcpu__icozip
• camera: advikbahadur__ulx3s-superresolution-cnn, angelojacobo__ulx3s_fpga_camera_streaming, angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670, emard__ulx3s-misc, intergalaktik__ulx4m-ls, jderobot__fpga-robotics, lawrie__blackicemxbook, lawrie__ulx3s-nmigen-examples, mangelajo__orangecrab-usb, msrraju07__iop, nh428__ulx3s-tft-display-sobel-object-detection, riltonf__thermal_camera_ulx3s, stereoninja__stereoninjafpga, toasterllc__mdccode, tucanae47__ulx3s-experiments
• compression: seminlim__zfpe
• constraints: acairncross__clash-ulx3s-examples, angelojacobo__ulx3s_fpga_camera_streaming, angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670, antonblanchard__chiselwatt, apfaudio__eurorack-pmod, bjonnh__ulx3s-synth, bnossum__midgetv, bornabiro__fpga_epaper, brunolevy__tordboyau, carlosedp__chiselv, carlraymond__ulx3s-container, chiplet__acorechip-ulx3s, chiplet__ulx3s-blinky, circuit-killer__fpga-usbhid-host, dan-rodrigues__ics-adpcm, dan-rodrigues__mobile-fpga-bluetooth-demo, darklife__darkriscv, datanoisetv__colorlight-i9-aes67, daveshah1__prjtrellis-dvi, detegr__ulx3s-projects, dstrbad__janestreet-advent-fpga, emard__cortex, emard__had2019-playground, emard__tinyfpga-bootloader-ulx3s, emard__ulx3s, emard__ulx3s-emi, emard__ulx3s-jtagthru, emard__ulx3s_c64, emard__ulx3s_galaksija, emard__usb_host, emard__vhdl_c64_c1541_sd, embeddeddojo__ulx3s_examples, fdarling__orangecrab-usb-cdc-demo, fedy0__neo, fedy0__zta, flyingoverclouds__flocs-ulx3s-samples, fpgawars__flix-v, fusesoc__blinky, gatecat__trellisboard, ghaworth__ulx3s-bldc-foc, gmejiamtz__ulx3s-components, gojimmypi__ulx3s-examples, gojimmypi__z80386-ulx3s-doom, gornjas__dvi_test, hexagon5un__hackaday_supercon_2019_logic_noise_fpga_workshop, hoglet67__ice40atom, hoglet67__ice40beeb, ibm2030__ibm2030, intergalaktik__ulx4m-ls, jamesbowman__swapforth, jamesrosssharp__1_bit_am, jamon__jspcpu, jderobot__fpga-robotics, johnazoidberg__ulx3s-espi-analyzer, kbeckmann__tt08-flame, kulp__tenyr, lawrie__fpga_pio, lawrie__jupiter_ace, lawrie__ulx3s_atari_2600, lawrie__ulx3s_ay_3_8500, lawrie__ulx3s_bbc_micro, lawrie__ulx3s_cpm_z80, lawrie__ulx3s_ql, lawrie__ulx3s_vhdl_examples, lawrie__ulx3s_vic_20, lawrie__ulx3s_z80_template, lawrie__ulx3s_z80_trs80, lfglabs-dev__lean-silicon, lucysrausch__colorlight-led-cube, machdyne__zeitlos, maxhpc__ecpix-5, mb-sat__ulx3s-longwave-sdr, mcejp__poly94, mebner86__icesugar-pro_sound2fft, msinger__iceboy, mystorm-org__blackice-ii, nh428__ulx3s-tft-display-sobel-object-detection, orangecrab-fpga__orangecrab-examples, p-kraszewski__cs-ulx3s-03, pcotret__ulx3s-examples, pietptr__ulx3s-dsp, q3k__ulx3s-foss-blinky, ranzbak__fpga-workshop, riltonf__thermal_camera_ulx3s, rj45__vdp, robinsonb5__eightthirtytwodemos, rxrbln__picorv32, schlae__graphics-gremlin, sefbkn__versa-ecp5-demo, smunaut__had2019-playground, smunaut__ice40-playground, speccery__icy99, spinalhdl__saxonsoc, stereoninja__stereoninjafpga, stnolting__neorv32-setups, thorkn__spinalsynth_ulx3s, thorkn__vexriscv-ulx3s-simple-plugin, tucanae47__ulx3s-experiments, ultraembedded__core_ddr3_controller, ultraembedded__ecpix-5, ultraembedded__orangecrab, ulx3s__blink, ulx3s__tt-support-tools, ulx3s__ulx3s-examples, w531t4__fpga_led_display, wren6991__hazard3, wren6991__riscboy, wuxx__colorlight-fpga-projects, wuxx__icesugar-pro, yosyshq__picorv32, yowasp__toolchain-demo, zeldin__icegdrom
• cordic-note-detector: pat-pgt__multifrequenciesdetector
• cpu-retro: danielh186__6502-tapeout, harrowm__mackerel_030f, rhobbie__library704
• crypto: assured__ct-key, chipdesign-bv__cdriscv-32s-20, gojimmypi__ttgf0p3-analog-uart-fsm-trng-lab, kbeckmann__pergola_projects, krishkc5__trng-ring-oscillator, lfglabs-dev__lean-silicon, marph91__yaaes, nusgreyhats__greybadge25, rainbow1128__vhdl-aes-master, williamsharkey__pruned-sha256-miner
• crypto-hsm: secworks__cryptkey
• dac: blazra__tdr
• ddr3: maxhpc__ecpix-5, openconcepts-ar__accel2d, remyciterin__3driscv, ultraembedded__core_ddr3_controller, ultraembedded__orangecrab
• debug-bridge: bonfireprocessor__bonfire-core, carlosedp__chisel-fpga-pinfinder, dangerousprototypes__buspirateultrahdl, ecp5-pcie__ecp5-pcie, glasgowembedded__glasgow, orbcode__orbtrace, ultraembedded__ecpix-5, voltcyclone__hurricanefpga, zipcpu__icozip
• debug-instrument: hdl4fpga__hdl4fpga, orbcode__orbtrace
• dma: apfaudio__guh, gojimmypi__z80386-ulx3s-doom, zipcpu__sdspi
• dsp: agamez__whisperice, alberto-grl__1bitsdr, alhusseingamal__r2sdf-fft, apfaudio__eurorack-pmod, damdoy__ice40_ultraplus_examples, dylansebastianheredia__e155_tuner_project, emeb__rpi_rxadc, enjoy-digital__litedsp, fulig__tinyfpga_fft, greatscottgadgets__amalthea, greatscottgadgets__cynthion-uac, greatscottgadgets__hackrf, hariharan6307-coder__verilog-goertzel-audio-visualizer, ipmgroup__fftd, joaln27__cordic, makisness__inductiq, mattvenn__fpga-sdft, maxzischka1__fastfouriertransformproject, meharbaan2__systemverilog-ofdm-phy-core, mehrdadh__lora-modulator, mysteriouswolf__vna_fpga_dsp, nicocavallu__rf-fft-engine, nkrackow__singularitysurfer-fpga-lock-in-amplifier, ox-computing__real-time-analytics-fpga, pat-pgt__multifrequenciesdetector, seminlim__sway, seminlim__zfpe, seth16225__riscv-core-portfolio, vyges__fast-fourier-transform-ip, zipcpu__dblclockfft, zipcpu__sdr
• dsp-sdr: agamez__whisperice, alberto-grl__1bitsdr, amin005__skywave_sdr, c-elegans__single_sdr, cariboulabs__cariboulite, dibyx__flux, dstrbad__janestreet-advent-fpga, emard__flearadio, emard__rdsfpga, emard__ulx3s-misc, emeb__iceradio, emeb__orangecrab-litex-adc, emeb__orangecrab_adc, emeb__rpi_rxadc, gage1999__fpga-sdr-receiver, gojimmypi__ulx3s-adda, greatscottgadgets__amalthea, greatscottgadgets__hackrf, hdl4fpga__hdl4fpga, jamesrosssharp__1_bit_am, jamesrosssharp__ulx3s_mixer_pcb, kelu124__lit3rick, kholia__colorlight-5a-75b, mb-sat__ulx3s-longwave-sdr, mebner86__icesugar-pro_sound2fft, mehrdadh__lora-modulator, mysteriouswolf__vna_fpga_dsp, nicocavallu__rf-dds-lo, nicocavallu__rf-sdr-frontend, nkrackow__singularitysurfer-fpga-lock-in-amplifier, osresearch__up5k, pietptr__ulx3s-dsp, romavis__lwdo-sdr-fw, semify-eda__waveform-generator, tarik-hamedovic__sdr-hls, thorkn__spinalsynth_ulx3s, tvelliott__dsp_ice, uttamcoomar__mac-units-for-various-number-formats, wuxx__icesugar, yope__cpuv2, zipcpu__sdr
• e1-telecom: osmocom__osmo-e1-hardware
• education: acairncross__clash-ulx3s-examples, andreaspirklbauer__oberon-extended, angelojacobo__ulx3s_fpga_camera_streaming, angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670, asinghani__advent-of-hardcaml-2024, asinghani__advent-of-hardcaml-2025, asinghani__ulx3s-vga-example, badgeteam__mch2022-firmware-ice40, bnossum__midgetv, brunolevy__learn-fpga, callummcduff-droid__cpu, cgarryza__advent-of-camel-2025, chrislikescisco__nes-fpga, dicethrow__amtest, doctorwkt__ulx3s-blinky, doctorwkt__verilog_tic-tac-toe, emard__verilog_tic-tac-toe, emeb__ulx3s_6502, eringr__nmigen_fibonacci, gergoerdi__advent-of-clash-2025, gojimmypi__ulx3s-examples, hassan2203__system-on-chip-soc-design-and-verification, heichips__heichips25-template, hexagon5un__hackaday_supercon_2019_logic_noise_fpga_workshop, hsa-ees__piconut, icebreaker-fpga__icebreaker-workshop, im-tomu__fomu-workshop, jamon__jspcpu, jderobot__fpga-robotics, jlopezr__mini-gpu, johngannon4__riscv-cpu-portfolio, kbeckmann__tt08-flame, kost__ulx3s-ghdl-examples, lawrie__blackicemxbook, lawrie__fpgacosmacelf, lawrie__ulx3s_examples, lawrie__ulx3s_vhdl_examples, lazardjurovic__edulent_rtl, lcausevic__ulx3s_fpga_logic_structures, marinsiric__ulx3s, mebner86__icesugar-pro_sound2fft, mkvenkit__learn_fpga, mmicko__fpga101-workshop, nesl__ice40_examples, obijuan__open-fpga-verilog-tutorial, orangecrab-fpga__orangecrab-examples, p-kraszewski__cs-ulx3s-03, ranzbak__fpga-workshop, reddocmd__klaus, remyciterin__adventoffpga, splinedrive__kianriscv, srjilarious__fpga_start, stefanhaslhofer__hardwaredesign, stnolting__neorv32, sylefeb__silice, thata__td4-ulx3s, theperfectcomputer__learn-clash, thewbi__ulx3s, thezoq2__tinytapeout02, thorkn__vexriscv-ulx3s-simple-plugin, ulx3s__fpga-odysseus, ulx3s__tt-support-tools, ulx3s__ulx3s-examples, wifiboy__ok-ice40pro, x653__xv6-riscv-fpga
• eink: bornabiro__fpga_epaper, emard__ulx3s-misc
• esp32: bonfireprocessor__bonfire-basic-soc, carlraymond__ulx3s-container, cheyao__nes_ecp5, cheyao__sega-sms, dan-rodrigues__mobile-fpga-bluetooth-demo, dan-rodrigues__ulx3s-bluetooth-gamepad, danodus__ulx3s_68k, danodus__ulx3s_sms, emard__apple2fpga, emard__cortex, emard__esp32ecp5, emard__had2019-playground, emard__nes_ecp5, emard__next186, emard__oberon, emard__snes_mister_ulx3s, emard__st7789py_mpy, emard__ti99_2, emard__uk101onfpga, emard__ulx3s-bin, emard__ulx3s-misc, emard__ulx3s-passthru, emard__ulx3s_vic_20, f32c__f32c, gojimmypi__ttgf0p3-analog-uart-fsm-trng-lab, gojimmypi__ulx3s-examples, hanseo03__ulx3s-custom-riscv-cpu, hanseo03__ulx3s-vexriscv-soc, ironsteel__nes_ecp5, joaln27__koti, kost__ulx3s-ghdl-examples, lawrie__ulx3s_68k, lawrie__ulx3s_altair_8800, lawrie__ulx3s_amstrad_cpc, lawrie__ulx3s_atari_2600, lawrie__ulx3s_colecovision, lawrie__ulx3s_gamegear, lawrie__ulx3s_mac128, lawrie__ulx3s_msx, lawrie__ulx3s_ql, lawrie__ulx3s_sg_1000, lawrie__ulx3s_sms, lawrie__ulx3s_trs_80, lawrie__ulx3s_vic_20, lawrie__ulx3s_z80_template, lawrie__ulx3s_z80_trs80, lawrie__ulx3s_zx_spectrum, machdyne__nes_ecp5, mithro__asus-d16-ulx3s-interface, pnru__ti99, stefanhaslhofer__hardwaredesign, techprototyper__trs80-rev-z, ulx3s__apple2fpga, ulx3s__ulx3s-examples
• esp32-osd: emard__libxsvf-esp
• ethernet: antoinevg__cynthion-tutorials, antoinevg__hello-ethernet, cube1us__ibm1410fpga, datanoisetv__colorlight-i9-aes67, emard__ulx3s-bin, emard__ulx3s-misc, hdl4fpga__hdl4fpga, intergalaktik__ulx4m-ls, kazkojima__litex-lattice-ecp5-evn, litex-hub__litex-boards, lucysrausch__colorlight-led-cube, machdyne__zeitlos, micki0271__maeri, openconcepts-ar__accel2d, sefbkn__versa-ecp5-demo, splinedrive__kianriscv, tvelliott__dsp_ice, wuxx__colorlight-fpga-projects, yope__cpuv2
• examples: acairncross__clash-ulx3s-examples, adrmcintyre__vixen, ahamidi87__simpleblinky, andrewcapon__spinaltemplatesbtulx3s, angelojacobo__ulx3s_fpga_camera_streaming, angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670, asinghani__pifive-cpu, asinghani__ulx3s-vga-example, badgeteam__mch2022-firmware-ice40, brunolevy__learn-fpga, c-elegans__ulx3s_sdram, chiplet__ulx3s-blinky, chrismoos__m6502, cliffordwolf__icotools, cronokirby__ck-snes, dan-rodrigues__icestation-32, dan-rodrigues__ulx3s-bluetooth-gamepad, daveshah1__pmods, detegr__ulx3s-projects, dfiantworks__interactive-sim, dicethrow__amtest, diegob94__ulx3s_blink, dman2021__blink, dman2021__fpga_count, dman2021__uart_echo, doctorwkt__ulx3s-blinky, dpks2003__dice_crap_game, dpks2003__my_ulx3s_repo, dschaefer__fpga-template, dschaefer__ulx3s-ghdl-adder, emard__fpga_snake_game, emard__ledstrip, emard__ulx3s-bin, emard__ulx3s-misc, embeddeddojo__ulx3s_examples, emeb__ulx3s_6502, evgenymuryshkin__quokkaevaluation, f32c__arduino, flyingoverclouds__flocs-ulx3s-samples, fusesoc__blinky, gatecat__trellisboard, gmejiamtz__ulx3s-components, gojimmypi__nextpnr-issue235, gojimmypi__ulx3s-examples, goran-mahovlic__prjtrellis-led64x64, guztech__ulx3s-nmigen-examples, jadephilipoom__ulx3s-experiments, jderobot__fpga-robotics, jlopezr__mini-gpu, joshajohnson__ecp5-mini-projects, kbeckmann__pergola_projects, kost__ulx3s-ghdl-examples, l0r3m1psum__videogame_verilog, lawrie__blackicemxbook, lawrie__fpga_pio, lawrie__hdmi_examples, lawrie__spinalulx3s, lawrie__ulx3s-nmigen-examples, lawrie__ulx3s_examples, lawrie__ulx3s_vhdl_examples, lawrie__ulx4m_amaranth_examples, lawrie__ulx4m_examples, lawrie__verilog_examples, lcausevic__ulx3s_fpga_logic_structures, marph91__pocket-bnn, marph91__yaaes, mcejp__poly94, mit-plv__koika, mkvenkit__learn_fpga, mmicko__fpga101-workshop, mmicko__ulx3s-examples, mpardalos__clash-blinky, msrraju07__iop, mystorm-org__blackice-ii, nesl__ice40_examples, nicocavallu__rf-dds-lo, nullobject__counter-ulx3s, p-kraszewski__cs-ulx3s-03, pablogs9__rocketfpga, pcotret__ulx3s-examples, pepijndevos__rust-litex-example, pmezydlo__beaglewire, q3k__ulx3s-foss-blinky, ranzbak__fpga-workshop, remyciterin__adventoffpga, rhobbie__library704, richardegeorge__ulx3s-chase, richardegeorge__ulx3s-flipflop, richardegeorge__ulx3s-passthru, rob-ng15__pawsv2, robinsonb5__eightthirtytwodemos, saul-rodriguez__ulx3s, semify-eda__waveform-generator, seminlim__bluerv32, splinedrive__my_hdmi_device, srjilarious__fpga_start, stefanhaslhofer__hardwaredesign, stnolting__neorv32-setups, sylefeb__a5k, sylefeb__silice, tarik-hamedovic__sdr-hls, td0034__fpga, thata__ulx3s-playground, thata__ulx3s-uart-loopback, thewbi__ulx3s, thorkn__vexriscv-ulx3s-helloworld, thorkn__vexriscv-ulx3s-simple-plugin, thorkn__vga_pong, tinyvision-ai-inc__pico-ice-sdk, tommythorn__bluespec_blink, tristanitschner__ulx3s-examples, ulixxe__usb_cdc, ulx3s__anotherworld_fpga, ulx3s__blink, ulx3s__fpga-odysseus, ulx3s__hazard3-doom, ulx3s__ulx3s-examples, volnirr__verilog-uart, yowasp__toolchain-demo, zipotron__ulx3s_sdram8
• fft: alhusseingamal__r2sdf-fft, c-elegans__single_sdr, dylansebastianheredia__e155_tuner_project, enjoy-digital__litedsp, fulig__tinyfpga_fft, gage1999__fpga-sdr-receiver, ipmgroup__fftd, mattvenn__fpga-sdft, maxzischka1__fastfouriertransformproject, meharbaan2__systemverilog-ofdm-phy-core, ox-computing__real-time-analytics-fpga, vyges__fast-fourier-transform-ip, zipcpu__dblclockfft
• flash-emulator: arisotura__spi_flash, osresearch__spispy
• flash-spi: arisotura__spi_flash, bonfireprocessor__bonfire-basic-soc, cbalint13__e-verest, cheyao__icepi-zero, cheyao__nes_ecp5, damdoy__ice40_ultraplus_examples, emard__esp32ecp5, emard__galaksija, emard__had2019-playground, emard__nes_ecp5, emard__snes_mister_ulx3s, emard__tinyfpga-bootloader-ulx3s, emard__ulx3s-misc, emeb__up5k_osc, emeb__up5k_vga, f32c__f32c, f32c__tools, fedy0__neo, fpgawars__flix-v, gatecat__snes_mister_ulx3s, gildobjanschi__riscv_processor, glasgowembedded__glasgow, greatscottgadgets__cynthion, greatscottgadgets__luna, greatscottgadgets__luna-soc, gtjennings1__hyperbus, icebreaker-fpga__icetwang, im-tomu__foboot, john-k__spinose, lawrie__ulx3s_acorn_atom, lawrie__ulx3s_bbc_micro, machdyne__fpga-dac, machdyne__nes_ecp5, machdyne__tinydfu-bootloader, mb-sat__ulx3s-longwave-sdr, mcejp__poly94, mithro__asus-d16-ulx3s-interface, nickmqb__fpga_craft, nklabs__libnklabs-ulx3s, no2fpga__no2bootloader, osresearch__spispy, pablogs9__rocketfpga, punchthatface__tinydma, rxrbln__picorv32, smunaut__had2019-playground, smunaut__ice40-playground, smunaut__ice40linux, spinalhdl__saxonsoc, splinedrive__kianriscv, stnolting__neorv32, sylefeb__silice, tadeoroboticsgroup__axiomacore-328, tinyfpga__tinyfpga-bootloader, tinyvision-ai-inc__pico-ice-sdk, wifiboy__ok-ice40pro, wuxx__icesugar, yosyshq__picorv32, zipcpu__icozip
• floppy: glasgowembedded__glasgow, gojimmypi__z80386-ulx3s-doom
• fm-transmitter: f32c__f32c
• forth: jamesbowman__swapforth
• functional-safety: chipdesign-bv__cdriscv-32s-20
• game-controller: icebreaker-fpga__icetwang
• gamepad: wifiboy__ok-ice40pro
• gateware: x653__xv6-riscv-fpga
• goertzel: hariharan6307-coder__verilog-goertzel-audio-visualizer
• gpio: aravindrajeshkanna__vernier-rv32, cliffordwolf__icotools, dangerousprototypes__buspirateultrahdl, danielh186__6502-tapeout, danodus__onramp-fpga, dicethrow__amtest, eringr__nmigen_fibonacci, fm4dd__pmod-7seg9, fm4dd__pmod-charlcd, fusetim__rusty-soc, gildobjanschi__riscv_processor, glasgowembedded__glasgow, greatscottgadgets__cynthion, hexagon5un__hackaday_supercon_2019_logic_noise_fpga_workshop, htfab__asicle2, ibm2030__ibm2030, kelu124__un0rick, lawrie__blackicemxbook, lawrie__verilog_examples, lucasebskora__wav-player, makisness__inductiq, markus-zzz__max9850-test, mikeakohn__riscv_fpga, msiddalingaiah__centurion, mystorm-org__blackice-ii, nesl__ice40_examples, obijuan__open-fpga-verilog-tutorial, pmezydlo__beaglewire, seminlim__blueyosys, srjilarious__fpga_start, tadeoroboticsgroup__axiomacore-328, thezoq2__tinytapeout02, titouanc__fpga-scratchpad, ultraembedded__ecpix-5, wren6991__riscboy, zipcpu__icozip, zyedidia__riscinator
• gpmc-bus: pmezydlo__beaglewire
• gpu: dan-rodrigues__icestation-32, danodus__xgsoc, dibyx__flux, egorxe__openglory, gonsolo__borg, jlopezr__mini-gpu, maxhpc__ecpix-5, nickmqb__fpga_craft, nullobject__m68k-ulx3s, nullobject__riscv-ulx3s, openconcepts-ar__accel2d, remyciterin__3driscv, remyciterin__adventoffpga, rj45__vdp, smunaut__mch2022-ice40, sylefeb__silice, sylefeb__tinygpus, toni3141__rastericer, victor-fisyuk__voodoo-fpga-public, wren6991__riscboy
• graph-algorithm: acairncross__euphrates
• hd44780-lcd: fm4dd__pmod-charlcd
• hdl-language: acairncross__clash-ulx3s-examples, acairncross__euphrates, adrmcintyre__vixen, andrewcapon__spinaltemplatesbtulx3s, asinghani__pifive-cpu, bonfireprocessor__bonfire-ecp5-jtagg-led-demo, bqqbarbhg__blipv1, brunolevy__learn-fpga, dschaefer__fpga-template, dschaefer__ulx3s-ghdl-adder, evgenymuryshkin__quokkaevaluation, fusetim__rusty-soc, fywc__ulx3s_rv32i_processor, glasgowembedded__glasgow, guztech__ulx3s-nmigen-examples, lawrie__spinalulx3s, lawrie__ulx3s-nmigen-examples, lawrie__ulx3s_68k, lawrie__ulx3s_vhdl_examples, michaelbell__nanov, mit-plv__koika, mkvenkit__learn_fpga, mpardalos__clash-blinky, obijuan__open-fpga-verilog-tutorial, pcotret__ulx3s-examples, pietptr__ulx3s-dsp, remyciterin__adventoffpga, rob-ng15__pawsv2, sangwoojun__ulx3s_bsv, sylefeb__silice, tarik-hamedovic__sdr-hls, theperfectcomputer__learn-clash, theperfectcomputer__mannachip, thezoq2__tinytapeout02, thorkn__vga_clock_1, thorkn__vga_pong, tommythorn__bluespec_blink, vmware-archive__cascade
• hyperram: asinghani__pifive-cpu, greatscottgadgets__cynthion, joshajohnson__ecp5-mini-projects, markus-zzz__hyperram-test
• i2c: apfaudio__eurorack-pmod, asinghani__pifive-cpu, glasgowembedded__glasgow, greatscottgadgets__luna, kelu124__lit3rick, machdyne__tinydfu-bootloader, markus-zzz__max9850-test, ox-computing__real-time-analytics-fpga, pmezydlo__beaglewire, toasterllc__mdccode
• ide: gojimmypi__z80386-ulx3s-doom, zeldin__icegdrom
• joybus-io: jamchamb__cojiro
• jtag: antonblanchard__chiselwatt, aravindrajeshkanna__vernier-rv32, bonfireprocessor__bonfire-core, bonfireprocessor__bonfire-ecp5-jtagg-led-demo, c-elegans__ulx3s_sdram, carlosedp__chiselv, cbalint13__e-verest, cheyao__icepi-zero, chipdesign-bv__cdriscv-32s-20, chiplet__acorechip-ulx3s, cliffordwolf__icotools, daveshah1__ulx3s, emard__esp32ecp5, emard__fleafpga-jtag, emard__libxsvf-esp, emard__tinyfpga-bootloader-ulx3s, emard__ulx3s-jtagthru, emard__ulx3s-misc, emard__vhdl_c64_c1541_sd, emard__wifijtag, f32c__tools, gatecat__trellisboard, glasgowembedded__glasgow, gojimmypi__ttgf-uart-fsm-trng-lab, gojimmypi__ttgf0p3-analog-uart-fsm-trng-lab, gojimmypi__ttgf0p3-uart-fsm-trng-lab, gojimmypi__ttsky-uart-fsm-trng-lab, gojimmypi__ulx3s-examples, gojimmypi__z80386-ulx3s-doom, greatscottgadgets__cynthion, greatscottgadgets__luna, intergalaktik__ulx4m-ls, kholia__colorlight-5a-75b, lfglabs-dev__lean-silicon, marinsiric__ulx3s, mithro__asus-d16-ulx3s-interface, orbcode__orbtrace, q3k__ulx3s-foss-blinky, spritetm__hadbadge2019_fpgasoc, stnolting__neorv32, thorkn__vexriscv-ulx3s-simple-plugin, tomverbeure__ecp5_jtag, ulx3s__hazard3, ulx3s__hazard3-doom, wifiboy__ok-ice40pro, wren6991__hazard3, wren6991__hazard3-swd-soc, wuxx__colorlight-fpga-projects, wuxx__icesugar-pro, xtrinch__fpga-bitcoin-miner
• led: joshajohnson__ecp5-mini-projects
• led-drivers: emard__ledstrip, joaln27__cordic
• led-matrix: antoinevg__cynthion-tutorials, carlraymond__ulx3s-container, emard__ulx3s-misc, evgenymuryshkin__quokkaevaluation, glasgowembedded__glasgow, goran-mahovlic__prjtrellis-led64x64, icebreaker-fpga__icebreaker-verilog-examples, icebreaker-fpga__icetwang, jadephilipoom__ulx3s-experiments, kbob__icebreaker-candy, lawrie__ulx3s_examples, lucysrausch__colorlight-led-cube, smunaut__ice40-playground, ulx3s__fpga-odysseus, w531t4__fpga_led_display
• linux: aravindrajeshkanna__vernier-rv32, assured__ct-key, cheyao__oberon, ckdur__riscvconsole, daveshah1__ulx3s, dok3r__ulx3s-saxonsoc, dstrbad__fpga-soc-ml-accelerator, emard__ulx3s-bin, fpgawars__flix-v, hsa-ees__piconut, joaln27__koti, lawrie__spinalulx3s, litex-hub__linux-on-litex-vexriscv, machdyne__zeitlos, markus-zzz__zzz-rv, remyciterin__3driscv, smunaut__ice40linux, spinalhdl__saxonsoc, splinedrive__kianriscv, ulx3s__ulx3s-saxonsoc, wuxx__icesugar-pro, x653__xv6-riscv-fpga
• logic-analyzer: dicethrow__amtest, dpks2003__dice_crap_game, dulatello08__litex-cpu-testing, glasgowembedded__glasgow, jamon__jspcpu, johnazoidberg__ulx3s-espi-analyzer, krishkc5__trng-ring-oscillator, lawrie__ice40logicsniffer, lfglabs-dev__lean-silicon, orbcode__orbtrace, pavlenkog__ecp5_pcie_analyzer, rj45__vdp, semify-eda__waveform-generator, techprototyper__trs80-rev-z, tomverbeure__ecp5_jtag
• logic-analyzer-buffer: dangerousprototypes__buspirateultrahdl
• lvds-display: emard__ulx3s-misc
• mac-unit: uttamcoomar__mac-units-for-various-number-formats
• mandelbrot-accel: mikeakohn__riscv_fpga
• microcode: msiddalingaiah__centurion
• micropython: mmicko__fpga101-workshop
• ml-accelerator: advikbahadur__ulx3s-superresolution-cnn, anmho__ulx3_bsv, dlobato__tfmicro-on-litex-vexriscv, dstrbad__fpga-soc-ml-accelerator, dstrbad__janestreet-advent-fpga, fedy0__zta, ghaworth__ulx3s-tinyai, google__cfu-playground, hsa-ees__piconut, jeli180__shape-inference-soc, marph91__pocket-bnn, micki0271__maeri, ox-computing__real-time-analytics-fpga, sangwoojun__ulx3s_bsv, seminlim__sway, seminlim__zfpe, tucanae47__litex_etpu, uttamcoomar__nn_digits
• mlp: jeli180__shape-inference-soc
• mmu: aravindrajeshkanna__vernier-rv32
• multi-board: alangarf__apple-one, cheyao__oberon, circuit-killer__fpga-usbserial, danodus__ecp5_hdmi_audio_video, emard__vhdl_c64_c1541_sd, jamesrosssharp__1_bit_am, lawrie__jupiter_ace, lawrie__ulx3s_atari_2600, lawrie__ulx3s_colecovision, linuxjedi__minimig_ecs, robinsonb5__eightthirtytwodemos, smunaut__ice40-playground, splinedrive__my_hdmi_device, ulx3s__hazard3-doom, w531t4__fpga_led_display
• none: mkvenkit__ulx3s_examples, pfontvilanova__pfforthmachine
• oled-lcd: assured__ct-key, badgeteam__mch2022-firmware-ice40, carlraymond__ulx3s-container, circuit-killer__fpga-usbhid-host, daveshah1__pmods, emard__apple2fpga, emard__st7789py_mpy, emard__ulx3s-misc, emard__ulx3s-passthru, f32c__f32c, fm4dd__pmod-charlcd, glasgowembedded__glasgow, guztech__ulx3s-nmigen-examples, hdl4fpga__hdl4fpga, lawrie__slabboy, lawrie__spinalulx3s, lawrie__ulx3s-nmigen-examples, lawrie__ulx3s_atari_2600, lawrie__ulx3s_cpm_z80, lawrie__ulx3s_examples, lawrie__ulx3s_gamegear, lawrie__ulx3s_ql, lawrie__ulx3s_sms, lawrie__ulx3s_z80_template, lawrie__ulx3s_z80_trs80, lawrie__ulx4m_amaranth_examples, lucasebskora__wav-player, mikeakohn__apollo11_fpga, mmicko__fpga101-workshop, msinger__iceboy, nh428__ulx3s-tft-display-sobel-object-detection, nullobject__m68k-ulx3s, nullobject__riscv-ulx3s, nusgreyhats__greybadge25, osresearch__up5k, pmezydlo__beaglewire, smunaut__mch2022-ice40, splinedrive__kianriscv, stuij__odyssey, sylefeb__silice, td0034__fpga, toni3141__rastericer, tucanae47__ulx3s-experiments, ulx3s__fpga-odysseus, wifiboy__ok-ice40pro, wuxx__colorlight-fpga-projects, wuxx__icesugar
• os-software: andreaspirklbauer__oberon-extended
• pcb: gtjennings1__hyperbus
• pcie: whitequark__yumewatari, zyp__katsuo-pcie, zyp__litepcie-katsuo-poc
• pio: lawrie__fpga_pio
• pmod-hardware: goran-mahovlic__ulx3s-pmod
• programmer-tool: circuit-killer__fpga-usbserial, cliffordwolf__icotools, daveshah1__prjtrellis-dvi, emard__esp32ecp5, emard__fleafpga-jtag, emard__ulx3s-bin, emard__ulx3s-jtagthru, emard__wifijtag, f32c__fpgarduino, f32c__tools, glasgowembedded__glasgow, gojimmypi__ulx3s-examples, kost__fujprog, mithro__asus-d16-ulx3s-interface, q3k__ulx3s-foss-blinky, ruebenschus__atari-fpcartridge, trabucayre__openfpgaloader, wren6991__hazard3-swd-soc, yowasp__toolchain-demo
• ps2: alangarf__apple-one, basman74__oberon_sdram, cheyao__icepi-zero, cheyao__oberon, danodus__msx_fpga, danodus__onramp-fpga, danodus__ulx3s_68k, danodus__xgsoc, emard__apple-one, emard__apple2fpga, emard__galaksija, emard__jupiter_ace, emard__minimig_ecs, emard__next186, emard__oberon, emard__papilio-arcade, emard__ti99_2, emard__uk101onfpga, emard__ulx3s-misc, emard__ulx3s_c64, emard__ulx3s_galaksija, emard__ulx3s_vic_20, emard__usb_host, emard__vhdl_c64_c1541_sd, emard__vhdl_phoenix, emeb__up5k_vga, f32c__f32c, glasgowembedded__glasgow, gojimmypi__z80386-ulx3s-doom, hoglet67__ice40atom, hoglet67__ice40beeb, lawrie__apple-one, lawrie__jupiter_ace, lawrie__spinalulx3s, lawrie__ulx3s-nmigen-examples, lawrie__ulx3s_acorn_atom, lawrie__ulx3s_amstrad_cpc, lawrie__ulx3s_cpm_z80, lawrie__ulx3s_examples, lawrie__ulx3s_gamegear, lawrie__ulx3s_mac128, lawrie__ulx3s_msx, lawrie__ulx3s_sg_1000, lawrie__ulx3s_trs_80, lawrie__ulx3s_z80_template, lawrie__ulx3s_z80_trs80, lawrie__ulx3s_zx81, lawrie__ulx3s_zx_spectrum, lawrie__ulx4m_amaranth_examples, lawrie__verilog_examples, linuxjedi__minimig_ecs, pnru__ti99, rxrbln__picorv32, spinalhdl__saxonsoc, stuij__odyssey, techprototyper__trs80-rev-z, ulx3s__apple2fpga, ulx3s__ulx3s_zx81
• psram: gildobjanschi__riscv_processor, gtjennings1__hyperbus, markus-zzz__hyperram-test, smunaut__ice40-playground, smunaut__ice40linux, smunaut__mch2022-ice40, spritetm__hadbadge2019_fpgasoc
• pwm: pmezydlo__beaglewire
• radio: joaln27__cordic, nicocavallu__fpga-lora-receiver, nicocavallu__rf-fft-engine
• radio-rx: alberto-grl__1bitsdr, amin005__skywave_sdr, cariboulabs__cariboulite, emard__flearadio, emeb__iceradio, emeb__rpi_rxadc, greatscottgadgets__amalthea, greatscottgadgets__hackrf, jamesrosssharp__1_bit_am, jamesrosssharp__ulx3s_mixer_pcb, mb-sat__ulx3s-longwave-sdr, meharbaan2__systemverilog-ofdm-phy-core, nicocavallu__rf-dds-lo, tarik-hamedovic__sdr-hls, zipcpu__sdr
• radio-tx: agamez__whisperice, cariboulabs__cariboulite, emard__rdsfpga, greatscottgadgets__hackrf, jamesrosssharp__1_bit_am, kbeckmann__pergola_projects, meharbaan2__systemverilog-ofdm-phy-core, mehrdadh__lora-modulator, zipcpu__sdr
• retro-arcade: abhinavputhran__ttysky-raycast-test, cliffordwolf__icotools, dan-rodrigues__icestation-32, emard__fpga_snake_game, emard__papilio-arcade, emard__vhdl_phoenix, htfab__asicle2, lawrie__hdmi_examples, lawrie__ulx3s_ay_3_8500, lawrie__ulx3s_examples, remyciterin__dooom, sylefeb__a5k, sylefeb__tinygpus, ulx3s__fpga-odysseus
• retro-computer: alangarf__apple-one, badgeteam__mch2022-firmware-ice40, basman74__next186, basman74__oberon_sdram, cheyao__oberon, chriscamacho__yazsof, cube1us__ibm1410fpga, danodus__msx_fpga, danodus__ulx3s_68k, daveshah1__up5k-demos, emard__apple-one, emard__apple2fpga, emard__cortex, emard__galaksija, emard__jupiter_ace, emard__minimig_ecs, emard__next186, emard__oberon, emard__ti99_2, emard__uk101onfpga, emard__ulx3s-bin, emard__ulx3s_c64, emard__ulx3s_galaksija, emard__ulx3s_vic_20, emard__vhdl_c64_c1541_sd, emeb__up5k_vga, evansm7__arcdvi, felipesanches__anotherworld_fpga, gojimmypi__z80386-ulx3s-doom, hoglet67__ice40atom, hoglet67__ice40beeb, ibm2030__ibm2030, lawrie__apple-one, lawrie__blackicemxbook, lawrie__fpgacosmacelf, lawrie__jupiter_ace, lawrie__ulx3s-nmigen-examples, lawrie__ulx3s_68k, lawrie__ulx3s_acorn_atom, lawrie__ulx3s_altair_8800, lawrie__ulx3s_amstrad_cpc, lawrie__ulx3s_bbc_micro, lawrie__ulx3s_cpm_z80, lawrie__ulx3s_examples, lawrie__ulx3s_mac128, lawrie__ulx3s_msx, lawrie__ulx3s_pdp_11, lawrie__ulx3s_ql, lawrie__ulx3s_trs_80, lawrie__ulx3s_vic_20, lawrie__ulx3s_z80_template, lawrie__ulx3s_z80_trs80, lawrie__ulx3s_zx81, lawrie__ulx3s_zx_spectrum, lawrie__verilog_examples, linuxjedi__minimig_ecs, markus-zzz__myc64, mikeakohn__apollo11_fpga, mmicko__fpga101-workshop, msiddalingaiah__centurion, nullobject__m68k-ulx3s, pnru__ti99, ruebenschus__atari-fpcartridge, schlae__graphics-gremlin, speccery__icy99, sylefeb__silice, techprototyper__trs80-rev-z, thata__td4-ulx3s, ulx3s__apple2fpga, ulx3s__fpga-odysseus, ulx3s__galaksija, ulx3s__ulx3s_zx81, wifiboy__ok-ice40pro, wuxx__icesugar
• retro-console: cheyao__nes_ecp5, cheyao__sega-sms, chrislikescisco__nes-fpga, danodus__ulx3s_sms, doctorwkt__verilog_tic-tac-toe, emard__nes_ecp5, emard__snes_mister_ulx3s, emard__verilog_tic-tac-toe, gatecat__snes_mister_ulx3s, ironsteel__nes_ecp5, lawrie__slabboy, lawrie__ulx3s_atari_2600, lawrie__ulx3s_colecovision, lawrie__ulx3s_gamegear, lawrie__ulx3s_sg_1000, lawrie__ulx3s_sms, machdyne__nes_ecp5, msinger__iceboy, quigleyj97__nesgate, rob-ng15__pawsv2, victor-fisyuk__voodoo-fpga-public, zeldin__icegdrom
• retro-console-vm: noxharmonium__sirc
• rgb-led: rschlaikjer__fpga-3-softcores
• riscv-learning: jadephilipoom__ulx3s-experiments
• rtc-power: emard__ulx3s-misc, hsa-ees__piconut
• sata: enjoy-digital__litesata
• sdcard: aravindrajeshkanna__vernier-rv32, bonfireprocessor__bonfire-basic-soc, cheyao__icepi-zero, cheyao__nes_ecp5, cheyao__oberon, cheyao__sega-sms, danodus__onramp-fpga, danodus__ulx3s_sms, danodus__xgsoc, dstrbad__fpga-soc-ml-accelerator, emard__apple2fpga, emard__esp32ecp5, emard__minimig_ecs, emard__nes_ecp5, emard__next186, emard__oberon, emard__snes_mister_ulx3s, emard__ti99_2, emard__ulx3s-misc, emard__ulx3s-passthru, emard__ulx3s_vic_20, emard__vhdl_c64_c1541_sd, f32c__f32c, fusetim__rusty-soc, gatecat__snes_mister_ulx3s, intergalaktik__ulx4m-ls, ironsteel__nes_ecp5, joaln27__koti, lawrie__ulx3s_amstrad_cpc, lawrie__ulx3s_bbc_micro, lawrie__ulx3s_cpm_z80, lawrie__ulx3s_msx, lawrie__ulx3s_ql, lawrie__ulx3s_sms, lawrie__ulx3s_trs_80, lawrie__ulx3s_vic_20, lawrie__ulx3s_z80_template, lawrie__ulx3s_z80_trs80, lawrie__ulx3s_zx_spectrum, litex-hub__linux-on-litex-vexriscv, litex-hub__litex-boards, logoposeidon__ulx3sjukebox, lucasebskora__wav-player, machdyne__nes_ecp5, machdyne__zeitlos, rob-ng15__pawsv2, spinalhdl__saxonsoc, sylefeb__silice, td0034__fpga, techprototyper__trs80-rev-z, toasterllc__mdccode, x653__xv6-riscv-fpga, zeldin__icegdrom, zipcpu__sdspi
• sdram: advikbahadur__ulx3s-superresolution-cnn, anmho__ulx3_bsv, aravindrajeshkanna__vernier-rv32, arisotura__spi_flash, assured__ct-key, basman74__oberon_sdram, bonfireprocessor__bonfire-basic-soc, bqqbarbhg__blipv1, brunolevy__learn-fpga, businessmanraduc__doggo-v6, c-elegans__ulx3s_sdram, cheyao__icepi-zero, danodus__onramp-fpga, danodus__ulx3s_68k, danodus__xgsoc, daveshah1__ulx3s, dicethrow__amaram, dlobato__cps1-musicbox, dlobato__tfmicro-on-litex-vexriscv, dok3r__ulx3s-saxonsoc, dulatello08__neocorefx-dram, emard__cortex, emard__minimig_ecs, emard__nes_ecp5, emard__next186, emard__oberon, emard__ulx3s-bin, emard__ulx3s-emi, emard__ulx3s-misc, f32c__f32c, fpgawars__flix-v, gage1999__fpga-sdr-receiver, ghaworth__ulx3s-tinyai, gildobjanschi__riscv_processor, gojimmypi__z80386-ulx3s-doom, gonsolo__borg, harrowm__mackerel_030f, hdl4fpga__hdl4fpga, ironsteel__nes_ecp5, jeli180__shape-inference-soc, jlopezr__mini-gpu, joaln27__koti, lawrie__ulx3s-nmigen-examples, lawrie__ulx3s_examples, lawrie__ulx3s_mac128, lawrie__ulx3s_sg_1000, lawrie__ulx3s_sms, lawrie__ulx4m_amaranth_examples, lawrie__ulx4m_examples, linuxjedi__minimig_ecs, litex-hub__linux-on-litex-vexriscv, litex-hub__litex-boards, machdyne__zeitlos, markus-zzz__zzz-rv, mcejp__poly94, micki0271__maeri, msrraju07__iop, nh428__ulx3s-tft-display-sobel-object-detection, nklabs__libnklabs-ulx3s, osresearch__spispy, pmezydlo__beaglewire, remyciterin__3driscv, remyciterin__dooom, riltonf__thermal_camera_ulx3s, robinsonb5__eightthirtytwodemos, rxrbln__picorv32, sangwoojun__ulx3s_bsv, seminlim__blueyosys, spinalhdl__saxonsoc, splinedrive__kianriscv, sylefeb__silice, thewbi__ulx3s, toasterllc__mdccode, ulx3s__hazard3, ulx3s__ulx3s-saxonsoc, victor-fisyuk__voodoo-fpga-public, wren6991__hazard3-swd-soc, wuxx__colorlight-fpga-projects, wuxx__icesugar-pro, zipotron__neorv32-complex-setups, zipotron__ulx3s_sdram8
• serdes: enjoy-digital__liteiclink
• serdes-pcie-sata: blazra__tdr, ecp5-pcie__ecp5-pcie, enjoy-digital__liteiclink, enjoy-digital__litesata, intergalaktik__ulx4m-ls, kazkojima__litex-lattice-ecp5-evn, litex-hub__litex-boards, pavlenkog__ecp5_pcie_analyzer, whitequark__yumewatari, zyp__katsuo-pcie, zyp__litepcie-katsuo-poc
• seven-segment-display: fm4dd__pmod-7seg9
• sha256: xtrinch__fpga-bitcoin-miner
• shader-core: dibyx__flux
• simulation-framework: dfiantworks__interactive-sim
• soc-cpu: adrmcintyre__vixen, anmho__ulx3_bsv, antoinevg__cynthion-tutorials, antonblanchard__chiselwatt, aravindrajeshkanna__vernier-rv32, asinghani__pifive-cpu, assured__ct-key, badgeteam__mch2022-firmware-ice40, basman74__next186, basman74__oberon_sdram, bhouvana__aegis-x86-processor, bnossum__midgetv, bonfireprocessor__bonfire-basic-soc, bonfireprocessor__bonfire-core, brunolevy__learn-fpga, brunolevy__tordboyau, businessmanraduc__doggo-v6, callummcduff-droid__cpu, carlosedp__chiselv, cbalint13__e-verest, chipdesign-bv__cdriscv-32s-20, chipflow__example-socs, chiplet__acorechip-ulx3s, chriscamacho__yazsof, chrismoos__m6502, ckdur__riscvconsole, cliffordwolf__icotools, damdoy__ice40_ultraplus_examples, dan-rodrigues__icestation-32, danodus__onramp-fpga, danodus__ulx3s_68k, danodus__xgsoc, darklife__darkriscv, datanoisetv__colorlight-i9-aes67, daveshah1__ulx3s, dlobato__cps1-musicbox, dlobato__tfmicro-on-litex-vexriscv, dok3r__ulx3s-saxonsoc, dstrbad__fpga-soc-ml-accelerator, dulatello08__litex-cpu-testing, dulatello08__neocore-fx, egorxe__openglory, emard__had2019-playground, emard__minimig_ecs, emard__next186, emard__oberon, emard__prjtrellis-picorv32, emard__ulx3s-bin, emard__usb_host, emeb__ulx3s_6502, emeb__up5k_osc, emeb__up5k_vga, f32c__arduino, f32c__f32c, f32c__fpgarduino, fedy0__neo, fedy0__zta, fpgawars__flix-v, fusetim__rusty-soc, fywc__ulx3s_rv32i_processor, gildobjanschi__riscv_processor, gojimmypi__z80386-ulx3s-doom, gonsolo__borg, google__cfu-playground, greatscottgadgets__cynthion, greatscottgadgets__luna-soc, gregdavill__luna-usb-serial-acm, gtjennings1__hyperbus, hanseo03__ulx3s-custom-riscv-cpu, hanseo03__ulx3s-vexriscv-soc, hassan2203__system-on-chip-soc-design-and-verification, hsa-ees__piconut, icebreaker-fpga__icetwang, im-tomu__foboot, im-tomu__fomu-workshop, jamesbowman__swapforth, jamon__jspcpu, jeli180__shape-inference-soc, jerry-d__sympl_ieee754-2019_isa, jlopezr__mini-gpu, joaln27__koti, john-k__spinose, johngannon4__riscv-cpu-portfolio, joshajohnson__ecp5-mini-projects, kbeckmann__pergola_projects, kulp__tenyr, lawrie__fpgacosmacelf, lawrie__spinalulx3s, lawrie__ulx3s_examples, lawrie__ulx4m_amaranth_examples, lawrie__ulx4m_examples, lazardjurovic__edulent_rtl, litex-hub__linux-on-litex-vexriscv, lucasebskora__wav-player, machdyne__zeitlos, markus-zzz__hyperram-test, markus-zzz__max9850-test, markus-zzz__zzz-rv, mcejp__poly94, michaelbell__nanov, micki0271__maeri, mikeakohn__apollo11_fpga, mikeakohn__riscv_fpga, mit-plv__koika, mmicko__fpga101-workshop, msiddalingaiah__centurion, nickmqb__fpga_craft, nklabs__libnklabs-ulx3s, no2fpga__no2bootloader, nullobject__m68k-ulx3s, nullobject__riscv-ulx3s, nusgreyhats__greybadge25, obijuan__open-fpga-verilog-tutorial, openconcepts-ar__accel2d, orangecrab-fpga__orangecrab-examples, osmocom__osmo-e1-hardware, pepijndevos__litedhrystone, pepijndevos__rust-litex-example, quigleyj97__nesgate, racerxdl__colorlight-picorv32, remyciterin__3driscv, remyciterin__adventoffpga, remyciterin__dooom, rob-ng15__pawsv2, robinsonb5__eightthirtytwodemos, rschlaikjer__fpga-3-softcores, rxrbln__picorv32, sangwoojun__ulx3s_bsv, saul-rodriguez__ulx3s, secworks__cryptkey, sefbkn__versa-ecp5-demo, semify-eda__waveform-generator, seminlim__bluerv32, seth16225__riscv-core-portfolio, smunaut__had2019-playground, smunaut__ice40-playground, smunaut__ice40linux, smunaut__mch2022-ice40, spinalhdl__saxonsoc, splinedrive__kianriscv, spritetm__hadbadge2019_fpgasoc, stefanhaslhofer__hardwaredesign, stnolting__neorv32, stnolting__neorv32-setups, sylefeb__silice, tadeoroboticsgroup__axiomacore-328, thorkn__vexriscv-ulx3s-helloworld, thorkn__vexriscv-ulx3s-simple-plugin, tinyvision-ai-inc__pico-ice-sdk, titouanc__fpga-scratchpad, tom7980__ulxws, tucanae47__litex_etpu, ultraembedded__ecpix-5, ulx3s__fpga-odysseus, ulx3s__hazard3, ulx3s__hazard3-doom, ulx3s__ulx3s-saxonsoc, vladov3000__ulx3s, wifiboy__ok-ice40pro, wren6991__hazard3, wren6991__hazard3-swd-soc, wren6991__riscboy, wuxx__colorlight-fpga-projects, wuxx__icesugar, wuxx__icesugar-pro, x653__xv6-riscv-fpga, yope__cpuv2, yosyshq__picorv32, zeldin__icegdrom, zipcpu__icozip, zipotron__neorv32-complex-setups, zipotron__ziposoc, zyedidia__riscinator
• sound-chips: thorkn__layr_audio
• spi: assured__ct-key, basman74__oberon_sdram, cariboulabs__cariboulite, cliffordwolf__icotools, dangerousprototypes__buspirateultrahdl, dicethrow__amtest, dylansebastianheredia__e155_tuner_project, fulig__tinyfpga_fft, fusetim__rusty-soc, glasgowembedded__glasgow, greatscottgadgets__luna, harrowm__mackerel_030f, hoglet67__ice40atom, hoglet67__ice40beeb, ipmgroup__fftd, kelu124__lit3rick, kelu124__un0rick, lawrie__verilog_examples, litex-hub__litex-boards, markus-zzz__zzz-rv, michaelbell__nanov, mikeakohn__apollo11_fpga, mikeakohn__riscv_fpga, mole99__tt05-one-sprite-pony, mysteriouswolf__vna_fpga_dsp, obijuan__open-fpga-verilog-tutorial, ox-computing__real-time-analytics-fpga, pmezydlo__beaglewire, toasterllc__mdccode, tvelliott__dsp_ice, ultraembedded__ecpix-5, ulx3s__hazard3, voltcyclone__hurra-fpga, x653__xv6-riscv-fpga, zipcpu__sdspi
• spram: damdoy__ice40_ultraplus_examples
• sram: kelu124__un0rick, mystorm-org__blackice-ii, wren6991__riscboy, zipcpu__icozip, zyedidia__riscinator
• swd-debug: orbcode__orbtrace, wren6991__hazard3-swd-soc
• synth-audio: bit-hack__icesid, bjonnh__ulx3s-synth, daglem__redip-sid, dlobato__cps1-musicbox, emard__rdsfpga, emard__synthowheel, emeb__up5k_osc, gojimmypi__z80386-ulx3s-doom, greatscottgadgets__cynthion-uac, hexagon5un__hackaday_supercon_2019_logic_noise_fpga_workshop, hoglet67__ice40atom, hoglet67__ice40beeb, icebreaker-fpga__icebreaker-verilog-examples, lawrie__spinalulx3s, lawrie__ulx3s_amstrad_cpc, lawrie__ulx3s_mac128, lawrie__ulx3s_zx_spectrum, lawrie__ulx4m_amaranth_examples, lawrie__verilog_examples, markus-zzz__myc64, mikeakohn__riscv_fpga, nullobject__riscv-ulx3s, obijuan__open-fpga-verilog-tutorial, pablogs9__rocketfpga, semify-eda__waveform-generator, spritetm__hadbadge2019_fpgasoc, thorkn__spinalsynth_ulx3s, tristanitschner__ulx3s-examples, tvelliott__dsp_ice
• timer: antoinevg__cynthion-tutorials, aravindrajeshkanna__vernier-rv32, gildobjanschi__riscv_processor, greatscottgadgets__luna-soc, msiddalingaiah__centurion, obijuan__open-fpga-verilog-tutorial, rschlaikjer__fpga-3-softcores, secworks__cryptkey, tadeoroboticsgroup__axiomacore-328, ultraembedded__ecpix-5, zyedidia__riscinator
• tiny-tapeout: michaelbell__nanov
• toolchain: alpin3__ulx3s, andrewcapon__spinaltemplatesbtulx3s, cheyao__oberon, dok3r__ulx3s-build, dok3r__ulx3s-saxonsoc, emard__tinyfpga-bootloader-ulx3s, enjoy-digital__litedsp, evgenymuryshkin__quokkaevaluation, f32c__arduino, f32c__fpgarduino, gatecat__trellisboard, ghaworth__ulx3s-bldc-foc, gmejiamtz__ulx3s-components, gojimmypi__nextpnr-issue235, gojimmypi__ttgf-uart-fsm-trng-lab, gojimmypi__ttgf0p3-uart-fsm-trng-lab, gojimmypi__ttsky-uart-fsm-trng-lab, google__cfu-playground, hsa-ees__piconut, kost__fujprog, kost__ulx3s-ghdl-examples, kulp__tenyr, litex-hub__litex-boards, mpardalos__clash-blinky, seminlim__bluerv32, ulx3s__tt-support-tools, ulx3s__ulx3s-examples, ulx3s__ulx3s-saxonsoc, vladov3000__ulx3s, yowasp__toolchain-demo, zipcpu__dblclockfft
• trng: secworks__cryptkey
• uart: acairncross__euphrates, advikbahadur__ulx3s-superresolution-cnn, agamez__whisperice, alangarf__apple-one, anmho__ulx3_bsv, antoinevg__cynthion-tutorials, aravindrajeshkanna__vernier-rv32, arisotura__spi_flash, asinghani__advent-of-hardcaml-2024, asinghani__advent-of-hardcaml-2025, asinghani__pifive-cpu, basman74__oberon_sdram, bjonnh__ulx3s-synth, bonfireprocessor__bonfire-basic-soc, bonfireprocessor__bonfire-core, businessmanraduc__doggo-v6, carlosedp__chisel-fpga-pinfinder, cbalint13__e-verest, cgarryza__advent-of-camel-2025, cheyao__icepi-zero, chriscamacho__yazsof, chrismoos__m6502, circuit-killer__fpga-usbserial, cliffordwolf__icotools, cronokirby__ck-snes, cube1us__ibm1410fpga, dan-rodrigues__ulx3s-bluetooth-gamepad, dangerousprototypes__buspirateultrahdl, danodus__onramp-fpga, danodus__ulx3s_68k, danodus__xgsoc, darklife__darkriscv, daveshah1__ulx3s, dlobato__cps1-musicbox, dman2021__uart_echo, doctorwkt__ulx3s-blinky, doctorwkt__verilog_tic-tac-toe, dstrbad__fpga-soc-ml-accelerator, dstrbad__janestreet-advent-fpga, dulatello08__litex-cpu-testing, dulatello08__neocore-fx, dulatello08__neocorefx-dram, dulatello08__ulx3s-tests, emard__apple-one, emard__cortex, emard__galaksija, emard__oberon, emard__prjtrellis-picorv32, emard__snes_mister_ulx3s, emard__uk101onfpga, emard__ulx3s-misc, emard__ulx3s-passthru, emard__ulx3s_galaksija, emard__ulx3s_vic_20, emard__usb_host, emard__verilog_tic-tac-toe, embeddeddojo__ulx3s_examples, emeb__ulx3s_6502, emeb__up5k_osc, emeb__up5k_vga, evgenymuryshkin__quokkaevaluation, f32c__f32c, f32c__tools, fedy0__neo, fpgawars__flix-v, gatecat__snes_mister_ulx3s, gergoerdi__advent-of-clash-2025, gildobjanschi__riscv_processor, glasgowembedded__glasgow, gojimmypi__ttgf-uart-fsm-trng-lab, gojimmypi__ttgf0p3-analog-uart-fsm-trng-lab, gojimmypi__ttgf0p3-uart-fsm-trng-lab, gojimmypi__ttsky-uart-fsm-trng-lab, gojimmypi__z80386-ulx3s-doom, gonsolo__borg, greatscottgadgets__cynthion, greatscottgadgets__luna, greatscottgadgets__luna-soc, gtjennings1__hyperbus, hanseo03__ulx3s-custom-riscv-cpu, hanseo03__ulx3s-vexriscv-soc, harrowm__mackerel_030f, hdl4fpga__hdl4fpga, hsa-ees__piconut, icebreaker-fpga__icebreaker-verilog-examples, ipmgroup__fftd, jamchamb__cojiro, jamesbowman__swapforth, jeli180__shape-inference-soc, jerry-d__sympl_ieee754-2019_isa, jlopezr__mini-gpu, joaln27__koti, johnazoidberg__ulx3s-espi-analyzer, joshajohnson__ecp5-mini-projects, kbeckmann__pergola_projects, kholia__colorlight-5a-75b, krishkc5__trng-ring-oscillator, lawrie__apple-one, lawrie__fpgacosmacelf, lawrie__ice40logicsniffer, lawrie__jupiter_ace, lawrie__ulx3s-nmigen-examples, lawrie__ulx3s_atari_2600, lawrie__ulx3s_bbc_micro, lawrie__ulx3s_cpm_z80, lawrie__ulx3s_examples, lawrie__ulx3s_ql, lawrie__ulx3s_vic_20, lawrie__ulx3s_z80_template, lawrie__ulx3s_z80_trs80, lawrie__ulx4m_examples, lfglabs-dev__lean-silicon, litex-hub__linux-on-litex-vexriscv, makisness__inductiq, marinsiric__ulx3s, markus-zzz__hyperram-test, markus-zzz__zzz-rv, marph91__pocket-bnn, maxhpc__ecpix-5, maxzischka1__fastfouriertransformproject, mcejp__poly94, mebner86__icesugar-pro_sound2fft, michaelbell__nanov, mikeakohn__apollo11_fpga, mikeakohn__riscv_fpga, mit-plv__koika, mithro__asus-d16-ulx3s-interface, mkvenkit__learn_fpga, mmicko__fpga101-workshop, msinger__iceboy, mystorm-org__blackice-ii, nklabs__libnklabs-ulx3s, nullobject__m68k-ulx3s, nullobject__riscv-ulx3s, nusgreyhats__greybadge25, obijuan__open-fpga-verilog-tutorial, osresearch__spispy, osresearch__up5k, pablogs9__rocketfpga, pcotret__ulx3s-examples, pmezydlo__beaglewire, racerxdl__colorlight-picorv32, remyciterin__3driscv, remyciterin__dooom, rob-ng15__pawsv2, rschlaikjer__fpga-3-softcores, rxrbln__picorv32, sangwoojun__ulx3s_bsv, saul-rodriguez__ulx3s, secworks__cryptkey, sefbkn__versa-ecp5-demo, seminlim__bluerv32, seminlim__sway, smunaut__ice40linux, spinalhdl__saxonsoc, splinedrive__kianriscv, spritetm__hadbadge2019_fpgasoc, stnolting__neorv32, stnolting__neorv32-setups, sylefeb__silice, tadeoroboticsgroup__axiomacore-328, tarik-hamedovic__sdr-hls, techprototyper__trs80-rev-z, thata__ulx3s-uart-loopback, theperfectcomputer__learn-clash, theperfectcomputer__mannachip, thorkn__vexriscv-ulx3s-helloworld, thorkn__vexriscv-ulx3s-simple-plugin, tinyvision-ai-inc__pico-ice-sdk, tristanitschner__ulx3s-examples, ultraembedded__ecpix-5, ulx3s__fpga-odysseus, ulx3s__galaksija, ulx3s__hazard3, ulx3s__hazard3-doom, uttamcoomar__mac-units-for-various-number-formats, uttamcoomar__nn_digits, vmware-archive__cascade, volnirr__verilog-uart, voltcyclone__hurricanefpga, w531t4__fpga_led_display, wifiboy__ok-ice40pro, wren6991__hazard3, wren6991__hazard3-swd-soc, wren6991__riscboy, wuxx__colorlight-fpga-projects, wuxx__icesugar, wuxx__icesugar-pro, x653__xv6-riscv-fpga, xtrinch__fpga-bitcoin-miner, yope__cpuv2, yosyshq__picorv32, zipcpu__icozip, zipotron__ziposoc, zyedidia__riscinator
• ultrasound-acquisition: kelu124__lit3rick, kelu124__un0rick
• ultrasound-envelope-dft: kelu124__lit3rick
• ultrasound-pulser: kelu124__lit3rick, kelu124__un0rick
• ulx4m: cheyao__nes_ecp5, danodus__ulx3s_sms, intergalaktik__ulx4m-ls, lawrie__ulx4m_amaranth_examples, lawrie__ulx4m_examples, litex-hub__litex-boards, ulx3s__hazard3, ulx3s__hazard3-doom
• usb-analyzer: greatscottgadgets__cynthion, greatscottgadgets__luna
• usb-device: antoinevg__cynthion-tutorials, bit-hack__icesid, cheyao__icepi-zero, circuit-killer__fpga-usbserial, daglem__redip-sid, dicethrow__amtest, emard__had2019-playground, emard__ulx3s-misc, f32c__f32c, fdarling__orangecrab-usb-cdc-demo, glasgowembedded__glasgow, greatscottgadgets__amalthea, greatscottgadgets__cynthion, greatscottgadgets__cynthion-uac, greatscottgadgets__luna, greatscottgadgets__luna-soc, gregdavill__luna-usb-serial-acm, hdl4fpga__hdl4fpga, icebreaker-fpga__icetwang, im-tomu__foboot, im-tomu__fomu-workshop, joshajohnson__ecp5-mini-projects, machdyne__tinydfu-bootloader, mangelajo__orangecrab-usb, no2fpga__no2bootloader, orangecrab-fpga__orangecrab-examples, orbcode__orbtrace, osmocom__osmo-e1-hardware, osresearch__spispy, osresearch__up5k, smunaut__had2019-playground, smunaut__ice40-playground, spritetm__hadbadge2019_fpgasoc, tinyfpga__tinyfpga-bootloader, tinyvision-ai-inc__pico-ice-sdk, ulixxe__usb_cdc, voltcyclone__hurra-fpga, wuxx__icesugar
• usb-host: alangarf__apple-one, apfaudio__guh, cheyao__nes_ecp5, cheyao__oberon, cheyao__sega-sms, circuit-killer__fpga-usbhid-host, danodus__xgsoc, emard__apple2fpga, emard__minimig_ecs, emard__nes_ecp5, emard__next186, emard__papilio-arcade, emard__ulx3s-bin, emard__ulx3s-misc, emard__usb_host, emard__vhdl_phoenix, greatscottgadgets__luna, hdl4fpga__hdl4fpga, ironsteel__nes_ecp5, jamchamb__cojiro, joaln27__koti, lawrie__spinalulx3s, lawrie__ulx3s_examples, linuxjedi__minimig_ecs, machdyne__nes_ecp5, machdyne__zeitlos, markus-zzz__myc64, seth16225__riscv-core-portfolio, ulx3s__apple2fpga, voltcyclone__hurra-fpga, voltcyclone__hurricanefpga
• vga: gojimmypi__z80386-ulx3s-doom
• video-composite: emard__vhdl_c64_c1541_sd, f32c__f32c, hoglet67__ice40atom, lawrie__ulx3s_atari_2600, lawrie__ulx3s_ay_3_8500, lawrie__ulx3s_bbc_micro, lawrie__ulx3s_zx_spectrum, nh428__ulx3s-tft-display-sobel-object-detection, rj45__vdp, robinsonb5__eightthirtytwodemos, schlae__graphics-gremlin, speccery__icy99, stuij__odyssey, thorkn__vga_clock_1, thorkn__vga_pong
• video-dvi: acairncross__clash-ulx3s-examples, adrmcintyre__vixen, aravindrajeshkanna__vernier-rv32, bqqbarbhg__blipv1, brunolevy__learn-fpga, cheyao__icepi-zero, cheyao__nes_ecp5, cheyao__oberon, cheyao__sega-sms, chriscamacho__yazsof, ckdur__riscvconsole, dan-rodrigues__icestation-32, danodus__ecp5_hdmi_audio_video, danodus__msx_fpga, danodus__onramp-fpga, danodus__ulx3s_sms, danodus__xgsoc, daveshah1__prjtrellis-dvi, detegr__ulx3s-projects, doctorwkt__ulx3s-blinky, doctorwkt__verilog_tic-tac-toe, egorxe__openglory, emard__apple-one, emard__apple2fpga, emard__fpga_snake_game, emard__galaksija, emard__jupiter_ace, emard__minimig_ecs, emard__nes_ecp5, emard__next186, emard__oberon, emard__papilio-arcade, emard__snes_mister_ulx3s, emard__ti99_2, emard__uk101onfpga, emard__ulx3s-emi, emard__ulx3s-misc, emard__ulx3s_c64, emard__ulx3s_galaksija, emard__ulx3s_vic_20, emard__verilog_tic-tac-toe, emard__vhdl_phoenix, evansm7__arcdvi, f32c__f32c, felipesanches__anotherworld_fpga, gatecat__snes_mister_ulx3s, gonsolo__borg, goran-mahovlic__gpdi_mirror, goran-mahovlic__odysseus_sprites, gornjas__dvi_test, guztech__ulx3s-nmigen-examples, hdl4fpga__hdl4fpga, icebreaker-fpga__icebreaker-verilog-examples, intergalaktik__ulx4m-ls, ironsteel__nes_ecp5, jlopezr__mini-gpu, joaln27__koti, kbeckmann__pergola_projects, kbeckmann__tt08-flame, l0r3m1psum__videogame_verilog, lawrie__apple-one, lawrie__hdmi_examples, lawrie__spinalulx3s, lawrie__ulx3s-nmigen-examples, lawrie__ulx3s_acorn_atom, lawrie__ulx3s_altair_8800, lawrie__ulx3s_amstrad_cpc, lawrie__ulx3s_colecovision, lawrie__ulx3s_examples, lawrie__ulx3s_gamegear, lawrie__ulx3s_mac128, lawrie__ulx3s_msx, lawrie__ulx3s_sg_1000, lawrie__ulx3s_sms, lawrie__ulx3s_trs_80, lawrie__ulx3s_zx81, lawrie__ulx3s_zx_spectrum, lawrie__ulx4m_amaranth_examples, lawrie__ulx4m_examples, linuxjedi__minimig_ecs, litex-hub__linux-on-litex-vexriscv, litex-hub__litex-boards, machdyne__nes_ecp5, machdyne__zeitlos, mb-sat__ulx3s-longwave-sdr, mebner86__icesugar-pro_sound2fft, mkvenkit__learn_fpga, msrraju07__iop, openconcepts-ar__accel2d, pnru__ti99, remyciterin__3driscv, remyciterin__dooom, riltonf__thermal_camera_ulx3s, rob-ng15__pawsv2, rxrbln__picorv32, seth16225__riscv-core-portfolio, smunaut__ice40-playground, smunaut__mch2022-ice40, spinalhdl__saxonsoc, splinedrive__my_hdmi_device, spritetm__hadbadge2019_fpgasoc, stereoninja__stereoninjafpga, sylefeb__silice, tallenintegsys__hdmi-orangecrab, techprototyper__trs80-rev-z, ultraembedded__ecpix-5, ulx3s__apple2fpga, ulx3s__fpga-odysseus, ulx3s__galaksija, ulx3s__hazard3, ulx3s__hazard3-doom, ulx3s__ulx3s_zx81, victor-fisyuk__voodoo-fpga-public, vladov3000__ulx3s, wren6991__smoldvi, wuxx__colorlight-fpga-projects, wuxx__icesugar-pro, yope__cpuv2
• video-input: advikbahadur__ulx3s-superresolution-cnn, angelojacobo__ulx3s_fpga_camera_streaming, angelojacobo__ulx3s_fpga_sobel_edge_detection_ov7670, anmho__ulx3_bsv, goran-mahovlic__gpdi_mirror, jderobot__fpga-robotics, kbeckmann__pergola_projects, nh428__ulx3s-tft-display-sobel-object-detection, riltonf__thermal_camera_ulx3s, stereoninja__stereoninjafpga, tucanae47__ulx3s-experiments
• video-vga: abhinavputhran__ttysky-raycast-test, alangarf__apple-one, asinghani__ulx3s-vga-example, daveshah1__pmods, daveshah1__up5k-demos, dibyx__flux, emard__fpga_snake_game, emeb__up5k_vga, glasgowembedded__glasgow, hoglet67__ice40beeb, htfab__asicle2, ibm2030__ibm2030, lawrie__blackicemxbook, lawrie__verilog_examples, mattvenn__fpga-sdft, mmicko__fpga101-workshop, mole99__tt05-one-sprite-pony, msinger__iceboy, nickmqb__fpga_craft, rxrbln__picorv32, schlae__graphics-gremlin, wifiboy__ok-ice40pro, wren6991__riscboy, wuxx__icesugar
• wishbone-bus: antoinevg__cynthion-tutorials, aravindrajeshkanna__vernier-rv32, assured__ct-key, greatscottgadgets__cynthion, greatscottgadgets__luna-soc, kulp__tenyr, rschlaikjer__fpga-3-softcores, tucanae47__litex_etpu, zipcpu__icozip, zipcpu__sdspi
• x86: bhouvana__aegis-x86-processor