VGA and video timing

VGA timing generators, framebuffers and text modes; 6845 CRTC, scandoublers.

Core Repository Language License FPGA Used by
Apple 1 VGA text-mode framebuffer core (vga/vram/font_rom) ★ lawrie__apple-one Verilog Apache-2.0 any 0
6845 CRTC reimplementation (Graphics Gremlin) schlae__graphics-gremlin Verilog CC-BY-SA-4.0 any 0
f32c VGA timing + hardware text-mode overlay f32c__f32c VHDL MIT-style permissive header any 0
MiST composite/RGB scandoubler (15kHz to VGA) hoglet67__ice40beeb Verilog GPL-3.0-or-later iCE40 1
vga_core / vga_timing portable VGA generator (Black Mesa Labs) icebreaker-fpga__icebreaker-verilog-examples Verilog CERN-OHL v1.2 iCE40 3
VgaSyncGen SpinalHDL VGA timing generator thorkn__vga_clock_1 SpinalHDL Apache-2.0 ECP5 2

Cores

Apple 1 VGA text-mode framebuffer core (vga/vram/font_rom) (best)

VGA timing generator driving a character-cell text framebuffer (vram.v) and 8x8 font ROM (font_rom.v); board-agnostic core wired to ULX3S GPDI via the sibling rtl/boards/ulx3s/vga2dvid.v.

   
Repository lawrie__apple-one: Apple 1 Verilog, ULX3S HDMI + PS/2 + UART
Files rtl/vga/vga.v, rtl/vga/vram.v, rtl/vga/font_rom.v, rtl/boards/ulx3s/vga2dvid.v
Top module vga
Language Verilog
License Apache-2.0 (LICENSE, root; core inherited unchanged from upstream alangarf/apple-one)
FPGA / primitives any: none (portable)
Tests iverilog tb, no self-checking pass/fail: tools/iverilog/vga_tb.v (run via run_vga_tb.sh, not make)

On ULX3S: Already targets ULX3S 25F (boards/ulx3s/yosys/, ulx3s_v20.lpf, prebuilt bitstream committed); feed vga.v output into rtl/boards/ulx3s/vga2dvid.v for GPDI.

6845 CRTC reimplementation (Graphics Gremlin)

Cycle-accurate Motorola 6845 CRTC reimplementation with an ISA-bus register interface, generating MDA/CGA-style character-cell video timing (hsync/vsync/cursor); board-agnostic, no vendor primitives.

   
Repository schlae__graphics-gremlin: Graphics Gremlin: ISA video card FPGA logic emulating IBM MDA
Files verilog/crtc6845.v
Top module crtc6845
Language Verilog
License CC-BY-SA-4.0 (LICENSE; file header confirms)
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: Replace the ISA-bus register shim with a simple MMIO/CPU interface; the timing-generator half is directly usable standalone.

f32c VGA timing + hardware text-mode overlay

VGA timing generator (vga.vhd) plus a full color text-mode overlay with selectable font ROM and optional SRAM/SDRAM bitmap plane (VGA_textmode.vhd), designed for the f32c SoC bus.

   
Repository f32c__f32c: f32c: retargetable RISC-V/MIPS 32-bit soft CPU + SoC library
Files rtl/soc/vgahdmi/vga.vhd, rtl/soc/vgahdmi/VGA_textmode.vhd
Top module VGA_textmode
Language VHDL
License MIT-style permissive header (vga.vhd: Copyright 2015 Davor Jadrijevic, LICENSE=BSD; VGA_textmode.vhd: Copyright 2015 Ken Jordan, MIT-text)
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: Not self-contained: expects f32c’s video_cache_d/videofifo signal conventions; proven on ULX3S 12F/25F/45F/85F via rtl/lattice/ulx3s/top/top_ulx3s_12f_xram_sdram_tv.vhd and siblings.

Full review: f32c__f32c.

MiST composite/RGB scandoubler (15kHz to VGA)

Converts 15.7kHz composite/RGB-timed video into standard 31.4kHz VGA timing; vendored from the MiST project into an iCE40 HX4K design but the file itself instantiates no vendor primitives.

   
Repository hoglet67__ice40beeb: Ice40Beeb: BBC Micro Model B retro-computer core
Files src/mist_scandoubler.v
Top module mist_scandoubler
Language Verilog
License GPL-3.0-or-later (file header, Copyright 2015 Till Harbaum, MiST project)
FPGA / primitives iCE40: none (portable)
Tests none found

On ULX3S: Portable structural Verilog; should synthesize unchanged for ECP5 with no primitive porting.

Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):

vga_core / vga_timing portable VGA generator (Black Mesa Labs)

Portable VGA timing generator (vga_timing.v) and test-pattern/framebuffer core (vga_core.v), originally written for Xilinx then ported to iCE40 without vendor primitives per the repo README.

   
Repository icebreaker-fpga__icebreaker-verilog-examples: iCEBreaker: collection of small Verilog examples
Files icebreaker/dvi-24bit/vga_core.v, icebreaker/dvi-24bit/vga_timing.v
Top module vga_core
Language Verilog
License CERN-OHL v1.2 (file header, Copyright 2017 Kevin M. Hubbard / Black Mesa Labs)
FPGA / primitives iCE40: none (portable)
Tests none found

On ULX3S: No porting needed for this pair of files; only the separate DVI serializer stage (not included) is board-specific.

Used by 3 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

VgaSyncGen SpinalHDL VGA timing generator

SpinalHDL VGA sync-timing generator and clock-cycle counter components, proven on ULX3S 85F (ulx3s/Makefile CHIP:=85k); reused unchanged in the author’s vga_pong project.

   
Repository thorkn__vga_clock_1: VGA digital clock display, hardware described in SpinalHDL/Scala and generated to Verilog for ULX3S 85k
Files spinalHDL/src/spinal/vgaclock/VgaSyncGen.scala, spinalHDL/src/spinal/vgaclock/ClockCounters.scala
Top module VgaSyncGen
Language SpinalHDL (Scala, elaborates to Verilog)
License Apache-2.0 (LICENSE)
FPGA / primitives ECP5: none (portable)
Tests none found

On ULX3S: Requires the SpinalHDL/Scala toolchain to elaborate to Verilog before synthesis; generator parameters cover standard VGA modes.

Used by 2 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

Other catalogued projects

Catalogued repos tagged video-vga (24), vga (1) are listed in the full catalogue.

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