OrangeCrab
Feather-format ECP5 board with DDR3 and native USB; DFU bootloader.
| Board | OrangeCrab (Feather format) |
| FPGA | LFE5U-25F or 85F, CSFBGA285 |
| Evidence | catalogue rows (orangecrab-fpga__orangecrab-examples, emeb__orangecrab_adc) |
| Clock | unknown |
| Catalogued repos | 13 |
The description is a short summary; FPGA facts come from the catalogue rows cited above.
Constraint files (LPF)
Most-copied distinct LPFs for this board in the cloned repos (from the LPF catalogue).
| LPF | Revision | Copies | Peripherals constrained |
|---|---|---|---|
orangecrab.lpf (hsa-ees__piconut) | unknown | 2 | ftdi-uart |
OrangeCrab.lpf (stnolting__neorv32-setups) | unknown | 1 | spi-flash |
ocadc.lpf (emeb__orangecrab_adc) | unknown | 1 | adc, button, led, usb |
orangecrab.lpf (hdl4fpga__hdl4fpga) | unknown | 1 | ddr3, gpio-header, led, usb |
orangecrab.lpf (zyedidia__riscinator) | unknown | 1 | ddr3, gpio-header, led, spi-flash, usb |
orangecrab_r02.lpf (fusesoc__blinky) | unknown | 1 | button |
pinout.lpf (sylefeb__silice) | unknown | 1 | led |
Reusable cores seen on this board
Cores whose source repo, or a repo that copies/instantiates them, targets this board.
| Core | Function | Source repo |
|---|---|---|
| Digital down-converter + AM/FM demod chain (post-ADC) | adc | emeb__orangecrab_adc |
| I2S receiver (orangecrab-usb) | audio-digital | mangelajo__orangecrab-usb |
| Fomu foboot DFU bootloader (LiteX/VexRiscv + ValentyUSB eptri) | bootloader-dfu | im-tomu__foboot |
| TinyFPGA USB Bootloader (USB-serial-to-SPI-flash bridge) | bootloader-dfu | tinyfpga__tinyfpga-bootloader |
| VexRiscv (SpinalHDL-generated Verilog) | cpu-riscv | rschlaikjer__fpga-3-softcores |
| secworks AES-128/256 core (via ct-key) | crypto | assured__ct-key |
| Lightweight AXI-4 DDR3 controller + ECP5 PHY | ddr-memory | ultraembedded__core_ddr3_controller |
| Lightweight DDR3 AXI4 memory controller (ECP5) | ddr-memory | ultraembedded__orangecrab |
| CIC decimator + FIR decimation filter | dsp | emeb__orangecrab_adc |
| glasgow I2C core (Amaranth) | i2c | glasgowembedded__glasgow |
| ecp5pll parametric PLL | pll-clock | emard__ulx3s-misc |
| katsuo.pcie ECP5 SERDES PHY + PCIe endpoint stack | serdes-links | zyp__katsuo-pcie |
| LAYR_AUDIO SID6581 sound chip core | sound-chips | thorkn__layr_audio |
| SPI master (Bus Pirate NextGen Ultra) | spi | dangerousprototypes__buspirateultrahdl |
| glasgow SPI controller (Amaranth) | spi | glasgowembedded__glasgow |
| hdl4fpga USB 1.1 device core | usb-device | hdl4fpga__hdl4fpga |
Projects targeting this board
- assured__ct-key: CT-key: LiteX/VexRiscv SoC with a Wishbone/CSR-mapped secworks AES core, real target for ULX3S
- emeb__orangecrab-litex-adc: OrangeCrab Litex ADC: LiteX/Migen SoC SDR gateware for the OrangeCrab ADC FeatherWing
- emeb__orangecrab_adc: OrangeCrab ADC FeatherWing: AD9203 10-bit/40MSPS ADC + audio board, gateware for SDR tuning/AM demodulation
- fdarling__orangecrab-usb-cdc-demo: OrangeCrab: minimal USB CDC
- google__cfu-playground: CFU-Playground: framework for building/benchmarking custom CFU
- greatscottgadgets__luna: LUNA: Amaranth USB 2.0/3.0 gateware framework
- hsa-ees__piconut: PicoNut: minimal, extensible RISC-V
- mangelajo__orangecrab-usb: OrangeCrab: two USB device examples
- openconcepts-ar__accel2d: accel2d: C-to-Verilog
- orangecrab-fpga__orangecrab-examples: OrangeCrab: example projects - RISC-V/VexRiscv firmware, plain Verilog
- tallenintegsys__hdmi-orangecrab: OrangeCrab: HDMI video+audio transmitter, porting Sameer Puri’s hdl-util/hdmi IP to Lattice ECP5 via yosys+synlig…
- ultraembedded__orangecrab: OrangeCrab: DDR3 128MB read/write memory test gateware (review)
- zyedidia__riscinator: Riscinator: 3-stage RV32I pipeline SoC in Chisel with SRAM/UART/GPIO/timer, synthesizable for OrangeCrab 25F or ULX3S…