DDR3 memory

DDR3 controllers and PHYs for ECP5 boards that have DDR3.

Core	Repository	Language	License	FPGA	Used by
Lightweight DDR3 AXI4 memory controller (ECP5) ★	ultraembedded__orangecrab	Verilog	Apache-2.0	ECP5	2
Lightweight AXI-4 DDR3 controller + ECP5 PHY	ultraembedded__core_ddr3_controller	Verilog	Apache-2.0	any	1
UberDDR3 controller + ECP5 PHY	remyciterin__3driscv	Verilog	GPL-3.0 (UberDDR3/LICENSE)	ECP5	2

Cores

Lightweight DDR3 AXI4 memory controller (ECP5) (best)

Complete AXI4 DDR3 controller (Ultra-Embedded.com) proven on OrangeCrab r0.2 (ECP5): JEDEC DFI sequencer + plain-IO PHY (no DQSBUFM/DELAYF hardware read-training). Not for stock ULX3S (SDR SDRAM only), only for ECP5 boards/add-ons with DDR3.

Repository	ultraembedded__orangecrab: OrangeCrab: DDR3 128MB read/write memory test gateware
Files	ddr_test/src_v/ddr3_axi.v, ddr_test/src_v/ddr3_axi_core.v, ddr_test/src_v/ddr3_axi_retime.v, ddr_test/src_v/ddr3_dfi_seq.v, ddr_test/src_v/ddr3_dfi_phy.v
Top module	ddr3_axi
Language	Verilog
License	Apache-2.0 (LICENSE)
FPGA / primitives	ECP5: ODDRX1F, IDDRX1F, BB
Tests	none found (no build script or testbench in this clone)

On ULX3S: Demonstrated only at a conservative 24 MHz DDR clock; re-tune DQ_IN_DELAY_INIT/TPHY_RDLAT for production speed. Needs a full LPF rewrite for any other board’s DDR3 pinout.

Full review: ultraembedded__orangecrab.

Used by 2 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

• maxhpc__ecpix-5 (instantiates libs/ddr3/ddr3_top.sv)
• ultraembedded__core_ddr3_controller (instantiates examples/arty_a7/top.v)

Lightweight AXI-4 DDR3 controller + ECP5 PHY

Compact 32-bit AXI-4 DDR3 memory controller run in DLL-off mode (<=125MHz), standardized DFI interface to a swappable PHY; ECP5 PHY plus Xilinx 7-series PHY both included. Smaller than vendor DDR3 MIGs (README: 9% vs 33% LUTs on the same design).

Repository	ultraembedded__core_ddr3_controller: Lightweight AXI-4 DDR3 memory controller
Files	src_v/ddr3_axi.v, src_v/ddr3_axi_pmem.v, src_v/ddr3_axi_retime.v, src_v/ddr3_core.v, src_v/ddr3_dfi_seq.v, src_v/phy/ecp5/ddr3_dfi_phy.v
Top module	ddr3_axi
Language	Verilog
License	Apache-2.0 (file headers, e.g. src_v/ddr3_axi.v)
FPGA / primitives	any: none (portable)
Tests	none found (tb/ddr3_core_xc7 needs proprietary Xilinx Vivado xsim/xelab, no open-source sim included)

On ULX3S: No SDRAM on ULX3S, so not directly usable there; targets ECP5 boards with DDR3 (ECPIX-5, tested at 100MHz sys clk / 50MHz DDR with a 90deg phase-shifted clock via ecp5pll). Up to 8 open rows, AXI-4 INCR bursts only (no WRAP).

Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):

• ultraembedded__orangecrab (instantiates ddr_test/src_v/ddr3_axi.v)

UberDDR3 controller + ECP5 PHY

DDR3 controller with a dedicated ecp5_phy/ddr3_phy_ecp5.v PHY (fabric-clocked BB/DELAYG, no PLL in-file); wired into the 3driscv RV32IMA SoC’s Wishbone DDR3 path via a Blarney (Core.hs) wrapper.

Repository	remyciterin__3driscv: 3DRiscV: RV32IMA CPU + custom RISC-V GPGPU SoC
Files	UberDDR3/rtl/ddr3_controller.v, UberDDR3/rtl/ddr3_phy.v, UberDDR3/rtl/ecp5_phy/ddr3_phy_ecp5.v
Top module	ddr3_controller
Language	Verilog
License	GPL-3.0 (UberDDR3/LICENSE)
FPGA / primitives	ECP5: BB, DELAYG
Tests	formal (SymbiYosys, UberDDR3/formal/*.sby) + icarus/vivado regression scripts (UberDDR3/testbench/)

On ULX3S: GPL-3.0 copyleft vs. the parent project’s MIT; check compatibility before reuse. Has SymbiYosys formal proofs and icarus/vivado regression tests, unlike most other DDR3 options here.

Used by 2 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

• aravindrajeshkanna__vernier-rv32 (instantiates rtl/soc/ddr3_ecp5_top.v)
• machdyne__zeitlos (instantiates rtl/mem/ddr3.v)

Other catalogued projects

Catalogued repos tagged ddr3 (5) are listed in the full catalogue.