HDMI / DVI output

TMDS encoders, serializers and DVI/HDMI transmitters (with or without audio), for the GPDI port.

Core Repository Language License FPGA Used by
vga2dvid + tmds_encoder DVI/TMDS core (Mike Field / EMARD) ★ emard__ulx3s-misc VHDL, Verilog MIT (vga2dvid.vhd, tmds_encoder.vhd headers,… ECP5 109
hdl4fpga TMDS encoder (video component library) hdl4fpga__hdl4fpga VHDL MIT (LICENSE; file header confirms same… any 0
HDMI TX with audio (danodus ecp5_hdmi_audio_video) danodus__ecp5_hdmi_audio_video Verilog MIT (LICENSE, Copyright 2026 Daniel Cliche / 2019… ECP5 0
my_hdmi_device TMDS encoder + video timing (chip_balls) splinedrive__my_hdmi_device Verilog ISC (LICENSE.md, Copyright 2021 Hirosh Dabui) ECP5 4
smoldvi small portable DVI core wren6991__smoldvi Verilog CC0-1.0 (LICENSE.md) any 4
sound2fft TMDS encoder + ECP5 DVI serializer mebner86__icesugar-pro_sound2fft Verilog MIT (LICENSE, root) ECP5 0

Cores

vga2dvid + tmds_encoder DVI/TMDS core (Mike Field / EMARD) (best)

Converts VGA-style RGB+HV+blank into 8b/10b TMDS-encoded DDR/SDR bitstreams for the GPDI port; fake_differential wraps ECP5 ODDRX1F for the 4 pseudo-differential pairs. Copied into dozens of repos in this collection.

   
Repository emard__ulx3s-misc: ULX3S misc/advanced examples: EMARD’s building-block library
Files examples/dvi/hdl/vga2dvid.vhd, examples/dvi/hdl/tmds_encoder.vhd, examples/dvi/hdl/fake_differential.v
Top module vga2dvid
Language VHDL, Verilog
License MIT (vga2dvid.vhd, tmds_encoder.vhd headers, Copyright 2012 Mike Field); fake_differential.v BSD-style (EMARD, no repo LICENSE file)
FPGA / primitives ECP5: ODDRX1F
Tests none found (top/top_vgatest.v is a synthesis smoke test, not self-checking)

On ULX3S: Drop-in for GPDI: instantiate vga2dvid with fake_differential(C_ddr=1) at 25 MHz pixel clock x5 shift clock.

Full review: emard__ulx3s-misc.

Used by 109 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

hdl4fpga TMDS encoder (video component library)

Reusable TMDS 8b/10b encoder entity from the hdl4fpga component library; encoder logic only, no serializer, meant to be paired with a board PHY (hdl4fpga ships ECP5 PHY files elsewhere in library/).

   
Repository hdl4fpga__hdl4fpga: hdl4fpga: portable VHDL library, ScopeIO oscilloscope, SDRAM graphics, eth/USB links
Files library/video/tmds_encoder.vhd
Top module tmds_encoder
Language VHDL
License MIT (LICENSE; file header confirms same permissive terms, Copyright 2015 Miguel Angel Sagreras)
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: Pair with an ECP5 ODDRX1F/ODDRX2F serializer to drive GPDI; VHDL-only, hdl4fpga’s own build scripts assume Diamond but the entity itself is toolchain-neutral.

Full review: hdl4fpga__hdl4fpga.

HDMI TX with audio (danodus ecp5_hdmi_audio_video)

Full HDMI TX stack with audio and info-frame packet insertion (clock regeneration, AVI/audio packets); ULX3S top-level wiring already provided in boards/ulx3s/.

   
Repository danodus__ecp5_hdmi_audio_video: ULX3S/IcePi Zero: HDMI audio+video transmitter core
Files rtl/hdmi.v, rtl/hdmi_tmds_channel.v, rtl/hdmi_serializer_ecp5.v, boards/ulx3s/ulx3s_top.v
Top module hdmi
Language Verilog
License MIT (LICENSE, Copyright 2026 Daniel Cliche / 2019 Sameer Puri)
FPGA / primitives ECP5: ODDRX1F
Tests none found

On ULX3S: boards/ulx3s/ulx3s_top.v + hdmi_pll*.v are ready-made for GPDI; pick the hdmi_pll variant matching your target resolution.

Full review: danodus__ecp5_hdmi_audio_video.

my_hdmi_device TMDS encoder + video timing (chip_balls)

hdmi_device.v does 8b/10b TMDS encoding from an incoming VGA-style RGB+sync stream; chip_balls.v wires it to ECP5 ODDRX1F for GPDI output. Builds against ulx3s_v20.lpf at –85k.

   
Repository splinedrive__my_hdmi_device: my_hdmi_device: from-spec TMDS/HDMI encoder, multi-board
Files tmds_encoder.v, hdmi_device.v, video_timings.v, chip_balls.v
Top module chip_balls
Language Verilog
License ISC (LICENSE.md, Copyright 2021 Hirosh Dabui)
FPGA / primitives ECP5: ODDRX1F
Tests none found

On ULX3S: Already has a ulx3s_v20.lpf and Makefile target (PROJ=chip_balls, –85k, CABGA381); pair with ecp5pll.sv (also in this repo) for the pixel/shift clocks.

Used by 4 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

smoldvi small portable DVI core

Minimal DVI TX (~20 LUTs/lane TMDS encoder); timing/encode/gearbox logic is vendor-neutral per the author, only the final serialiser targets a specific FPGA’s DDR output primitive.

   
Repository wren6991__smoldvi: iCEBreaker/iCEstick/iCESugar/TinyFPGA-BX: SmolDVI, a small direct DVI/TMDS output core
Files hdl/smoldvi/smoldvi.v, hdl/smoldvi/smoldvi_tmds_encode.v, hdl/smoldvi/smoldvi_timing.v, hdl/smoldvi/smoldvi_serialiser.v
Top module smoldvi
Language Verilog
License CC0-1.0 (LICENSE.md)
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: Port smoldvi_serialiser.v/smoldvi_clock_driver.v from iCE40 SB_IO to ECP5 ODDRX2F/ECLKSYNCB; the rest is drop-in.

Full review: wren6991__smoldvi.

Used by 4 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

sound2fft TMDS encoder + ECP5 DVI serializer

8b/10b TMDS encoder plus an ECP5 ODDRX1F-based DVI serializer, part of a larger FFT+PDM-mic+HDMI pipeline built for an ECP5 25F board (iCEsugar-Pro).

   
Repository mebner86__icesugar-pro_sound2fft: iCESugar-Pro sound2fft: real-time audio spectrum analyzer
Files rtl/tmds_encoder.v, rtl/tmds_serializer.v
Top module tmds_serializer
Language Verilog
License MIT (LICENSE, root)
FPGA / primitives ECP5: ODDRX1F
Tests waveform-only tb: projects/02_hdmi_test/hdmi_test_tb.v (no PASS/FAIL assertions found for tmds specifically)

On ULX3S: Board is ECP5 25F like the ULX3S 25F variant; only GPDI pin remapping should be needed.

Other catalogued projects

Catalogued repos tagged video-dvi (118) are listed in the full catalogue.

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