Sound chips and synths
Sound chip reimplementations (SID, SN76489, AY, YM) and synthesizers.
| Core | Repository | Language | License | FPGA | Used by |
|---|---|---|---|---|---|
| SN76489 PSG (sound chip) ★ | lawrie__ulx3s_sms | Verilog | none found | any | 10 |
| JT51 (YM2151 FM synth core) | dlobato__cps1-musicbox | Verilog | GPL-3.0 (gateware/rtl/jt51/LICENSE) | any | 0 |
| JT89 (AY-3-8910-like PSG) | danodus__ulx3s_68k | Verilog | GPL-3.0-or-later | ECP5 | 0 |
| LAYR_AUDIO SID6581 sound chip core | thorkn__layr_audio | Verilog | none found | ECP5 | 41 |
| SID (MOS 6581/8580) reimplementation, technology-independent | daglem__redip-sid | SystemVerilog | CERN-OHL-S-2.0 | iCE40 UP5K | 0 |
| SID reimplementation (icesid) | bit-hack__icesid | Verilog | CERN-OHL-S-2.0 | iCE40 UP5K | 0 |
Cores
SN76489 PSG (sound chip) (best)
Texas Instruments SN76489 programmable sound generator (3 tone channels + noise), the Sega Master System/BBC Micro PSG; parametric AUDIO_RES output width.
| Repository | lawrie__ulx3s_sms: Sega Master System / SG-1000: TV80, VDP, SN76489, SDRAM carts, ESP32 OSD |
| Files | src/sn76489.v |
| Top module | sn76489 |
| Language | Verilog |
| License | none found (no header in file; repo has no LICENSE/COPYING) |
| FPGA / primitives | any: none (portable) |
| Tests | none found |
On ULX3S: Proven on ULX3S 85F in lawrie__ulx3s_sms, cheyao__sega-sms and danodus__ulx3s_sms; feed audio_out into an I2S/DAC block from this same collection.
Full review: lawrie__ulx3s_sms.
Used by 10 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- cheyao__sega-sms (instantiates
src/sms.v) - danodus__ulx3s_68k (instantiates
src/test68.v) - danodus__ulx3s_sms (instantiates
src/sms.v) - hoglet67__ice40beeb (instantiates
src/bbc.v) - lawrie__ulx3s_68k (instantiates
src/test68.v) - lawrie__ulx3s_bbc_micro (instantiates
src/bbc.v) - lawrie__ulx3s_colecovision (instantiates
src/coleco.v) - lawrie__ulx3s_gamegear (instantiates
src/sms.v) - lawrie__ulx3s_ql (copies
src/sn76489.v) - lawrie__ulx3s_sg_1000 (instantiates
src/sg1000.v)
JT51 (YM2151 FM synth core)
Jotego’s cycle-accurate reimplementation of the Yamaha YM2151 FM synthesizer (used in many arcade boards incl. CPS1); ships its own ver/ verification testbenches.
| Repository | dlobato__cps1-musicbox: RISC-V (VexRiscv) + CPS1 arcade sound-chip (YM2151, MSM6295) emulation SoC built with LiteX/Migen, plays VGM… |
| Files | gateware/rtl/jt51/hdl |
| Top module | jt51 |
| Language | Verilog |
| License | GPL-3.0 (gateware/rtl/jt51/LICENSE) |
| FPGA / primitives | any: none (portable) |
| Tests | ver/ directory with per-module testbenches (jotego JT-series standard test harness; not individually re-run here) |
On ULX3S: Used as the CPS1 music core over a LiteX SoC targeting ULX3S (radiona_ulx3s.py); GPL-3.0 copyleft applies.
JT89 (AY-3-8910-like PSG)
Jotego’s AY-3-8910-compatible 3-channel PSG core (tone/noise/volume/mixer), used as the sound chip in the Atari ST-style ULX3S 68000 project.
| Repository | danodus__ulx3s_68k: 68000 CPU experiments |
| Files | src/jt89/jt89.v, src/jt89/jt89_tone.v, src/jt89/jt89_vol.v, src/jt89/jt89_noise.v, src/jt89/jt89_mixer.v |
| Top module | jt89 |
| Language | Verilog |
| License | GPL-3.0-or-later (in-file header, Jose Tejada / jotego) |
| FPGA / primitives | ECP5: none (portable) |
| Tests | none found in this pass |
On ULX3S: Proven on ULX3S 85F alongside src/fx68k.sv (68000 core) in the same repo.
LAYR_AUDIO SID6581 sound chip core
Single-file behavioral port of the Commodore 64 SID (6581) sound chip (sid_voice, sdadc, filter submodules under top module sid), forked from CornN64/C64-SID-on-a-FPGA and given a real ULX3S ECP5-85F Makefile/lpf.
| Repository | thorkn__layr_audio: LAYR_AUDIO: ULX3S ECP5-85F port of the C64 SID |
| Files | src/sid.v |
| Top module | sid |
| Language | Verilog |
| License | none found |
| FPGA / primitives | ECP5: none (portable) |
| Tests | none found |
On ULX3S: Pair with src/pll.v (25MHz->10MHz EHXPLLL wrapper, needs porting off ECP5) for the ULX3S build; drop-in on ULX3S per src/Makefile (CHIP=85k).
Used by 41 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- amin005__skywave_sdr (instantiates
fpga/ep1_pktsrc.v) - aravindrajeshkanna__vernier-rv32 (instantiates
rtl/debug/dm.v) - bhouvana__aegis-x86-processor (instantiates
RTL/bpu/dir_sc.sv) - bit-hack__icesid (instantiates
icesid/sid.v) - businessmanraduc__doggo-v6 (instantiates
rtl/soc/mem/sdram-adapter.sv) - cheyao__nes_ecp5 (instantiates
cart.sv) - chipdesign-bv__cdriscv-32s-20 (instantiates
rtl/boot/cdriscv_32s_20_qspi_boot.sv) - circuit-killer__fpga-usbserial (instantiates
usb_serial/usb_serial.vhd) - cube1us__ibm1410fpga (instantiates
VHDL/ALD_19_10_06_1_I_O_UNIT_INTERRUPT_COND_LATCHES_tb.vhdl) - daglem__redip-sid (instantiates
gateware/redip_sid.sv) - emard__nes_ecp5 (instantiates
cart.sv) - emard__ulx3s-misc (instantiates
examples/usb/usbcdc/usb_serial.vhd) - emard__ulx3s_c64 (instantiates
rtl/sid8580/sid8580.v) - emard__vhdl_c64_c1541_sd (instantiates
rtl_dar/sid6581.vhd) - emeb__orangecrab-litex-adc (instantiates
hw/deps/valentyusb/docs/source/conf.py) - … and 26 more (see
data/core_usage.json)
SID (MOS 6581/8580) reimplementation, technology-independent
Reference-quality Commodore 64 SID sound chip DSP core (waveform/envelope/filter/voice/DAC), technology-independent with no SB_* primitives in the listed files.
| Repository | daglem__redip-sid: reDIP SID: iCE40UP5K DIP-28 board running cycle-accurate MOS 6581/8580 SID chip emulation, with I2S/SGTL5000… |
| Files | gateware/sid_voice.sv, gateware/sid_waveform.sv, gateware/sid_envelope.sv, gateware/sid_filter.sv, gateware/sid_dac.sv, gateware/sid_api.sv |
| Top module | sid_api |
| Language | SystemVerilog |
| License | CERN-OHL-S-2.0 (LICENSE, root; matching header in gateware/*.sv, Dag Lem 2022-2023) |
| FPGA / primitives | iCE40 UP5K: none (portable) |
| Tests | none found in this pass |
On ULX3S: Core logic ports directly to ECP5; needs an I2S/sigma-delta output stage from this collection and the surrounding reDIP-SID board glue rewritten.
SID reimplementation (icesid)
Alternate technology-independent Verilog SID core (dac/env/voice/filter/mult/output split into separate modules), no SB_* primitives.
| Repository | bit-hack__icesid: reDIP-SID/iCESugar: open-source FPGA reimplementation of the MOS 6581/8580 SID chip audio synthesis, drop-in… |
| Files | icesid/sid.v, icesid/voice.v, icesid/env.v, icesid/filter.v, icesid/dac.v |
| Top module | sid |
| Language | Verilog |
| License | CERN-OHL-S-2.0 (LICENCE, root; matching SPDX header, Sylvain Munaut) |
| FPGA / primitives | iCE40 UP5K: none (portable) |
| Tests | none found in this pass |
On ULX3S: Same porting story as redip-sid: DSP core is portable, needs a ULX3S audio output stage.
Other catalogued projects
Catalogued repos tagged synth-audio (29) are listed in the full catalogue.