USB device

USB full-speed device stacks and CDC-ACM serial on the US2 port.

Core Repository Language License FPGA Used by
no2usb-derived ECP5 USB FS device core (had2019 bootloader) ★ emard__had2019-playground Verilog LGPL-3.0-or-later ECP5 6
circuit-killer USB FS serial device (VHDL, ULX3S-built) circuit-killer__fpga-usbserial VHDL GPL-2.0 (usb_serial/COPYING) ECP5 2
f32c USB CDC-ACM device + soft PHY f32c__f32c VHDL BSD-2-Clause any 2
hdl4fpga USB 1.1 device core hdl4fpga__hdl4fpga VHDL MIT (LICENSE, Miguel Angel Sagreras) any 13
ulixxe USB CDC-ACM device core ulixxe__usb_cdc Verilog MIT (LICENSE) any 2
ulx3s-misc USB CDC-ACM device (VHDL) emard__ulx3s-misc VHDL GPL-2.0-or-later any 0

Cores

no2usb-derived ECP5 USB FS device core (had2019 bootloader) (best)

Early ECP5-ported snapshot of Sylvain Munaut’s no2usb: full-speed USB device MAC/PHY (EP buffers, CRC, transaction engine) driving the US2 pins directly; the core shipped as the fielded ULX3S DFU bootloader’s USB device.

   
Repository emard__had2019-playground: HAD2019 badge playground
Files cores/usb/rtl
Top module usb
Language Verilog
License LGPL-3.0-or-later (LICENSE.lgpl3; header in cores/usb/rtl/usb.v)
FPGA / primitives ECP5: TRELLIS_IO, OFS1P3DX, IDDRX1F
Tests waveform-only (cores/usb/sim/*_tb.v via iverilog, never run to a pass/fail check)

On ULX3S: Runs at 48 MHz from a 25->48MHz EHXPLLL (sysmgr.v); wire to usb_fpga_bd_dp/dn + usb_fpga_pu_dp on US2.

Used by 6 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

circuit-killer USB FS serial device (VHDL, ULX3S-built)

USB CDC-ACM device core with its own soft PHY (usb11_phy_vhdl, no vendor primitives) plus an optional ULPI wrapper; the repo ships ULX3S v2.0/v3.1.7 LPFs and 12F/25F/45F/85F build dirs.

   
Repository circuit-killer__fpga-usbserial: USB1.1 full-speed device-side USB-to-serial core
Files usb_serial, usb11_phy_vhdl
Top module usb_serial
Language VHDL
License GPL-2.0 (usb_serial/COPYING)
FPGA / primitives ECP5: none (portable)
Tests none found

On ULX3S: Use usb11_phy_vhdl (direct US2 pins), not ulpi_wrapper (needs an external ULPI PHY chip).

Used by 2 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

f32c USB CDC-ACM device + soft PHY

USB 2.0 CDC-ACM device entity (usb_serial.vhd) over a UTMI-style soft PHY (usb11_phy, ported from Verilog), wired into f32c SoCs proven across ULX3S 12F-85F.

   
Repository f32c__f32c: f32c: retargetable RISC-V/MIPS 32-bit soft CPU + SoC library
Files rtl/soc/usb_serial, rtl/soc/usb11_phy
Top module usb_serial
Language VHDL
License BSD-2-Clause (repo fallback, no per-file header on usb_serial.vhd); usb11_phy is OpenCores-permissive (Copyright 2000-2002 Rudolf Usselmann)
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: Same core family as emard__ulx3s-misc/examples/usb/usbcdc; check docs/projects/f32c__f32c.md before reuse (license per-file uncertainty).

Full review: f32c__f32c.

Used by 2 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

hdl4fpga USB 1.1 device core

Portable USB 1.1 device core with no vendor primitives, switchable device/host role via a build constant; used on real ULX3S hardware by boards/ULX3S/apps/ser_debug.vhd on the US2 pins.

   
Repository hdl4fpga__hdl4fpga: hdl4fpga: portable VHDL library, ScopeIO oscilloscope, SDRAM graphics, eth/USB links
Files library/usb/usbdev.vhd, library/usb/usbphy.vhd
Top module usbdev
Language VHDL
License MIT (LICENSE, Miguel Angel Sagreras)
FPGA / primitives any: none (portable)
Tests waveform tb in boards/ULX3S/testbenches (12 tb files across boards, not all self-checking)

On ULX3S: Set the usb_device constant true in a ser_debug.vhd-style top; needs the matching usbphy.vhd PHY.

Full review: hdl4fpga__hdl4fpga.

Used by 13 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

ulixxe USB CDC-ACM device core

Self-contained full-speed USB CDC-ACM device (SIE, control/bulk endpoints, PHY rx/tx) with no BRAM/vendor primitives, shipped with pin files for 21 boards (Fomu, TinyFPGA-BX, iCEBreaker…).

   
Repository ulixxe__usb_cdc: Fomu / TinyFPGA-BX: USB_CDC, a from-scratch Full-Speed
Files usb_cdc
Top module usb_cdc
Language Verilog
License MIT (LICENSE)
FPGA / primitives any: none (portable)
Tests self-checking: examples/{TinyFPGA-BX,Fomu}/…/tb_demo.v uses assert_error macros (iverilog)

On ULX3S: No ULX3S pin file yet; add one for usb_fpga_bd_dp/dn + pull-up, following an existing board example.

Full review: ulixxe__usb_cdc.

Used by 2 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

ulx3s-misc USB CDC-ACM device (VHDL)

Same usb_serial.vhd device entity family as f32c, packaged as a standalone ULX3S example with a Windows .inf driver file; this copy documents itself as GPL, unlike the BSD-2 fallback claimed for the f32c copy.

   
Repository emard__ulx3s-misc: ULX3S misc/advanced examples: EMARD’s building-block library
Files examples/usb/usbcdc
Top module usb_serial
Language VHDL
License GPL-2.0-or-later (examples/usb/usbcdc/README.txt)
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: examples/usb/usbcdc/usbtest.vhd is the ready-to-build ULX3S top.

Full review: emard__ulx3s-misc.

Other catalogued projects

Catalogued repos tagged usb-device (38) are listed in the full catalogue.

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