ECPIX-5
ECP5-5G board with DDR3, RGMII Ethernet, HDMI (IT6613), a SATA port driven by LiteSATA over the SERDES, SD, ULPI USB and 8 PMODs; programmed with openFPGALoader -b ecpix5.
| Board | LambdaConcept ECPIX-5 |
| FPGA | LFE5UM5G-45F or LFE5UM5G-85F (ECP5-5G, with SERDES), BG554 |
| Evidence | LiteX / Amaranth board files, see the TinyFPGA EX / ECPIX-5 / Cynthion survey |
| Clock | 100 MHz (board files) |
| Catalogued repos | 12 |
The description is a short summary; FPGA facts come from the catalogue rows cited above.
Constraint files (LPF)
Most-copied distinct LPFs for this board in the cloned repos (from the LPF catalogue).
| LPF | Revision | Copies | Peripherals constrained |
|---|---|---|---|
ecpix5.lpf (aravindrajeshkanna__vernier-rv32) | unknown | 1 | ftdi-uart, led |
ecpix5.lpf (sylefeb__silice) | unknown | 1 | ftdi-uart, led |
ecpix5_ddr3.lpf (aravindrajeshkanna__vernier-rv32) | unknown | 1 | ddr3 |
ecpix5_ddr3_probe.lpf (aravindrajeshkanna__vernier-rv32) | unknown | 1 | ddr3 |
fpga.lpf (ultraembedded__core_ddr3_controller) | unknown | 1 | ddr3 |
pinmap.lpf (apfaudio__eurorack-pmod) | unknown | 1 | ftdi-uart, gpio-header, i2c |
Reusable cores seen on this board
Cores whose source repo, or a repo that copies/instantiates them, targets this board.
| Core | Function | Source repo |
|---|---|---|
| AK4619 audio codec driver + PMOD I2C master | audio-digital | apfaudio__eurorack-pmod |
| Cynthion USB Audio Class 2.0 example | audio-digital | greatscottgadgets__cynthion-uac |
| LUNA-SoC VexRiscv SoC framework (Moondancer’s CPU) | cpu-riscv | greatscottgadgets__luna-soc |
| VexRiscv (SpinalHDL-generated Verilog) | cpu-riscv | rschlaikjer__fpga-3-softcores |
| Lightweight AXI-4 DDR3 controller + ECP5 PHY | ddr-memory | ultraembedded__core_ddr3_controller |
| Lightweight DDR3 AXI4 memory controller (ECP5) | ddr-memory | ultraembedded__orangecrab |
| UberDDR3 controller + ECP5 PHY | ddr-memory | remyciterin__3driscv |
| glasgow I2C core (Amaranth) | i2c | glasgowembedded__glasgow |
| ORBTrace SWD/JTAG debug + parallel TRACE core (legacy plain-Verilog flow) | jtag-debug | orbcode__orbtrace |
| Vernier-RV32 RV32IMA Linux-capable Wishbone SoC | linux | aravindrajeshkanna__vernier-rv32 |
| ecp5pll parametric PLL | pll-clock | emard__ulx3s-misc |
| LiteICLink ECP5 SERDES (DCUA) wrapper | serdes-links | enjoy-digital__liteiclink |
| LiteSATA ECP5 SATA PHY + core | serdes-links | enjoy-digital__litesata |
| katsuo.pcie ECP5 SERDES PHY + PCIe endpoint stack | serdes-links | zyp__katsuo-pcie |
| LAYR_AUDIO SID6581 sound chip core | sound-chips | thorkn__layr_audio |
| SPI master (Bus Pirate NextGen Ultra) | spi | dangerousprototypes__buspirateultrahdl |
| glasgow SPI controller (Amaranth) | spi | glasgowembedded__glasgow |
| hdl4fpga USB 1.1 device core | usb-device | hdl4fpga__hdl4fpga |
Projects targeting this board
- antoinevg__cynthion-tutorials: cynthion-tutorials: Amaranth tutorials for Cynthion/ECPIX-5
- apfaudio__eurorack-pmod: Eurorack PMOD: AK4619 audio-codec PMOD gateware
- aravindrajeshkanna__vernier-rv32: Vernier-RV32: RV32IMA 5-stage pipelined SoC
- enjoy-digital__liteiclink: LiteICLink: Migen/LiteX inter-chip link cores - generic ECP5 SerDes
- enjoy-digital__litesata: LiteSATA: Migen/LiteX SATA host core
- greatscottgadgets__luna: LUNA: Amaranth USB 2.0/3.0 gateware framework
- litex-hub__litex-boards: LiteX board-support collection: Python platform + target definitions
- maxhpc__ecpix-5: ECPIX-5 gateware collection: LEDs, UART, DDR3 top
- openconcepts-ar__accel2d: accel2d: C-to-Verilog
- orbcode__orbtrace: ORBTrace: Cortex-M SWD/JTAG debug + parallel TRACE probe gateware
- ultraembedded__core_ddr3_controller: Lightweight AXI-4 DDR3 memory controller
- ultraembedded__ecpix-5: ECPiX-5: RISC-V TCM SoC with AXI4 interconnect and IT6613-based HDMI/DVI framebuffer output