PSRAM and HyperRAM
QSPI/QPI PSRAM and HyperBus controllers (add-on memories).
| Core | Repository | Language | License | FPGA | Used by |
|---|---|---|---|---|---|
| Hackaday badge QPI-PSRAM PHY + cache (ECP5-native) ★ | spritetm__hadbadge2019_fpgasoc | Verilog | BSD-3 (per-file headers, LICENSE.bsd) | ECP5 | 0 |
| hbc portable HyperBus/HyperRAM controller | gtjennings1__hyperbus | Verilog | MIT-style | any | 0 |
| hyper_xface HyperRAM DWORD interface | asinghani__pifive-cpu | Verilog | CERN-OHL-1.2 | any | 1 |
| no2fpga HyperRAM controller (no2hyperbus) | smunaut__ice40-playground | Verilog | CERN-OHL-P-2.0 | iCE40 | 1 |
Cores
Hackaday badge QPI-PSRAM PHY + cache (ECP5-native) (best)
Cleanly layered QPI-PSRAM stack for two interleaved Lyontek LY68L6400 8 MB QPI chips (16 MB total): only qspi_phy_2x_ecp5.v touches ECP5 DDR-IO primitives, qpimem_cache/arbiter/dma_rdr above it are portable logic. Ships on real 45F badge silicon.
| Repository | spritetm__hadbadge2019_fpgasoc: Hackaday Supercon 2019 badge: ECP5 SoC |
| Files | soc/qpi_cache/qspi_phy_2x_ecp5.v, soc/qpi_cache/qpimem_iface_2x2w.v, soc/qpi_cache/qpimem_cache.v, soc/qpi_cache/qpimem_arbiter.v, soc/qpi_cache/qpimem_dma_rdr.v |
| Top module | qpimem_cache |
| Language | Verilog |
| License | BSD-3 (per-file headers, LICENSE.bsd) |
| FPGA / primitives | ECP5: ODDRX1F, IDDRX1F, TRELLIS_IO, OFS1P3DX |
| Tests | self-checking iverilog testbenches: qpimem_cache_testbench.v, qpimem_iface_testbench.v, qpimem_interleave_testbench.v |
On ULX3S: ULX3S has no on-board QPI PSRAM; only useful pairing with a compatible add-on board. Runs at 48 MHz interleaved; new LPF and pin remap required either way.
Full review: spritetm__hadbadge2019_fpgasoc.
hbc portable HyperBus/HyperRAM controller
Self-contained HyperBus/HyperRAM controller in plain Verilog with no vendor primitives in the core FSM (hbc.v); written for iCE40 UP5K boards but architecturally the most portable HyperRAM core in the collection.
| Repository | gtjennings1__hyperbus: UPduino: HyperBus/HyperRAM controller plus a PicoRV32 RISC-V SoC demo for iCE40 UltraPlus |
| Files | standalone/hbc.v, standalone/hbc_io.v |
| Top module | hbc |
| Language | Verilog |
| License | MIT-style (embedded header, Gnarly Grey LLC 2017; no repo LICENSE/COPYING file) |
| FPGA / primitives | any: none (portable) |
| Tests | self-checking testbench: sim/hbc_tb.v ($display PASS/FAIL per byte) |
On ULX3S: No ULX3S/ECP5 target exists; needs a new top-level with ECP5 tristate DQ IO and timing closure at the board’s clock.
hyper_xface HyperRAM DWORD interface
DWORD-granularity HyperRAM interface (targets Cypress S27KL0641), optimized for RTL portability over bandwidth; DRAM clock is fabric-clock/4. Vendored into the pifive-cpu SoC but its instance is commented out there.
| Repository | asinghani__pifive-cpu: 3-stage RV32I(+M) |
| Files | soc/third_party/hyperram/hyper_xface.v, soc/third_party/hyperram/hyper_dword.v |
| Top module | hyper_xface |
| Language | Verilog |
| License | CERN-OHL-1.2 (claimed in-file header only, Kevin M. Hubbard 2018; not formalized at repo level) |
| FPGA / primitives | any: none (portable) |
| Tests | none found |
On ULX3S: Portable Verilog-2001, no vendor primitives; needs its own top-level pin mapping and has not been exercised end-to-end in the parent project (instantiation commented out). Byte-identical copy runs on ULX3S in markus-zzz__hyperram-test (syn/build-ulx3s.sh, HyperRAM add-on).
Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):
- markus-zzz__hyperram-test (instantiates
rtl/top.v)
no2fpga HyperRAM controller (no2hyperbus)
Wishbone-facing HyperRAM controller from Sylvain Munaut’s no2fpga library: hbus_memctrl.v and hbus_dline.v are primitive-free link-layer logic, only hbus_phy_ice40.v instantiates iCE40 SB_IO for the physical DQ/RWDS pins.
| Repository | smunaut__ice40-playground: iCEBreaker: collection of iCE40 UP5K IP cores |
| Files | cores/no2hyperbus/rtl/hbus_memctrl.v, cores/no2hyperbus/rtl/hbus_dline.v, cores/no2hyperbus/rtl/hbus_phy_ice40.v |
| Top module | hbus_memctrl |
| Language | Verilog |
| License | CERN-OHL-P-2.0 (cores/no2hyperbus/LICENSE) |
| FPGA / primitives | iCE40: SB_IO |
| Tests | sim/hbus_memctrl_tb.v against a bundled sim/s27kl0642.v behavioral model |
On ULX3S: Only hbus_phy_ice40.v needs an ECP5 rewrite (TRELLIS_IO/ODDRX1F in place of SB_IO); memctrl/dline logic is vendor-neutral as-is.
Full review: smunaut__ice40-playground.
Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):
- smunaut__ice40linux (instantiates
gateware/riscv_linux/rtl/top.v)
Other catalogued projects
Catalogued repos tagged psram (7), hyperram (4) are listed in the full catalogue.