SPI master / slave
Generic SPI master and slave cores.
| Core | Repository | Language | License | FPGA | Used by |
|---|---|---|---|---|---|
| APB SPI master (microSD) ★ | ulx3s__hazard3 | Verilog | Apache-2.0 | ECP5 | 0 |
| glasgow SPI controller (Amaranth) | glasgowembedded__glasgow | Python (Amaranth) | 0BSD OR Apache-2.0 | any | 5 |
| llsdspi low-level SPI engine | zipcpu__sdspi | Verilog | GPL-3.0 (per-file header, no top-level LICENSE) | any | 0 |
| OpenCores SPI slave (Santhosh G) | kelu124__lit3rick | Verilog | unknown (no SPDX header; file credits OpenCores… | any | 0 |
| SPI master (Bus Pirate NextGen Ultra) | dangerousprototypes__buspirateultrahdl | Verilog | GPL-3.0 (repo LICENSE) | any | 10 |
Cores
APB SPI master (microSD) (best)
Small software-driven APB SPI master (mode 0, MSB-first, no FIFO/DMA) built for the ULX3S micro-SD socket.
| Repository | ulx3s__hazard3: Hazard3 RV32IMACZb* CPU: ULX3S/ULX4M-LD fork with dedicated build docs, incl. |
| Files | example_soc/soc/apb_sd_spi.v |
| Top module | apb_sd_spi |
| Language | Verilog |
| License | Apache-2.0 (repo LICENSE) |
| FPGA / primitives | ECP5: none (portable) |
| Tests | none found |
On ULX3S: Actually wired into ulx3s__hazard3’s example_soc for ULX3S 85F; CLKDIV register sets SCLK from clk/2*(CLKDIV+1).
glasgow SPI controller (Amaranth)
Pure-Amaranth SPI controller core, part of Glasgow’s gateware library; elaborates to plain Verilog with no vendor primitives.
| Repository | glasgowembedded__glasgow: Glasgow Interface Explorer: multi-protocol USB debug/reverse-engineering tool - Amaranth-generated gateware… |
| Files | software/glasgow/gateware/spi.py |
| Top module | n/a |
| Language | Python (Amaranth) |
| License | 0BSD OR Apache-2.0 (repo LICENSE-*.txt) |
| FPGA / primitives | any: none (portable) |
| Tests | software/tests (cocotb-style, not spi.py-specific in this pass) |
On ULX3S: Needs an Amaranth build flow (glasgow CLI / YoWASP toolchain) to elaborate; ECP5 platform support already exists in the repo.
Used by 5 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- asinghani__pifive-cpu (copies
soc/rtl/periphs/spi.py) - cheyao__icepi-zero (copies
gateware/spi/rpi/spi.py) - greatscottgadgets__hackrf (copies
firmware/fpga/interface/spi.py) - greatscottgadgets__luna (copies
luna/gateware/interface/spi.py) - markus-zzz__zzz-rv (copies
rtl/spi.py)
llsdspi low-level SPI engine
Portable low-level SPI-mode engine (originally for SD cards) plus a byte/command-level sdspi wrapper; vendor-neutral, no synthesis flow bundled.
| Repository | zipcpu__sdspi: SD-Card cores |
| Files | rtl/spi/llsdspi.v, rtl/spi/sdspi.v |
| Top module | sdspi |
| Language | Verilog |
| License | GPL-3.0 (per-file header, no top-level LICENSE) |
| FPGA / primitives | any: none (portable) |
| Tests | bench/formal/*.sby SymbiYosys proofs; bench/cpp verilator C++ tb (self-checking) |
On ULX3S: Heaviest formal verification of any SPI core in the collection (~60 SymbiYosys proofs); GPL-3.0 copyleft.
Full review: zipcpu__sdspi.
OpenCores SPI slave (Santhosh G)
Classic OpenCores SPI-slave shift register (configurable bit order via mlb, tri-state output enable via ten), used in lit3rick to expose the acquired signal/FFT RAM over SPI to a Raspberry Pi host.
| Repository | kelu124__lit3rick: lit3rick: single-channel ultrasound pulse-echo board - UP5K ADC/pulser, on-chip DFT envelope extraction,… |
| Files | verilog/src/rtl/spi_slave.v |
| Top module | spi_slave |
| Language | Verilog |
| License | unknown (no SPDX header; file credits OpenCores project ‘spi_verilog_master_slave’, author Santhosh G santhg@opencores.org; opencores.org projects are commonly LGPL but that is not stated in this file) |
| FPGA / primitives | any: none (portable) |
| Tests | none found (exercised indirectly inside verilog/src/tb/tb_top.sv but no dedicated spi_slave testbench) |
On ULX3S: No vendor primitives; a generic byte-wide SPI slave, drop-in portable as-is.
Full review: kelu124__lit3rick.
SPI master (Bus Pirate NextGen Ultra)
Configurable SPI master written for the Bus Pirate NextGen Ultra debug probe; no vendor primitives in the file itself.
| Repository | dangerousprototypes__buspirateultrahdl: BusPirateUltraHDL: Bus Pirate Ultra FPGA gateware - SPI/UART/PWM/ADC engines + MCU parallel interface for the… |
| Files | hdl/spimaster.v |
| Top module | spimaster |
| Language | Verilog |
| License | GPL-3.0 (repo LICENSE) |
| FPGA / primitives | any: none (portable) |
| Tests | components/spi has a standalone testbench, not wired into hdl/Makefile |
On ULX3S: Repo builds for iCE40 HX8K, but spimaster.v has no SB_* instantiation, so it drops onto ECP5 unmodified.
Used by 10 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- assured__ct-key (instantiates
ctkey_package/src/ctkey/targets/ctkey_ulx3s.py) - egorxe__openglory (instantiates
hw/litex/radiona_ulx3s.py) - fusetim__rusty-soc (instantiates
hardware/lib/fusetim/spi/SpiMasterPeripheral.v) - litex-hub__linux-on-litex-vexriscv (instantiates
soc_linux.py) - litex-hub__litex-boards (instantiates
litex_boards/targets/radiona_ulx3s.py) - markus-zzz__zzz-rv (instantiates
rtl/soc.py) - mole99__tt05-one-sprite-pony (instantiates
tb/tb_cocotb.py) - pablogs9__rocketfpga (instantiates
Software/FPGA Sample Code/Codec/configurator.v) - spinalhdl__saxonsoc (instantiates
hardware/deprecated/blackice/BlackiceSocArduino.scala) - w531t4__fpga_led_display (instantiates
src/include/tb_spi_streamer.svh)
Other catalogued projects
Catalogued repos tagged spi (35) are listed in the full catalogue.