Retro CPUs

6502, Z80, 8080, 68000, 1802 and other classic CPUs.

Core Repository Language License FPGA Used by
cpu_6502 (Klaus Dormann-verified 6502 core) ★ chrismoos__m6502 SystemVerilog MIT (LICENSE) any 0
CDP1802-compatible core (SpinalHDL) lawrie__fpgacosmacelf Scala (SpinalHDL) GPL-3.0 any 0
danielh186 6502-compatible CPU core (FPGA-proven) danielh186__6502-tapeout Verilog none found ECP5 0
fx68k 68000-compatible core (nullobject vendored copy) nullobject__m68k-ulx3s Verilog GPL-3.0 (lib/fx68k/LICENSE) ECP5 5
grom toy 8-bit CPU + computer (FPGA 101 original) mmicko__fpga101-workshop Verilog MIT (repo LICENSE; files have no header) any 3
i8080-compatible core (Bashkiria-2M-derived) lawrie__ulx3s_examples Verilog modified BSD ECP5 4
TMS9900-family CPU core (public domain) pnru__ti99 Verilog public domain ECP5 1
TV80 Z80-compatible core (emard__ulx3s_galaksija copy) emard__ulx3s_galaksija Verilog MIT (OpenCores-style header, Copyright (c) 2004… any 24

Cores

cpu_6502 (Klaus Dormann-verified 6502 core) (best)

6502-compatible core, and the most reusable/tested CPU of any family in this collection: 9 cocotb test suites plus a Klaus Dormann full-opcode functional test, with ready-made ULX3S and Fomu targets/ dirs.

   
Repository chrismoos__m6502: m6502: compact microcoded cycle-accurate 6502 in SystemVerilog + MCU wrapper
Files rtl/cpu_6502.sv, rtl/cpu_6502_alu.sv, rtl/cpu_6502_ir_decoder.sv, rtl/cpu_6502_microcode.sv
Top module cpu_6502
Language SystemVerilog
License MIT (LICENSE)
FPGA / primitives any: none (portable)
Tests self-checking: make test (9 cocotb suites, python asserts) + make test-klaus (Klaus Dormann functional ROM)

On ULX3S: targets/ulx3s/ is a direct ULX3S build; no porting needed.

Full review: chrismoos__m6502.

CDP1802-compatible core (SpinalHDL)

‘Others’ family pick #2: a COSMAC ELF (CDP1802 CPU + CDP1861 video) reimplementation in SpinalHDL, elaborated to Verilog/VHDL at build time; built for ULX3S 12F default (12-85 range).

   
Repository lawrie__fpgacosmacelf: Cosmac ELF: CDP1802 + CDP1861 in SpinalHDL, UART loader
Files src/main/scala/Spinal1802/CDP1802.scala
Top module CDP1802
Language Scala (SpinalHDL)
License GPL-3.0
FPGA / primitives any: none (portable)
Tests ./verification dir present; self-checking status not confirmed

On ULX3S: Needs sbt+SpinalHDL to elaborate before synthesis, unlike the plain-HDL cores above.

danielh186 6502-compatible CPU core (FPGA-proven)

6502-compatible core implementing only the legal opcodes with deterministic (often reduced) per-opcode cycle counts; SO/SYNC/RDY/HALT/NMI/IRQ pins removed to save die area for its SG13G2 ASIC tapeout target – not a pin/cycle-exact 6502 replacement.

   
Repository danielh186__6502-tapeout: Open-source 6502-compatible CPU core
Files fpga-test/cpu.v, fpga-test/include.v
Top module CPU
Language Verilog
License none found
FPGA / primitives ECP5: none (portable)
Tests cocotb via Icarus, self-checking (cocotb-testbench/test_cpu.py: verify_attr/verify_memory compare DUT registers/memory against a maintained reference model after every instruction)

On ULX3S: fpga-test/{top.v,ulx3s_v20.lpf} build with nextpnr-ecp5 –85k –package CABGA381; README reports it running on a real Radiona ULX3S with clk/data/RW wired to GPIOs 0-9, verified with a logic analyzer. FPGA RAM is flip-flop based so only a 4096B window fits (shrink-memory.sh).

fx68k 68000-compatible core (nullobject vendored copy)

The 68000-family pick: fx68k is used throughout the collection (also in lawrie__ulx3s_examples/test68, danodus__ulx3s_68k, lawrie__ulx3s_mac128/ql); this copy is the one with an explicit vendored LICENSE file, unlike the widely-copied lawrie__ulx3s_examples/test68/fx68k.v which carries none.

   
Repository nullobject__m68k-ulx3s: Motorola 68000 SoC on ULX3S using the fx68k core, with OLED display, framebuffer/GPU and ACIA serial
Files lib/fx68k/fx68k.v, lib/fx68k/fx68kAlu.v
Top module fx68k
Language Verilog
License GPL-3.0 (lib/fx68k/LICENSE)
FPGA / primitives ECP5: none (portable)
Tests none found for fx68k itself (repo’s make sim only exercises hdl/gpu.v)

On ULX3S: Built for ULX3S 85F (Makefile DEVICE=85k) with a GPU/OLED SoC wrapped around it; the CPU files alone are reusable.

Used by 5 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

grom toy 8-bit CPU + computer (FPGA 101 original)

Teaching CPU by Miodrag Milanović: 8-bit data, 12-bit address, small ISA, with RAM and a ‘computer’ wrapper driving LEDs. Original of the copies in lawrie’s examples and FPGA Odysseus.

   
Repository mmicko__fpga101-workshop: FPGA 101 workshop
Files tutorials/10-CPU/grom_cpu.v, tutorials/10-CPU/alu.v, tutorials/10-CPU/grom_computer.v, tutorials/10-CPU/grom_top.v, tutorials/10-CPU/grom_computer_tb.v
Top module grom_top
Language Verilog
License MIT (repo LICENSE; files have no header)
FPGA / primitives any: none (portable)
Tests waveform-only (tutorials/10-CPU/grom_computer_tb.v, $dumpvars/$finish)

On ULX3S: Already ported: ulx3s__fpga-odysseus tutorials/06-CPU (identical grom_cpu.v) with ULX3S LPF.

Full review: mmicko__fpga101-workshop.

Used by 3 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

i8080-compatible core (Bashkiria-2M-derived)

8080-compatible core lifted from the Bashkiria-2M FPGA replica, wired here into an Altair 8800 emulator (computer/altair.v, computer/top_altair.v) built for ULX3S 25F/85F. Originates from mmicko__fpga101-workshop tutorials/11-Computer (identical i8080.v/altair.v).

   
Repository lawrie__ulx3s_examples: Lawrie Griffiths Verilog examples: HDMI, displays, PS/2, SDRAM, USB host, CPUs
Files computer/i8080.v
Top module i8080
Language Verilog
License modified BSD (Copyright (C) 2010 Dmitry Tselikov, LICENSE.TXT referenced in-file)
FPGA / primitives ECP5: none (portable)
Tests waveform-only tb present elsewhere in repo (test68/ps2send), none specific to i8080.v

On ULX3S: computer/top_altair.v is the ready ULX3S top; no other i8080 core was found in the collection.

Full review: lawrie__ulx3s_examples.

Used by 4 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

TMS9900-family CPU core (public domain)

‘Others’ family pick: a public-domain TMS99xxx CPU core (TI-99/4A lineage) built into a complete ULX3S 25F home-computer replica with HDMI, PS/2 and SD card.

   
Repository pnru__ti99: TI-99/2 in Verilog
Files ti99_2/tms99000.v
Top module tms99000
Language Verilog
License public domain (file header)
FPGA / primitives ECP5: none (portable)
Tests 1 tb file present

On ULX3S: speccery__icy99 is a second TMS9900-family repo (own core, license none found) if a different implementation is wanted.

Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):

TV80 Z80-compatible core (emard__ulx3s_galaksija copy)

The Z80-family pick: a Verilog port (TV80) of the well-known T80 VHDL Z80 core, no vendor primitives, and by far the most reused retro CPU in the collection (galaksija, jupiter_ace, msx_fpga, sms/sg-1000/gamegear, trs_80, yazsof…).

   
Repository emard__ulx3s_galaksija: emard/ulx3s_galaksija: Galaksija Z80 retro-computer core ported to ULX3S
Files tv80n.v, tv80_alu.v, tv80_reg.v, tv80_mcode.v, tv80_core.v
Top module tv80n
Language Verilog
License MIT (OpenCores-style header, Copyright (c) 2004 Guy Hutchison, based on Daniel Wallner’s VHDL T80)
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: This copy already carries a standalone ULX3S build (FPGA_SIZE 12/25/45/85).

Used by 24 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

Other catalogued projects

Catalogued repos tagged retro-computer (74), retro-console (22), retro-arcade (14) are listed in the full catalogue.

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Generated from the JSON in data/ by the scripts in .claude/skills. Facts cite the upstream file at the reviewed commit; verify before reuse.

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