RISC-V CPUs and SoCs

RISC-V cores and small SoCs.

Core Repository Language License FPGA Used by
PicoRV32 RISC-V core ★ yosyshq__picorv32 Verilog ISC (COPYING) any 35
f32c RISC-V/MIPS-compatible core f32c__f32c VHDL BSD-2-Clause any 0
FPGA 101 PicoSoC with LCD text console and MicroPython mmicko__fpga101-workshop Verilog, C MIT (repo LICENSE); z_picorv32.v ISC; MicroPython… iCE40 4
Hazard3 RV32IMAC core wren6991__hazard3 Verilog Apache-2.0 any 1
KianV RV32IMA+Sv32 core (Linux-capable) splinedrive__kianriscv Verilog Apache-2.0 any 0
LUNA-SoC VexRiscv SoC framework (Moondancer’s CPU) greatscottgadgets__luna-soc Python (Amaranth), Verilog… BSD-3-Clause any 1
NEORV32 RV32 core (VHDL) stnolting__neorv32 VHDL (+ generated Verilog wrapper in… BSD-3-Clause any 0
VexRiscv (SpinalHDL-generated Verilog) rschlaikjer__fpga-3-softcores Verilog (SpinalHDL-generated) MIT (upstream VexRiscv/SpinalHDL project; repo… any 19
Vernier-RV32 RV32IMA Linux-capable Wishbone SoC aravindrajeshkanna__vernier-rv32 Verilog Apache-2.0 WITH SHL-2.1 ECP5 3

Cores

PicoRV32 RISC-V core (best)

Single-file RV32I(MC) core, board- and vendor-agnostic, the most-reused RISC-V core in the collection (had2019/hazard3-doom bootloaders, hadbadge2019, wuxx__icesugar, racerxdl__colorlight-picorv32, nklabs, lawrie examples…).

   
Repository yosyshq__picorv32: PicoRV32: size-optimized RISC-V
Files picorv32.v
Top module picorv32
Language Verilog
License ISC (COPYING)
FPGA / primitives any: none (portable)
Tests self-checking: make test/test_wb/test_ez/test_axi (iverilog) and test_verilator, magic-MMIO pass/fail check

On ULX3S: No board dependency; wrap with picosoc.v-style memory-mapped peripherals and a BRAM/flash for firmware.

Full review: yosyshq__picorv32.

Used by 35 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

f32c RISC-V/MIPS-compatible core

Pipelined core that decodes either RISC-V (RV32IM) or a MIPS-compatible ISA (MI32) at build time (idecode_rv32.vhd/idecode_mi32.vhd), backing an entire SoC family (UART/SDRAM/DVI/USB/audio) proven across ULX3S 12F-85F for over a decade.

   
Repository f32c__f32c: f32c: retargetable RISC-V/MIPS 32-bit soft CPU + SoC library
Files rtl/cpu/f32c_core.vhd, rtl/cpu/idecode_rv32.vhd, rtl/cpu/idecode_mi32.vhd
Top module f32c_core
Language VHDL
License BSD-2-Clause (most files, per docs/projects/f32c__f32c.md)
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: Select ISA via the defs_f32c.vhd generic; comes with its own SoC glue, not a bare drop-in CPU.

Full review: f32c__f32c.

FPGA 101 PicoSoC with LCD text console and MicroPython

PicoRV32 PicoSoC for the UP5K badge: 128 KB SPRAM main memory, XIP flash, UART, memory-mapped text-mode video on the parallel LCD; firmware examples and a MicroPython port (board LCD/LED/switch modules).

   
Repository mmicko__fpga101-workshop: FPGA 101 workshop
Files tutorials/12-RiscV/top.v, tutorials/12-RiscV/picosoc.v, tutorials/12-RiscV/up_spram.v, tutorials/12-RiscV/video.v, tutorials/12-RiscV/simpleuart.v, tutorials/12-RiscV/02-Micropython/ports/picorv32
Top module top
Language Verilog, C
License MIT (repo LICENSE); z_picorv32.v ISC; MicroPython MIT
FPGA / primitives iCE40: SB_SPRAM256KA, SB_PLL40_CORE, SB_IO, SB_HFOSC
Tests none found

On ULX3S: Replace SB_SPRAM256KA with DP16KD/SDRAM, SB_PLL40_CORE with EHXPLLL, LCD video with a DVI path; the ULX3S follow-up is ulx3s__fpga-odysseus tutorials/08-RISCV.

Full review: mmicko__fpga101-workshop.

Used by 4 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

Hazard3 RV32IMAC core

Pipelined RV32IMAC core with CSR/PMP/debug support, board-agnostic; the ulx3s__hazard3 build validates it on real ULX3S 85F and ULX4M-LD hardware with documented Fmax/build steps.

   
Repository wren6991__hazard3: Hazard3: 3-stage RV32IMACZb* core with debug, example_soc synthesizable for ULX3S
Files hdl/hazard3_core.v, hdl/hazard3_csr.v, hdl/hazard3_pmp.v
Top module hazard3_core
Language Verilog
License Apache-2.0 (root LICENSE)
FPGA / primitives any: none (portable)
Tests self-checking: test/sim/test.py via cxxrtl, PASS/FAIL + CPU exit code

On ULX3S: 12F is too small (BRAM); use 85F. See ulx3s__hazard3/doc/ulx3s-ulx4m-build-and-validation.md.

Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):

KianV RV32IMA+Sv32 core (Linux-capable)

Standalone SoC-independent RV32IMA core with an Sv32 MMU, the CPU used by splinedrive’s Linux-on-ULX3S SoC; reusable on its own wherever an MMU-capable RV32 core is needed, not just with kianriscv’s own bus.

   
Repository splinedrive__kianriscv: KianV RV32IMA SV32 Linux SoCs
Files linux_socs/LinuxSoC_v2/engineering/kianv-rv32-linuxcore/kianv_sv32.v
Top module kianv_sv32
Language Verilog
License Apache-2.0 (SPDX header in file)
FPGA / primitives any: none (portable)
Tests 1 tb file present (not confirmed self-checking)

On ULX3S: Pair with the repo’s sdram/icache/dcache/clint/plic modules for a full SoC (85F default).

LUNA-SoC VexRiscv SoC framework (Moondancer’s CPU)

Wishbone/CSR SoC framework wrapping a pre-generated VexRiscv (or Minerva) RISC-V core, with an interrupt controller and Cynthion-specific board wiring (provider/cynthion.py); this is the CPU+fabric that the official Moondancer/Facedancer SoC in greatscottgadgets/cynthion is built on.

   
Repository greatscottgadgets__luna-soc: LUNA-SoC: Amaranth Wishbone/CSR SoC framework
Files luna_soc/gateware/cpu/vexriscv.py, luna_soc/gateware/cpu/verilog/vexriscv/vexriscv_cynthion.v, luna_soc/gateware/cpu/ic.py, luna_soc/gateware/provider/cynthion.py
Top module VexRiscv
Language Python (Amaranth), Verilog (SpinalHDL-generated)
License BSD-3-Clause (luna-soc LICENSE.txt) for the Amaranth wrapper; vexriscv_cynthion.v (SpinalHDL-generated) has no header in this clone
FPGA / primitives any: none (portable)
Tests none found

On ULX3S: Whole-system SoC framework, not a drop-in core: pair with core/{uart,timer,blockram,spiflash,usb2} peripherals and a platform (Cynthion provider bundled; others require writing a new provider). Regenerating the VexRiscv Verilog needs Scala/sbt (cpu/verilog/Makefile), outside the open FPGA flow.

Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):

NEORV32 RV32 core (VHDL)

Full-featured RV32 microcontroller core (CSR, on-chip debugger, rich peripheral set), vendor-agnostic; stnolting__neorv32-setups provides a generic open-toolchain osflow that builds it for ULX3S (BOARD=ULX3S).

   
Repository stnolting__neorv32: NEORV32 RISC-V microcontroller SoC
Files rtl/core
Top module neorv32_top
Language VHDL (+ generated Verilog wrapper in rtl/verilog)
License BSD-3-Clause
FPGA / primitives any: none (portable)
Tests self-checking: make -C rtl/verilog sim (ghdl->Verilog, checks for ‘Simulation successful!’ vs timeout)

On ULX3S: No ULX3S target ships inside this repo itself; use the neorv32-setups osflow or fedy0__neo’s neorv32_ULX3S_BoardTop_MinimalBoot.vhd top.

VexRiscv (SpinalHDL-generated Verilog)

Vendored single-file Verilog output of a VexRiscv RV32 configuration, wired to a Wishbone SoC in this repo; the same generate-a-.v-snapshot pattern also appears in hanseo03__ulx3s-vexriscv-soc and thorkn’s ULX3S VexRiscv examples.

   
Repository rschlaikjer__fpga-3-softcores: fpga-3-softcores: VexRiscv Wishbone SoC demo
Files vendor/vexriscv/VexRiscv.v
Top module VexRiscv
Language Verilog (SpinalHDL-generated)
License MIT (upstream VexRiscv/SpinalHDL project; repo LICENSE.md is MIT, no per-file header on the generated .v)
FPGA / primitives any: none (portable)
Tests waveform tb in ./test, ./sim (8 files, not confirmed self-checking)

On ULX3S: Regenerate with GenVexRiscv.scala for a different pipeline/extension config; the checked-in .v is a fixed snapshot.

Used by 19 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

Vernier-RV32 RV32IMA Linux-capable Wishbone SoC

5-stage RV32IMA + Zicsr pipeline with Sv32 MMU, CLINT/PLIC, boot ROM, UART, GPIO, SPI/SD and a Wishbone SoC fabric; boots mainline-style Linux to userspace on a real ULX3S LFE5U-85F (fpga/README.md logs SOC-TEST: PASS and a full Linux boot).

   
Repository aravindrajeshkanna__vernier-rv32: Vernier-RV32: RV32IMA 5-stage pipelined SoC
Files rtl/top.v, rtl/soc/soc_top.v, fpga/ulx3s_top.v, fpga/constraints/ulx3s.lpf
Top module ulx3s_top
Language Verilog
License Apache-2.0 WITH SHL-2.1 (Solderpad Hardware License 2.1; SPDX header in LICENSE)
FPGA / primitives ECP5: EHXPLLL, ODDRX1F, ODDRX2F, DELAYG, DQSBUFM
Tests sim/ and tests/ dirs, 65 tb/test files, verilator+iverilog (scan_tests.sh); riscv-tests + Spike co-simulation per README badges

On ULX3S: Real, hardware-verified pin-out (fpga/constraints/ulx3s.lpf, every pin placed); Fmax margin is thin (23-26 MHz vs the board’s 25 MHz, 4/6 seeds close) - see fpga/README.md before reusing at full clock. Also has an ECPIX5 DDR3 variant (rtl/soc/ddr3_*_ecp5.v) and an unrun Xilinx/Vivado path.

Used by 3 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

Other catalogued projects

Catalogued repos tagged soc-cpu (173) are listed in the full catalogue.

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