Buses and interconnect
Wishbone/AXI interconnects, arbiters, bridges.
| Core | Repository | Language | License | FPGA | Used by |
|---|---|---|---|---|---|
| wb_intercon Wishbone mux/arbiter (olofk) ★ | kulp__tenyr | Verilog | ISC (file headers, Copyright Olof Kindgren) | any | 4 |
| AHB-Lite crossbar/arbiter/APB bridge | ulx3s__hazard3 | Verilog | WTFPL (file headers, Copyright 2018 Luke Wren) | ECP5 | 3 |
| wb_intercon (olofk), iCE40 copy | rschlaikjer__fpga-3-softcores | Verilog | ISC (vendor/wb_intercon/LICENSE) | iCE40 | 0 |
Cores
wb_intercon Wishbone mux/arbiter (olofk) (best)
Standard olofk/wb_intercon Wishbone crossbar mux and round-robin arbiter, wired into tenyr’s own CPU SoC.
| Repository | kulp__tenyr: tenyr: 32-bit orthogonal computer architecture + full software toolchain, with a hw/yosys ULX3S 12F build |
| Files | 3rdparty/wb_intercon/rtl/verilog/wb_mux.v, 3rdparty/wb_intercon/rtl/verilog/wb_arbiter.v |
| Top module | wb_mux |
| Language | Verilog |
| License | ISC (file headers, Copyright Olof Kindgren) |
| FPGA / primitives | any: none (portable) |
| Tests | 3rdparty/wb_intercon/bench/{wb_mux_tb.v,wb_arbiter_tb.v} (iverilog) |
On ULX3S: Fetched as a git submodule; actually used in hw/verilog/top.v for a ULX3S 12F build (yosys+nextpnr-ecp5+ecppack).
Used by 4 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- daveshah1__ulx3s (instantiates
rtl/verilog/wb_intercon.v) - machdyne__zeitlos (instantiates
rtl/sysctl.v) - osmocom__osmo-e1-hardware (instantiates
gateware/common/rtl/soc_iobuf.v) - rschlaikjer__fpga-3-softcores (instantiates
rtl/gen/wb_intercon.v)
AHB-Lite crossbar/arbiter/APB bridge
AHB-Lite crossbar, arbiter, splitter and an AHB-Lite-to-APB bridge, connecting the Hazard3 CPU to its peripherals.
| Repository | ulx3s__hazard3: Hazard3 RV32IMACZb* CPU: ULX3S/ULX4M-LD fork with dedicated build docs, incl. |
| Files | example_soc/libfpga/busfabric/ahbl_crossbar.v, example_soc/libfpga/busfabric/ahbl_arbiter.v, example_soc/libfpga/busfabric/ahbl_to_apb.v, example_soc/libfpga/busfabric/ahbl_splitter.v |
| Top module | ahbl_crossbar |
| Language | Verilog |
| License | WTFPL (file headers, Copyright 2018 Luke Wren) |
| FPGA / primitives | ECP5: none (portable) |
| Tests | no unit test of the crossbar/arbiter themselves; indirectly exercised by test/sim SoC-level cxxrtl tests (coremark, riscv-tests) |
On ULX3S: Actually instantiated in example_soc/soc/example_soc.v for the ULX3S 85F / ULX4M-LD build; fetched via the Hazard3-libfpga submodule.
Used by 3 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- wren6991__hazard3 (instantiates
example_soc/soc/example_soc.v) - wren6991__hazard3-swd-soc (instantiates
hdl/soc/soc.v) - wren6991__riscboy (instantiates
hdl/libfpga/busfabric/ahbl_crossbar.v)
wb_intercon (olofk), iCE40 copy
Same olofk/wb_intercon library as kulp__tenyr, vendored directly (not a submodule) alongside a VexRiscv SoC.
| Repository | rschlaikjer__fpga-3-softcores: fpga-3-softcores: VexRiscv Wishbone SoC demo |
| Files | vendor/wb_intercon/rtl/verilog/wb_mux.v, vendor/wb_intercon/rtl/verilog/wb_arbiter.v |
| Top module | wb_mux |
| Language | Verilog |
| License | ISC (vendor/wb_intercon/LICENSE) |
| FPGA / primitives | iCE40: none (portable) |
| Tests | vendor/wb_intercon/bench/{wb_mux_tb.v,wb_arbiter_tb.v} |
On ULX3S: Files contain no SB_* primitives; only the board’s PCF/PLL needs porting, the bus logic is vendor-neutral.
Other catalogued projects
Catalogued repos tagged bus-fabric (13), wishbone-bus (10) are listed in the full catalogue.