ADC
ADC interfaces (onboard MAX11125 and external ADCs).
| Core | Repository | Language | License | FPGA | Used by |
|---|---|---|---|---|---|
| MAX1112x ADC reader (ulx3s-misc) ★ | emard__ulx3s-misc | VHDL | BSD (-- AUTHOR=EMARD / -- LICENSE=BSD header) | any | 1 |
| AD9629 12-bit parallel ADC capture (adc_receiver) | kelu124__lit3rick | Verilog | GPL-3.0-or-later | any | 0 |
| Digital down-converter + AM/FM demod chain (post-ADC) | emeb__orangecrab_adc | Verilog | none found | any | 3 |
| MAX1112x ADC reader (ulx3s-emi copy) | emard__ulx3s-emi | VHDL | BSD (-- AUTHOR=EMARD / -- LICENSE=BSD header) | any | 1 |
| SPI ADC core (Bus Pirate Ultra HDL) | dangerousprototypes__buspirateultrahdl | Verilog | GPL-3.0 (repo LICENSE) | iCE40 HX8K | 0 |
| InductIQ lock-in mixer + BRAM-LUT NCO | makisness__inductiq | SystemVerilog, Verilog | MIT (LICENSE) | any | 0 |
Cores
MAX1112x ADC reader (ulx3s-misc) (best)
Init+read core for the onboard MAX1112x (MAX11125-family) SPI ADC used on the ULX3S; shift and array register variants.
| Repository | emard__ulx3s-misc: ULX3S misc/advanced examples: EMARD’s building-block library |
| Files | examples/adc/max1112x/hdl/max1112x_reader_shift.vhd, examples/adc/max1112x/hdl/max1112x_reader_array.vhd, examples/adc/max1112x/hdl/max1112x_init_pack.vhd |
| Top module | max1112x_reader_shift |
| Language | VHDL |
| License | BSD (-- AUTHOR=EMARD / -- LICENSE=BSD header) |
| FPGA / primitives | any: none (portable) |
| Tests | none found (repo-wide: only examples/audio/testbench/sinewave.c is a non-HDL C reference model) |
On ULX3S: Drop-in for the ULX3S onboard MAX11125 ADC pins; verified in docs/projects/emard__ulx3s-misc.md.
Full review: emard__ulx3s-misc.
Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):
AD9629 12-bit parallel ADC capture (adc_receiver)
Captures a fixed 8192-sample burst from a 12-bit parallel ADC (AD9629BCPZ-65, up to 65 Msps) on a start pulse, subtracts the ADC’s 2048 mid-scale DC offset, and emits sample_num/DOUT_vld plus a finish flag for a downstream RAM writer.
| Repository | kelu124__lit3rick: lit3rick: single-channel ultrasound pulse-echo board - UP5K ADC/pulser, on-chip DFT envelope extraction,… |
| Files | verilog/src/rtl/adc_receiver.v |
| Top module | adc_receiver |
| Language | Verilog |
| License | GPL-3.0-or-later (repo Readme.md ## License; no per-file SPDX header) |
| FPGA / primitives | any: none (portable) |
| Tests | exercised (not unit-tested standalone) by verilog/src/tb/tb_top.sv test_adc task through a behavioural AD9629 model, verilog/src/tb/ad9629.sv |
On ULX3S: No vendor primitives; a plain free-running counter and register pipeline, easily retargeted to any parallel ADC by changing the ADC_D width and the 2048 offset constant.
Full review: kelu124__lit3rick.
Digital down-converter + AM/FM demod chain (post-ADC)
Digital down-converter, tuner NCO, AM/FM demodulators plus CIC decimator and FIR filter, fed from an external fast ADC on OrangeCrab 25F; no vendor primitives seen.
| Repository | emeb__orangecrab_adc: OrangeCrab ADC FeatherWing: AD9203 10-bit/40MSPS ADC + audio board, gateware for SDR tuning/AM demodulation |
| Files | gateware/verilog/src/ddc_14.v, gateware/verilog/src/demods.v, gateware/verilog/src/tuner_2.v, gateware/verilog/src/cic_dec_4.v, gateware/verilog/src/fir8dec_par.v |
| Top module | ddc_14 |
| Language | Verilog |
| License | none found (no LICENSE file in repo) |
| FPGA / primitives | any: none (portable) |
| Tests | none found |
On ULX3S: Needs an external high-speed ADC on ULX3S (no onboard equivalent); the DSP chain itself (CIC/FIR/demod) is portable.
Used by 3 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- emeb__iceradio (copies
FPGA/rxadc_2/verilog/src/tuner_2.v) - emeb__orangecrab-litex-adc (copies
hw/vsrc/cic_dec_4.v) - emeb__rpi_rxadc (instantiates
gateware/icehat_rxadc/icestorm/icehat_rxadc.v)
MAX1112x ADC reader (ulx3s-emi copy)
Same EMARD MAX1112x ADC init/read core vendored into the ulx3s-emi (12F) example board design.
| Repository | emard__ulx3s-emi: emard/ulx3s-emi: ULX3S electromagnetic-interference |
| Files | hdl/max1112x_reader_array.vhd, hdl/max1112x_init_pack.vhd |
| Top module | max1112x_reader_array |
| Language | VHDL |
| License | BSD (-- AUTHOR=EMARD / -- LICENSE=BSD header) |
| FPGA / primitives | any: none (portable) |
| Tests | none found |
On ULX3S: Same core as ulx3s-misc; use if you want the ulx3s-emi top-level wiring as a starting point.
Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):
SPI ADC core (Bus Pirate Ultra HDL)
Standalone 14-bit SPI ADC read/calibration core for the Bus Pirate Ultra’s onboard ADC channel.
| Repository | dangerousprototypes__buspirateultrahdl: BusPirateUltraHDL: Bus Pirate Ultra FPGA gateware - SPI/UART/PWM/ADC engines + MCU parallel interface for the… |
| Files | hdl/adc.v |
| Top module | adc |
| Language | Verilog |
| License | GPL-3.0 (repo LICENSE) |
| FPGA / primitives | iCE40 HX8K: none (portable) |
| Tests | none found |
On ULX3S: adc.v itself is plain Verilog (no SB_* seen); the board’s pll.v/buspirate.v use iCE40 SB_PLL40_CORE/SB_IO and would need ECP5 equivalents if reused wholesale.
InductIQ lock-in mixer + BRAM-LUT NCO
Digital lock-in amplifier: multiplies a 12-bit ADC sample by 16-bit sine/cosine references from a BRAM quarter-wave-LUT NCO (32-bit phase accumulator), then accumulates I/Q over up to 2^15 samples in 48-bit accumulators for synchronous detection. No vendor primitives.
| Repository | makisness__inductiq: InductIQ: FPGA lock-in amplifier + impedance sweep instrument for eddy-current coil sensing |
| Files | hdl/rtl/lia/lia_core.sv, hdl/rtl/dds/configurable_nco.v, hdl/rtl/dds/quarter_sine_lut_Q1_15.mem |
| Top module | lia_core |
| Language | SystemVerilog, Verilog |
| License | MIT (LICENSE) |
| FPGA / primitives | any: none (portable) |
| Tests | hdl/tb/top_tb.sv + hdl/tb/adc_model.sv present in the clone; no Makefile/runner found so self-checking could not be confirmed |
On ULX3S: Proven on ULX3S 85F via apio (board=ulx3s-85f); drop-in with any signed ADC sample stream and matching sine/cosine reference width. Fills a gap noted in reusable-cores.md: no lock-in amplifier core existed in the collection before this.
Other catalogued projects
Catalogued repos tagged adc (37) are listed in the full catalogue.