PLLs and clocking

ECP5 EHXPLLL wrappers and PLL parameter calculators.

Core	Repository	Language	License	FPGA	Used by
ecp5pll parametric PLL ★	emard__ulx3s-misc	SystemVerilog, VHDL	BSD (// (c)EMARD / License=BSD, file header)	ECP5	92
blip nMigen ECP5 PLL wrapper	bqqbarbhg__blipv1	Python (nMigen)	none found	ECP5	0
Glasgow ECP5 PLL parameter solver (Amaranth)	glasgowembedded__glasgow	Python (Amaranth)	0BSD OR Apache-2.0	ECP5	0
hdl4fpga ecp5_videodcm / ecp5_sdramdcm clock generators	hdl4fpga__hdl4fpga	VHDL	MIT (LICENSE)	ECP5	0

Cores

ecp5pll parametric PLL (best)

Computes EHXPLLL divider/phase parameters from requested in/out frequencies at elaboration time; up to 4 outputs with independent phase, actual achieved frequency reported in the trellis/Diamond build log. Copied into dozens of other repos in this collection.

Repository	emard__ulx3s-misc: ULX3S misc/advanced examples: EMARD’s building-block library
Files	examples/ecp5pll/hdl/sv/ecp5pll.sv, examples/ecp5pll/hdl/vhd/ecp5pll.vhd
Top module	ecp5pll
Language	SystemVerilog, VHDL
License	BSD (// (c)EMARD / License=BSD, file header)
FPGA / primitives	ECP5: EHXPLLL
Tests	none found

On ULX3S: Drop-in on ULX3S: in_hz=25000000 (board oscillator); no other configuration needed.

Full review: emard__ulx3s-misc.

Used by 92 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

• advikbahadur__ulx3s-superresolution-cnn (instantiates src/top_module.v)
• assured__ct-key (instantiates aes_test/soc.py)
• bjonnh__ulx3s-synth (instantiates i2s.v)
• blazra__tdr (instantiates gateware/versa_ecp5-litex/tdr/clock.py)
• bqqbarbhg__blipv1 (instantiates blip/rtl/ecp5/io.py)
• cheyao__icepi-zero (instantiates gateware/sdram/memtest/memtest.sv)
• cheyao__nes_ecp5 (instantiates top.v)
• cheyao__oberon (instantiates hdl/pnru_mix/Ulx3s_Top.v)
• cheyao__sega-sms (instantiates src/sms.v)
• danodus__ulx3s_68k (instantiates src/test68.v)
• danodus__ulx3s_sms (instantiates src/sms.v)
• danodus__xgsoc (instantiates rtl/icepi-zero/icepi_zero_top.sv)
• datanoisetv__colorlight-i9-aes67 (instantiates litex/soc.py)
• dicethrow__amaram (instantiates amaram/sdram_n_fifo_interface/interface_fifo_build/top.debug.v)
• dicethrow__amtest (instantiates amtest/boards/ulx3s/common/ECP5PLL.py)
• … and 77 more (see data/core_usage.json)

blip nMigen ECP5 PLL wrapper

nMigen PLL wrapper (PllClock) with an ECP5-specific backend, built directly against nmigen_boards’ ULX3S_85F_Platform for the blip engine’s ULX3S target.

Repository	bqqbarbhg__blipv1: nMigen/Amaranth DVI
Files	blip/rtl/pll.py, blip/rtl/ecp5/pll.py
Top module	n/a
Language	Python (nMigen)
License	none found
FPGA / primitives	ECP5: EHXPLLL
Tests	none found

On ULX3S: Requires the nMigen/Amaranth flow and nmigen-boards’ ULX3S platform definition rather than plain Verilog/VHDL.

Glasgow ECP5 PLL parameter solver (Amaranth)

Amaranth-based EHXPLLL parameter solver derived from Project Trellis’ PLL calculations, instantiating EHXPLLL plus an FD1S3AX loss-of-lock flop and reset-synchronizer flops; used by Glasgow revD which is itself an ECP5 25F board.

Repository	glasgowembedded__glasgow: Glasgow Interface Explorer: multi-protocol USB debug/reverse-engineering tool - Amaranth-generated gateware…
Files	software/glasgow/gateware/pll/ecp5.py
Top module	n/a
Language	Python (Amaranth)
License	0BSD OR Apache-2.0 (LICENSE-0BSD.txt, LICENSE-Apache-2.0.txt)
FPGA / primitives	ECP5: EHXPLLL, FD1S3AX
Tests	software/glasgow/gateware/pll/bench.py (benchmark/consistency script, not a synthesis test)

On ULX3S: Needs an Amaranth flow (not plain yosys/nextpnr from Verilog/VHDL sources); complements rather than replaces emard-ecp5pll for HDL-only designs.

hdl4fpga ecp5_videodcm / ecp5_sdramdcm clock generators

Two purpose-built EHXPLLL wrappers (video pixel-clock and SDRAM clock) that all three ULX3S hdl4fpga apps instantiate from a single 25 MHz clk_25mhz input, confirmed against the real ulx3s_v20.lpf pin name.

Repository	hdl4fpga__hdl4fpga: hdl4fpga: portable VHDL library, ScopeIO oscilloscope, SDRAM graphics, eth/USB links
Files	library/apps/ecp5_videodcm.vhd, library/apps/ecp5_sdramdcm.vhd
Top module	ecp5_videodcm
Language	VHDL
License	MIT (LICENSE)
FPGA / primitives	ECP5: EHXPLLL
Tests	none found

On ULX3S: Ready-made for hdl4fpga-based designs; for a generic new design emard-ecp5pll is more self-contained (single generic module vs. two purpose-specific entities).

Full review: hdl4fpga__hdl4fpga.