lattice-verilog-projects: open gateware for the ULX3S and small Lattice boards

Reusable open gateware for the ULX3S FPGA board (Radiona, Lattice ECP5 LFE5U-12F/25F/45F/85F) and other small Lattice boards (ECP5, iCE40 UP5K, iCE40 HX8K/HX4K), organised by function. For each function (HDMI, VGA, SDRAM, SD card, USB, UART, SPI, I2C, ADC, DAC, audio, radio, CPUs…) it gives the best core found in 376 open-source repos, the alternatives, links to the original files at the reviewed commit, their license and FPGA primitives, and the other projects that use them.

Use it to find prior art before writing a core. Start from Cores by function; check the board page for pin maps; read the guides to build, load and port; the in-depth reviews document the richest repos block by block.

Facts cite the upstream file at a pinned commit; nothing was built or simulated, and anything not verified is marked unknown. Check each core’s license before reusing it. Every page is generated from the JSON in data/ by the scripts described in the methodology.

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218 reusable cores in 34 functions, used by 274 of the 523 catalogued repos; 18 board pages; 20 in-depth reviews.


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Generated from the JSON in data/ by the scripts in .claude/skills. Facts cite the upstream file at the reviewed commit; verify before reuse.

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