DAC, PWM and sigma-delta

Sigma-delta/PWM/PDM DACs and external DAC interfaces.

Core	Repository	Language	License	FPGA	Used by
Sigma-delta PCM audio DAC (fpga-dac) ★	machdyne__fpga-dac	Verilog	1-clause BSD-like	ECP5	0
PDM audio DAC (hadbadge2019 soc/audio)	spritetm__hadbadge2019_fpgasoc	Verilog	BSD-3-Clause	any	0
Resistor+PWM hybrid DAC (dacpwm)	emard__ulx3s-misc	Verilog, VHDL	none found	any	7
Sigma-delta DAC (synthowheel)	emard__synthowheel	VHDL	BSD (LICENSE.txt: AUTHOR=EMARD LICENSE=BSD)	any	3
Sigma-delta DAC (up5k-demos)	daveshah1__up5k-demos	Verilog	none found	iCE40 UP5K	16

Cores

Sigma-delta PCM audio DAC (fpga-dac) (best)

First-order sigma-delta stereo audio DAC that streams 48kHz 16-bit signed PCM from SPI flash; simple phase accumulator, no vendor primitives in audio.v itself.

Repository	machdyne__fpga-dac: Machdyne Konfekt/Lakritz/Noir: experimental sigma-delta PCM audio DAC/player that streams 48kHz 16-bit stereo…
Files	rtl/audio.v
Top module	audio
Language	Verilog
License	1-clause BSD-like (LICENSE.md, Lone Dynamics Corporation)
FPGA / primitives	ECP5: none (portable)
Tests	none found

On ULX3S: Self-contained modulator (l_pwm_acc/r_pwm_acc); reuse just the sigma-delta block and drive it from any PCM source (SDRAM, ESP32, etc.) instead of SPI flash. rtl/pll.v is board-specific and needs re-deriving for 25 MHz ULX3S input.

PDM audio DAC (hadbadge2019 soc/audio)

First-order pulse-density-modulation DAC core with dither, used for the hadbadge2019 SoC’s audio synth output.

Repository	spritetm__hadbadge2019_fpgasoc: Hackaday Supercon 2019 badge: ECP5 SoC
Files	soc/audio/pdm.v
Top module	pdm
Language	Verilog
License	BSD-3-Clause (in-file header, LICENSE.bsd, Sylvain Munaut 2019)
FPGA / primitives	any: none (portable)
Tests	none found

On ULX3S: Pairs well with soc/audio/synth_core.v in the same repo; plain Verilog, no ECP5-specific primitives.

Full review: spritetm__hadbadge2019_fpgasoc.

Resistor+PWM hybrid DAC (dacpwm)

Combines a coarse resistor-ladder DAC (upper bits) with a PWM output (lower bits) to raise effective DAC resolution from a small pin count.

Repository	emard__ulx3s-misc: ULX3S misc/advanced examples: EMARD’s building-block library
Files	examples/audio/hdl/dacpwm.v, examples/audio/hdl/dacpwm_vhdl.vhd
Top module	dacpwm
Language	Verilog, VHDL
License	none found (no header in file; repo has no LICENSE file)
FPGA / primitives	any: none (portable)
Tests	waveform-only (examples/audio/testbench/sinewave.c is a plain C reference model, not a Verilog tb)

On ULX3S: Parametric C_pcm_bits/C_dac_bits; used in the ULX3S audio example (examples/audio/hdl/top_audio.v) with 25 MHz clock.

Full review: emard__ulx3s-misc.

Used by 7 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

• dan-rodrigues__icestation-32 (instantiates hardware/ulx3s/ics32_top_ulx3s.v)
• dan-rodrigues__ics-adpcm (instantiates demo/adpcm_demo_top.v)
• dlobato__cps1-musicbox (instantiates gateware/dacpwm.py)
• emard__ulx3s_c64 (instantiates rtl/top_ulx3s_v20_c64.vhd)
• f32c__f32c (instantiates rtl/generic/glue_xram_vector.vhd)
• lawrie__spinalulx3s (instantiates src/main/scala/mylib/DacPwm.scala)
• logoposeidon__ulx3sjukebox (instantiates audio_test.v)

Sigma-delta DAC (synthowheel)

Standalone sigma-delta modulator used to drive the audio output of the synthowheel ULX3S synth project.

Repository	emard__synthowheel: Synthowheel: polyphonic additive synth, 128 gen x 9 harmonics, SPDIF + sigma-delta
Files	sigmadelta.vhd
Top module	sigmadelta
Language	VHDL
License	BSD (LICENSE.txt: AUTHOR=EMARD LICENSE=BSD)
FPGA / primitives	any: none (portable)
Tests	none found

On ULX3S: Pairs with synth.vhd in the same repo; single-bit output suitable for a simple RC lowpass to line-out.

Used by 3 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

• f32c__f32c (instantiates rtl/generic/glue_xram.vhd)
• glasgowembedded__glasgow (instantiates software/glasgow/applet/audio/dac/__init__.py)
• tarik-hamedovic__sdr-hls (instantiates 3.Testing/1bitADCLattice/Lattice/First_Implementation/ADC_top_prim.v)

Sigma-delta DAC (up5k-demos)

Tiny parametric-width sigma-delta DAC (delta/sigma adder pair) used for the NES APU audio output.

Repository	daveshah1__up5k-demos: UPduino: UP5K demos - a buildable port of the MiST NES core to iCE40 UltraPlus
Files	nes/sigma_delta_dac.v
Top module	sigma_delta_dac
Language	Verilog
License	none found (repo has no LICENSE/COPYING file; nes.v claims GPL but no license text present)
FPGA / primitives	iCE40 UP5K: none (portable)
Tests	none found

On ULX3S: Plain Verilog, no SB_* primitives; drops onto ECP5 unchanged, only the surrounding NES top-level is iCE40-specific.

Used by 16 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):

• cheyao__nes_ecp5 (copies sigma_delta_dac.v)
• cheyao__sega-sms (instantiates src/sms.v)
• danodus__ulx3s_sms (instantiates src/sms.v)
• darklife__darkriscv (instantiates boards/de10nano_cyclonev_mister/sys/audio_out.v)
• emard__nes_ecp5 (instantiates top.v)
• emard__snes_mister_ulx3s (instantiates sys/audio_out.v)
• enjoy-digital__litedsp (instantiates impl/modules.py)
• gatecat__snes_mister_ulx3s (instantiates sys/audio_out.v)
• gojimmypi__z80386-ulx3s-doom (instantiates third_party/z386_MiSTer/sys/audio_out.v)
• ironsteel__nes_ecp5 (instantiates top.v)
• lawrie__ulx3s_gamegear (instantiates src/sms.v)
• lawrie__ulx3s_mac128 (instantiates src/mac128.v)
• lawrie__ulx3s_sms (instantiates src/sms.v)
• machdyne__nes_ecp5 (instantiates top.v)
• wifiboy__ok-ice40pro (instantiates ok-nes-vga-src/NES_okice40_pro.v)
• … and 1 more (see data/core_usage.json)

Other catalogued projects

Catalogued repos tagged audio-dac (63), dac (1) are listed in the full catalogue.