JTAG and debug
User JTAG access, debug bridges, logic analysers.
| Core | Repository | Language | License | FPGA | Used by |
|---|---|---|---|---|---|
| OpenCores JTAG TAP + JTAGG bridge ★ | emard__ulx3s-misc | Verilog | LGPL-2.1-or-later | ECP5 | 0 |
| Bonfire ECP5 JTAGG bridge + MyHDL LED demo | bonfireprocessor__bonfire-ecp5-jtagg-led-demo | VHDL, Python | MIT (LICENSE, Bonfire Processor / Thomas… | ECP5 | 1 |
| Cynthion USB analyzer (used by Packetry) | greatscottgadgets__cynthion | Python (Amaranth) | BSD-3-Clause | ECP5 | 0 |
| ECP5 JTAGG demo (Ecp5JtagDemo) | tomverbeure__ecp5_jtag | Verilog | none found | ECP5 | 0 |
| eSPI bus capture + packet decoder | johnazoidberg__ulx3s-espi-analyzer | Verilog | none found | ECP5 | 0 |
| OpenDAP SW-DP + Mem-AP (SWD debug probe) | wren6991__hazard3-swd-soc | Verilog | CC0-1.0 (file header + submodule LICENSE) | any | 0 |
| ORBTrace SWD/JTAG debug + parallel TRACE core (legacy plain-Verilog flow) | orbcode__orbtrace | Verilog | BSD-3-Clause | any | 0 |
| SUMP logic analyzer core (ECP5-ported) | lawrie__ice40logicsniffer | Verilog | GPL-2.0-or-later | ECP5 | 0 |
Cores
OpenCores JTAG TAP + JTAGG bridge (best)
Generic OpenCores JTAG TAP (jtag_slave.v, vendor-neutral) plus a demo top that bridges it through the ECP5 JTAGG primitive so user logic gets its own JTAG chain via the board’s existing FTDI/ESP32 JTAG.
| Repository | emard__ulx3s-misc: ULX3S misc/advanced examples: EMARD’s building-block library |
| Files | examples/jtag_slave/hdl/jtag_slave.v, examples/jtag_slave/hdl/jtag_slave_clk.v, examples/jtag_slave/hdl/tap_defines.v, examples/jtag_slave/hdl/top/top_jtagg_slave.v |
| Top module | jtag_slave |
| Language | Verilog |
| License | LGPL-2.1-or-later (jtag_slave.v OpenCores tap_top.v header, Igor Mohor/Nathan Yawn); top_jtagg_slave.v: none found |
| FPGA / primitives | ECP5: JTAGG, ODDRX1F |
| Tests | none found |
On ULX3S: top_jtagg_slave.v is a real ULX3S example (clk_25mhz, btn/led/oled/gpdi ports); ODDRX1F instances are only in the demo’s DVI/OLED wiring, not the TAP itself.
Full review: emard__ulx3s-misc.
Bonfire ECP5 JTAGG bridge + MyHDL LED demo
Static VHDL wrapper directly instantiating the ECP5 JTAGG primitive (JTAG USER1/2 data registers), driven by portable MyHDL logic that shifts a bit pattern into an LED register on JCE1/JSHIFT/JUPDATE.
| Repository | bonfireprocessor__bonfire-ecp5-jtagg-led-demo: Standalone MyHDL/FuseSoC demo wrapping the ECP5 JTAGG primitive to shift an LED pattern via the JTAG USER1/2… |
| Files | fusesoc/vhdl/ecp5_jtagg_bridge.vhd, src/bonfire_ecp5_jtagg_led_demo/jtagg_interface.py, src/bonfire_ecp5_jtagg_led_demo/led_demo.py |
| Top module | ecp5_jtagg_bridge |
| Language | VHDL, Python (MyHDL) |
| License | MIT (LICENSE, Bonfire Processor / Thomas Hornschuh 2017) |
| FPGA / primitives | ECP5: JTAGG |
| Tests | pytest, self-checking (tests/test_led_demo_logic.py runs a MyHDL behavioral sim and asserts the LED shift register matches the expected pattern) |
On ULX3S: fusesoc/fpga/ulx3s/{board.lpf,ulx3s_jtagg_led_top.vhdl} target LFE5U-85F-6BG381C directly; extracted from bonfireprocessor__bonfire-core’s own ulx3s_jtagg FuseSoC target.
Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):
Cynthion USB analyzer (used by Packetry)
Official low/full/high-speed USB protocol analyzer core: captures traffic on Cynthion’s TARGET port (via LUNA’s UTMITranslator + speed/event detection) into a FIFO, streamed to the host over a USB2 device endpoint; the capture backend for greatscottgadgets/packetry.
| Repository | greatscottgadgets__cynthion: Cynthion: official GSG gateware |
| Files | cynthion/python/src/gateware/analyzer/analyzer.py, cynthion/python/src/gateware/analyzer/top.py, cynthion/python/src/gateware/analyzer/event_detection.py, cynthion/python/src/gateware/analyzer/speed_detection.py, cynthion/python/src/gateware/analyzer/fifo.py |
| Top module | USBAnalyzer |
| Language | Python (Amaranth) |
| License | BSD-3-Clause (repo LICENSE.txt; per-file SPDX header) |
| FPGA / primitives | ECP5: none (portable) |
| Tests | self-checking: USBAnalyzerTest / USBAnalyzerStackTest classes in analyzer.py (LunaGatewareTestCase, amaranth.sim) |
On ULX3S: Needs a Cynthion (or another 3-ULPI-PHY LUNA board); built via python -m cynthion.gateware.analyzer.top --output build/analyzer.bit on the cynthion_r1_4 platform.
ECP5 JTAGG demo (Ecp5JtagDemo)
Minimal, well-documented instantiation of the ECP5 JTAGG primitive with a reverse-engineering write-up of its TCK/TDI/TDO timing.
| Repository | tomverbeure__ecp5_jtag: Colorlight i5: reverse-engineering notes plus a SpinalHDL/Verilog example demonstrating the Lattice ECP5… |
| Files | verilog/top.v, tb/src/JTAGG.v |
| Top module | Ecp5JtagDemo |
| Language | Verilog |
| License | none found |
| FPGA / primitives | ECP5: JTAGG |
| Tests | tb/ iverilog testbench, waveform-only ($dumpvars, no PASS/FAIL) |
On ULX3S: Built for a Colorlight i5 (ECP5-25F); pin remap only needed to reuse on ULX3S.
eSPI bus capture + packet decoder
eSPI (Enhanced SPI) bus signal capture with CDC double-registering and single/dual/quad IO decode, plus a packet decoder pipeline.
| Repository | johnazoidberg__ulx3s-espi-analyzer: JohnAZoidberg/ulx3s-espi-analyzer: passive eSPI bus sniffer/analyzer for ULX3S |
| Files | hdl/espi_capture.v, hdl/espi_packet_decoder.v |
| Top module | espi_capture |
| Language | Verilog |
| License | none found (repo-wide; only ecp5pll.sv credited BSD to EMARD) |
| FPGA / primitives | ECP5: none (portable) |
| Tests | none found |
On ULX3S: Nix-flake reproducible ULX3S build (default 12F, also 25/45/85); a purpose-built protocol logic analyzer, not a generic one.
OpenDAP SW-DP + Mem-AP (SWD debug probe)
ADIv5.2 SW-DP (Serial Wire Debug) and APB Mem-AP implementation: an alternative to JTAG for debugging soft cores.
| Repository | wren6991__hazard3-swd-soc: Example SoC: Hazard3 RISC-V core + OpenDAP SWD debug port + SRAM/UART/timer |
| Files | lib/opendap/hdl/opendap_sw_dp.v, lib/opendap/hdl/opendap_mem_ap_apb.v |
| Top module | opendap_sw_dp |
| Language | Verilog |
| License | CC0-1.0 (file header + submodule LICENSE) |
| FPGA / primitives | any: none (portable) |
| Tests | lib/opendap/test/{dp,dap}/testcase (cxxrtl, self-checking tb_assert) |
On ULX3S: Repo’s own README calls the SoC experimental (“no idea how to program it”); the DP/Mem-AP cores themselves are standalone and CC0.
ORBTrace SWD/JTAG debug + parallel TRACE core (legacy plain-Verilog flow)
Cortex-M debug (SWD + JTAG) state machines behind a common dbgIF, plus a 1-4 bit parallel TRACE capture core (traceIF), validated against BlackMagic Probe/OpenOCD/pyOCD (debug) and Orbuculum (trace). Each block has its own testbed under verilog/testbeds/.
| Repository | orbcode__orbtrace: ORBTrace: Cortex-M SWD/JTAG debug + parallel TRACE probe gateware |
| Files | verilog/dbgIF.v, verilog/swdIF.v, verilog/jtagIF.v, verilog/traceIF.v, verilog/ram.v |
| Top module | dbgIF |
| Language | Verilog |
| License | BSD-3-Clause (COPYING, applies repo-wide unless a file states otherwise) |
| FPGA / primitives | any: none (portable) |
| Tests | verilog/testbeds/{dbgIF_tb,swdIF_tb,jtagIF_TB,traceIF_tb}.v - waveform-only (no assertions seen; iverilog/vvp style testbenches, not scanned by Makefile) |
On ULX3S: Plain Verilog, no vendor primitives; this legacy flow already builds for ECP5 (verilog/Makefile ECPIX_5_85F target: yosys+nextpnr-ecp5+ecppack) and for iCE40 (ICEBREAKER/ICE40HX8K_B_EVN targets). Needs a USB-Bulk/CMSIS-DAP front-end (from verilog/uart.v+frameToSerial.v or the main orbtrace/ Amaranth SoC) to be a complete probe.
SUMP logic analyzer core (ECP5-ported)
Classic openbench SUMP-protocol logic analyzer (sampler, RLE encoder, trigger, BRAM ring buffer) already re-targeted to ECP5 via ecp5_pll.v (an SB_PLL40_CORE version, pll.v, also exists for iCE40).
| Repository | lawrie__ice40logicsniffer: Open Bench Logic Sniffer |
| Files | src/Logic_Sniffer.v, src/core.v, src/sampler.v, src/rle_enc.v, src/trigger.v, src/ecp5_pll.v |
| Top module | Logic_Sniffer |
| Language | Verilog |
| License | GPL-2.0-or-later (file headers, Copyright 2006 Michael Poppitz) |
| FPGA / primitives | ECP5: EHXPLLL |
| Tests | src/Logic_Sniffer_tb.v present, not confirmed self-checking |
On ULX3S: Built –25k with an idcode for 12F in this repo; BRAM-based capture buffer, not SDRAM-backed.
Other catalogued projects
Catalogued repos tagged jtag (50), debug-bridge (9), logic-analyzer (15), debug-instrument (2) are listed in the full catalogue.