SPI flash
SPI/QSPI flash readers, XIP controllers and flash writers.
| Core | Repository | Language | License | FPGA | Used by |
|---|---|---|---|---|---|
| spimemio SPI/QSPI flash XIP controller ★ | yosyshq__picorv32 | Verilog | ISC (COPYING; per-file header) | any | 11 |
| MappedSPIFlash read-only XIP driver | mb-sat__ulx3s-longwave-sdr | Verilog | GPL-3.0 (repo LICENSE) | any | 1 |
| NEORV32 ULX3S XIP flash-execute top | fedy0__neo | VHDL | BSD-3-Clause | ECP5 | 0 |
| qspi_phy_ecp5 QSPI flash PHY (ECP5-native) | emard__had2019-playground | Verilog | BSD-3-clause | ECP5 | 2 |
| Wishbone Quad-SPI flash controller (Gisselquist-derived) | emard__ulx3s-misc | Verilog | GPL-3.0 (Gisselquist Technology LLC 2015-2016,… | any | 0 |
Cores
spimemio SPI/QSPI flash XIP controller (best)
Memory-mapped SPI-flash execute-in-place controller from PicoSoC: no vendor primitives, expects four bidirectional flash_io[0:3] pins split into oe/do/di triples. Widely reused, well-tested reference XIP controller.
| Repository | yosyshq__picorv32: PicoRV32: size-optimized RISC-V |
| Files | picosoc/spimemio.v |
| Top module | spimemio |
| Language | Verilog |
| License | ISC (COPYING; per-file header) |
| FPGA / primitives | any: none (portable) |
| Tests | root Makefile self-checking testbenches (test/test_wb/test_synth/…) exercise picosoc including spimemio via firmware; no standalone spimemio testbench found |
On ULX3S: Needs a board-side tristate wrapper (ECP5 generic inout/BB instead of the reference tops’ iCE40 SB_IO) for the shared ULX3S config-flash pins.
Full review: yosyshq__picorv32.
Used by 11 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- chipflow__example-socs (instantiates
my_design/design.py) - gtjennings1__hyperbus (instantiates
riscv32/hardware/picosoc.v) - im-tomu__foboot (copies
hw/rtl/spimemio.v) - im-tomu__fomu-workshop (copies
litex/rtl/spimemio.v) - kelu124__lit3rick (instantiates
micropython/source/picosoc.v) - mkvenkit__learn_fpga (instantiates
ice40up5k/picosoc_gpio/picosoc.v) - mmicko__fpga101-workshop (instantiates
tutorials/12-RiscV/picosoc.v) - nklabs__libnklabs-ulx3s (instantiates
rtl/bus_spiflash.v) - rxrbln__picorv32 (instantiates
picosoc/picosoc.v) - spritetm__hadbadge2019_fpgasoc (instantiates
soc/picorv32/picosoc/picosoc.v) - wuxx__icesugar (instantiates
src/advanced/picorv32/picosoc/picosoc.v)
MappedSPIFlash read-only XIP driver
Minimal read-only SPI-flash-in-memory-space driver from Bruno Levy’s FemtoRV32 project, vendored to run the FemtoRV32 core on the ULX3S 85F longwave-SDR design.
| Repository | mb-sat__ulx3s-longwave-sdr: mb-sat/ulx3s-longwave-sdr: longwave/VLF direct-conversion SDR receiver for ULX3S 85F |
| Files | logic/common-verilog/MappedSPIFlash.v |
| Top module | MappedSPIFlash |
| Language | Verilog |
| License | GPL-3.0 (repo LICENSE) |
| FPGA / primitives | any: none (portable) |
| Tests | none found |
On ULX3S: Read-only (no write/erase); smallest option here when a design only needs to execute firmware from flash.
Used by 1 other catalogued repo (file copies or module instances found by scan_core_usage.py; heuristic):
- brunolevy__learn-fpga (instantiates
FemtoRV/RTL/femtosoc.v)
NEORV32 ULX3S XIP flash-execute top
ULX3S 85F board top pairing the NEORV32 RISC-V core’s built-in XIP module with the ECP5 config-flash pins (USRMCLK), so firmware executes directly from SPI flash instead of block RAM.
| Repository | fedy0__neo: NEORV32 RISC-V SoC running on the ULX3S |
| Files | top/neorv32_ULX3S_xip.vhd |
| Top module | neorv32_ULX3S_xip |
| Language | VHDL |
| License | BSD-3-Clause (NEORV32, Stephan Nolting 2023) |
| FPGA / primitives | ECP5: USRMCLK |
| Tests | none found |
On ULX3S: Built via a dedicated Makefile.xip target; simplest path to XIP-from-flash on ULX3S if already using NEORV32.
qspi_phy_ecp5 QSPI flash PHY (ECP5-native)
ECP5-native QSPI flash PHY (drives USRMCLK and the shared config-flash IO through TRELLIS_IO/IFS1P3DX/OFS1P3DX) used by the PicoRV32-based USB DFU bootloader that ships bitstreams into ULX3S flash from the US2 port.
| Repository | emard__had2019-playground: HAD2019 badge playground |
| Files | projects/bootloader/rtl/qspi_phy_ecp5.v |
| Top module | qspi_phy_ecp5 |
| Language | Verilog |
| License | BSD-3-clause (Sylvain Munaut 2019, file header + LICENSE.bsd) |
| FPGA / primitives | ECP5: USRMCLK, TRELLIS_IO, IFS1P3DX, OFS1P3DX |
| Tests | none found |
On ULX3S: Proven in production on ULX3S (emard’s DFU bootloader, 1d50:614b); pairs with picorv32/picosoc for a full XIP+DFU stack.
Used by 2 other catalogued repos (file copies or module instances found by scan_core_usage.py; heuristic):
- smunaut__had2019-playground (instantiates
projects/bootloader/rtl/top.v) - ulx3s__hazard3-doom (instantiates
bootloader/rtl/top-ulx3s.v)
Wishbone Quad-SPI flash controller (Gisselquist-derived)
ZipCPU/Gisselquist eqspiflash core (originally for the Arty board) wrapped as a Wishbone slave (wbqspiflash), ported into EMARD’s ULX3S example library with read/write/erase register control and XIP support.
| Repository | emard__ulx3s-misc: ULX3S misc/advanced examples: EMARD’s building-block library |
| Files | examples/qspi/hdl/wbspiflash.v, examples/qspi/hdl/eqspiflash.v, examples/qspi/hdl/llqspi.v |
| Top module | wbqspiflash |
| Language | Verilog |
| License | GPL-3.0 (Gisselquist Technology LLC 2015-2016, file header) |
| FPGA / primitives | any: none (portable) |
| Tests | bench/busmaster.v simulation harness (not confirmed self-checking) |
On ULX3S: GPL-3.0 copyleft; has a bench/busmaster.v simulation harness for standalone verification before wiring into a SoC.
Full review: emard__ulx3s-misc.
Other catalogued projects
Catalogued repos tagged flash-spi (58) are listed in the full catalogue.