Architecture

rp417 is a test fixture on a board: an RP2354B (always powered) controls a CH32H417MEU6 (QFN88), the device under test. A host PC talks to both over USB, so a script can power, reset, flash, stimulate and measure the CH32 without anyone touching the board. Guiding constraint (D22): as simple as possible, minimal BOM — firmware and on-chip resources first, extra ICs only where they earn their place.

            USB-C J3                         USB-C J1 (USB3 SS + USB2 HS)   USB-C J2 (USB FS / ISP)
               │                                   │        │                      │
        ┌──────┴──────┐  UART · I2C · QSPI    ┌────┴────────┴──────┐               │
        │   RP2354B   │  8-line logic bus     │                    ├───────────────┘
        │ supervisor  ├──────────────────────►│   CH32H417MEU6     │
        │ (always on) │  HSYNC · VSYNC · MARK │   (DUT, switched   │── microSD J4 (SDIO)
        │             │                       │    power domain)   │
        │  PIO count ─┼──► 2:1 switch ──DVP──►│                    │
        │             │        ▲              │  PB8/PB9 (HS + SDI)│
        │  SWIO/SWCLK ┼── TS3USB221A ◄────────┤                    │
        │  NRST, PWR  ┼──────────────────────►│                    │
        │  Si5351A ───┼─ CLK0 ─► ADC10065 ────┘ (D0–D9 into the 2:1 switch)
        │             ├─ CLK1 ─► PCLK
        │             └─ CLK2 ─► LC filter ─► GEN ─► J5 ─► ADC10065 / CH32 ADC + HSADC (PC0)
        └─────────────┘

The full mermaid block diagrams from the design phase are on the design page.

Inter-chip links

All RP↔CH32 lines have a series resistor — 33 Ω on QSPI, the logic bus and the sync lines, 220 Ω on the UART, 100 Ω on I2C, 22 Ω on the capture data, 1 kΩ on NRST — to limit clamp current if the RP drives a line while the CH32 domain is off (D29). Full list: pin map.

Link	Pins	Notes
UART	RP GPIO0/1 ↔ CH32 PA9/PA10 (USART1)	also the CH32’s UART ISP pins on QFN88
I2C	RP GPIO2/3 ↔ CH32 PB10/PB11	pull-ups on the CH32 rail (D29)
QSPI	RP GPIO6–11 ↔ CH32 PE10–PE15	CH32 QSPI is master-only (RM V1.8 ch. 37) → RP PIO slave (D38)
Logic bus	RP GPIO12–19 ↔ CH32 PD10–PD15, PC6, PC7	8 general-purpose lines (D03, D56)
Capture control	RP GPIO31/32 → HSYNC PA4 / VSYNC PA5; GPIO33 → shot marker PB14 (TIM9_CH1); GPIO34 ← CH32 MCO	D37, D56
Programming	RP GPIO35/36 → SWIO/SWCLK (via U4); GPIO37 → NRST; GPIO38 → CH32 power enable	D11, D26

Programming the CH32

• Primary: the RP2354B runs a port of ch32fun’s funprog programmer and appears to the host as a USB device that minichlink drives. It bit-bangs 1-wire SWIO or 2-wire RVSWD on PB9/PB8 (D11).
• PB8/PB9 are also the CH32’s USB HS D+/D−. A TS3USB221A (U4, RP GPIO39 USB_SEL) connects them either to J1 (default, also when the RP is absent) or to the RP’s SWD pins. It doubles as a software “unplug” for USB HS tests (D26).
• Fallback: the CH32 has no BOOT0 pin; it enters its bootloader by power-cycling. The RP can drive the WCH UART ISP protocol on PA9/PA10, or the host can use USB ISP on J2 (DP high at power-on). See the hardware notes.

Capture path

• ADC10065 (U10, 10-bit 65 MSPS, DNP — hand-soldered by the user, D42) clocked by Si5351 CLK0. Its input comes from header J5: jumper 1–2 = on-board generator, 2–3 = external input (49.9 Ω terminated, clamped by D5). Input range set by solder jumper JP1 (default 2 Vpp, D44).
• 2:1 capture switch (3 × SN74CBTLV3257, U11–U13, D55): CAP_SEL (RP GPIO42, pull-down → ADC by default) feeds the CH32 DVP either from the ADC10065 or from a 10-bit counter pattern generated by RP PIO (GPIO20–29
  • side-set PCLK GPIO30). The counter shows lost, duplicated or reordered samples exactly. The switches are in the CH32 power domain (I_off isolation) and sit next to their DVP pins (D57).
• DVP pins (QFN88): D0 PE0, D1 PE1, D2 PB13, D3 PE3, D4 PE4, D5 PF14, D6 PE5, D7 PE6, D8 PF4, D9 PF3, PCLK PB12 (the only PCLK pin on QFN88), HSYNC PA4, VSYNC PA5. PCLK also clocks TIM8_ETR (PF2) to count samples (D56).
• DVP in JPEG mode with a static HSYNC lets the DMA switch buffers by length; gapless continuous capture is still to be proven on hardware (D37).

Clocks and test signal

• Si5351A-B-GTR (genuine, D46): CLK0 → ADC10065 clock; CLK1 (same PLL, phase-tunable) → PCLK; CLK2 (second PLL) → test-signal generator (D32).
• Generator (D31, D33): CLK2 → 49.9 Ω → 5th-order Butterworth LC low-pass (68 pF / 470 nH / 220 pF / 470 nH / 68 pF), doubly terminated. Clean sine from about 10 MHz to the ≈ 28.6 MHz corner, a shaped square below; amplitude estimated at 1.5–2 Vpp (to bench-verify). Meant for throughput tests, not signal fidelity (D05).
• CH32 ADC + HSADC (D35): the same input net reaches PC0 (ADC_IN10 + HSADC_IN0) through a series R, an AC coupling cap and a VDD33A/2 bias. J6 (2×2, D64/D65) exposes PC1 (HSADC_IN1) and PC3 (HSADC_IN3) through 100 Ω, with GND and the generator output, for multi-channel tests.

User I/O

• D6 RGB LED on the RP (GPIO43/46/47) and D7 RGB LED on the CH32 (PC2/PF0/PF1), common anode, each on its own chip’s rail so a switched-off CH32 is never back-fed (D62, D63, D66).
• SW1 BOOTSEL (RP), SW2 CH32 reset.
• J7 SAO header (2×3, SAO v1.69bis pinout) on RP I2C0 = GPIO44 SDA / GPIO45 SCL, 4.7 kΩ pull-ups, VCC = +3V3 (D66).
• The 2.54 mm headers J5, J6, J7 are not assembled by JLCPCB (DNP, D68).

Standalone mode

The RP2354B is always on the board and always powered. “Standalone” means no host on the RP’s USB: its firmware boots into safe defaults (CH32 powered, NRST released, USB switch → connector, generator off), and the CH32 can command the RP over UART/I2C (generator frequency, sample clock, rail measurements) so CH32-only tests keep their stimulus (D15, R10).

Not on rev A

UHSIF capture (parked, D21), an external power input (D41), current monitoring ICs (D28: the RP’s ADC watches the CH32 rail and VSYS instead), an on-board WCH-LinkE (D10), a CH32 debug header (dropped 2026-11-14).