rp417 — block diagram & pin plan

CH32H417QEU6 test board supervised by an RP2350 · rev A · proposals P1–P3 · updated 2026-11-13 · source of truth: .claude/SPEC.md, .claude/DECISIONS.md

decided = logged in .claude/DECISIONS.md   proposed = new in this document, awaiting approval   withdrawn = replaced by a later proposal

Rev A, redrawn 2026-11-13 for D22–D48 (minimal BOM). Parts list and area budget: §8–§9.

1. System block diagram

Rev A after the minimal-BOM constraint (D22–D41). Wide diagram: scroll sideways inside the frame.

flowchart TB
  HOST(["Host PC - test scripts"])
  HOST --- J3["J3 USB-C 2.0
RP2350"]
  HOST --- J1["J1 USB-C 3.x
CH32 USB3, single orientation"]
  HOST --- J2["J2 USB-C 2.0
CH32 USBFS / ISP"]

  subgraph SUP["Always-on 3V3 domain"]
    direction TB
    RP["RP2354B
RP2350B + 2 MB flash"]
    SI["Si5351A
CLK0 ADC clock, CLK1 PCLK, CLK2 generator"]
    LPF["LC low-pass 5th order
fc ~30 MHz"]
    HDR["1x4 header + jumper
GEN / ADC_IN / EXT / GND"]
    RP -- "I2C0" --- SI
    SI -- "CLK2" --> LPF --> HDR
  end

  J3 --- RP
  J1 -- "SS pairs direct, CC = 5.1k Rd" --- CH
  J1 -- "D+ / D-" --- USW["TS3USB221A
USB2 switch"]
  USW -- "SWIO / SWCLK" --- RP

  subgraph TGT["CH32 domain - load switch, RP-controlled, default ON"]
    direction TB
    CH["CH32H417MEU6
QFN88, internal 1V2 LDO"]
    ADC["ADC10065 - DNP
user-fitted, 10-bit 65 MSPS"]
    SD["microSD"]
    CH --- SD
  end

  HDR -- "ADC_IN single-ended, AC + VCOM bias" --> ADC
  HDR -- "ADC_IN, AC + mid-rail bias" --> CH
  SI -- "CLK0" --> ADC
  SI -- "CLK1 PCLK" --> CSW
  ADC -- "D0-D9" --> CSW
  RP -- "counter D0-D9 + PCLK" --> CSW["3 x SN74CBTLV3257
2:1 capture switch"]
  CSW -- "DVP D0-D9, PB12 PCLK" --> CH
  RP -- "logic bus 8 GPIO" --- CH
  RP -- "UART, I2C, QSPI, HSYNC/VSYNC, marker, MCO
series R, firmware tri-state" --- CH
  USW -- "PB8 / PB9 USBHS" --- CH
  J2 -- "PA11 / PA12" --- CH
  RP -- "NRST open-drain, PWR_EN" --> CH

2. Power tree

flowchart LR
  V1["J1 VBUS"] --> D1["LM66100"]
  V2["J2 VBUS"] --> D2["LM66100"]
  V3["J3 VBUS"] --> D3["LM66100"]
  D1 & D2 & D3 --> VSYS(["VSYS 5 V"])
  VSYS --> B0["Buck 5 V to 3V3, 2 A
always on"]
  B0 --> SUPL["RP2354B, Si5351A,
TS3USB221A"]
  B0 --> LS{{"Load switch, quick discharge
EN = RP GPIO38, pull-up = default ON"}}
  LS --> C33(["3V3_CH32"])
  C33 --> CHP["CH32 VDD33, VDDIO = VIO18
internal LDO: VDDK, VDD12A"]
  C33 --> FB["ferrite + caps"] --> AV["VDD33A, VREFP
ADC10065 VA"]
  C33 --> SDP["microSD, ADC10065 VDR"]
  RPA["RP ADC GPIO40/41"] -. "senses" .- C33
  RPA -. "senses" .- VSYS

3. Capture path detail (D55)

flowchart LR
  SI0["Si5351 CLK0"] --> ADCCLK["ADC10065 CLK"]
  ADCD["ADC10065 D0-D9 (DNP)
33 ohm series"] --> B1["switch B1"]
  SI1["Si5351 CLK1
phase-tunable"] --> B1
  RPD["RP2350 PIO counter
GPIO20-29 + PCLK GPIO30"] --> B2["switch B2"]
  SEL["RP GPIO42 CAP_SEL
pull-down = ADC"] --> SW
  B1 & B2 --> SW["3 x SN74CBTLV3257
2:1, 11 lines, CH32 domain"]
  SW -- "D0-D9" --> DVP["CH32 DVP
PE0 PE1 PB13 PE3 PE4 PF14 PE5 PE6 PF4 PF3"]
  SW -- "PCLK" --> PCLK["PB12 DVP_PCLK"]
  SW -- "PCLK" --> ETR["PF2 TIM8_ETR
sample counter"]
  RPS["RP2350 GPIO31/32"] --> SYNC["PA4 HSYNC static, PA5 VSYNC frame"]

• QFN88 (D54) has only one DVP_PCLK pin (PB12) and no free second set for D2, so the alternate-pin trick (D36) is replaced by a 2:1 FET switch (D55). Switch powered from 3V3_CH: Ioff isolates the RP and the Si5351 when the CH32 is off.
• Counter is now the full 10 bits; DVP in 10-bit mode stores 16-bit words → 130 MB/s at 65 MS/s.
• DVP in JPEG mode: HSYNC may be held static, buffer switching follows the DMA length (RM V1.8 §29.2.2, §29.3.1) → RP sync needs no alignment to PCLK (D37).
• RP2350 PIO: one sample per two instructions → ~75 MS/s at 150 MHz. 33 Ω series on all counter lines.
• ADC10065 fitted by hand (DNP, D42).

3b. Analog front-end

flowchart LR
  CLK2["Si5351 CLK2
3.3 V square"] --> RS["50 ohm series"] --> LC["5th-order LC LPF
fc ~30 MHz, 50 ohm"] --> RT["50 ohm termination"]
  RT --> P1(["hdr 1 GEN"])
  EXT(["hdr 3 EXT"]) --> PROT["49.9 ohm term,
series R + clamp diodes"]
  P1 -. "jumper 1-2" .- P2(["hdr 2 ADC_IN"])
  PROT -. "jumper 2-3" .- P2
  P2 --> AC1["AC cap + R to VCOM"] --> ADC["ADC10065 VIN+
VIN- = VCOM, IRS"]
  P2 --> AC2["series R + AC cap +
VDD33A/2 divider"] --> PC0["CH32 PC0
ADC_IN10 + HSADC_IN0"]

• Doubly-terminated filter: fundamental ≈ (4/π)·(3.3/2)·½ ≈ 1 V peak ⇒ ≈ 2 V_pp ideal; the Si5351 driver impedance lowers it (estimate 1.5–2 V_pp, bench-verify). Clean sine from ≈ 10 to 30 MHz; below f_c/3 a shaped square.
• ADC10065 single-ended full scale = 2.0 / 1.5 / 1.0 V_pp for IRS = VDDA / VSSA / floating (ADC10065.md) — IRS on a 3-way solder jumper, default VDDA = 2 V_pp (D44).
• CH32 ADCs get the same net with no anti-alias filter: 10–30 MHz aliases at 5/20 MSPS (deterministic, fine for throughput, D35).

4. CH32H417MEU6 pin plan (QFN88, D54)

Generated from hw/gen/nets.json; pins/AF from datasheets/CH32H417DS0_V1.9_en.md (pin table, Table 2-2-4, 2-2-23). All I/O at 3.3 V (D23). QFN88 has no VREFP/VBAT/VSSA pins.

Free: PA0, PA13, PA14, PA15, PB1, PB3, PB4, PC1, PC2, PC3, PD1, PD3, PD4, PD5, PD6, PD7, PF0, PF1, PF5.

5. RP2354B pin plan (48 GPIO)

RP2354B kept (D24): 43 of 48 GPIO used, 5 spare (GPIO43–47).

6. RP2350 ↔ CH32 interconnect

No bus switches (D29): the RP2350 is always powered, so the only back-feed direction is RP → CH32. Power-off sequence in RP firmware: tri-state GPIO0–36 and 42, disable Si5351 CLK0–2, assert NRST, then drop PWR_EN; check GPIO40 reads ≈ 0 V. Series resistors only limit clamp current if firmware misbehaves.

7. New proposals in this document (to approve → .claude/DECISIONS.md)

P2 — after the simplification constraint D22 (2026-11-13)

P3 — parts list and area budget (2026-11-13)

P4 — after the QFN88 rework (2026-11-13)

8. Parts list — ICs and key parts (JLC/LCSC snapshot 2026-11-13)

JLC parts API, stock and USD price @10 / @100. B = Basic, E = Extended. Passives (0402 R/C) not listed. Economic vs Standard assembly is not shown by the API → check in the JLC quote.

• ≈ 20 unique IC/connector lines, almost all Extended (each adds JLC's Extended-part loading fee). Basic only: 25 MHz HSE crystal, ferrite, buttons, and the 0402 passives.
• Rejected: WAS4729 (80 MHz BW, not USB2 HS), TPS22919 (1.5 A).

9. Area budget (playing-card outline, D19)

Courtyard estimates incl. local decoupling, from package sizes (CH32H417MEU6 QFN88 = 10 × 10 mm, 0.4 mm pitch, D54; DS V1.9 §4.1). Board = 63.5 × 88.9 mm = 5645 mm² per side.

• Fits on one side with room for routing (rule of thumb: ≤ 50–60 % placement density), but parts go on both sides where it helps (D48):
• Top: connectors J1–J5, microSD, CH32, RP2354B, Si5351 + crystals, ADC10065 (hand-fitted), buck + inductor, TS3USB221A, ESD (at the connectors), LC filter, buttons.
• Bottom: CH32 / RP2354B / Si5351 decoupling directly under their power pins (shortest loops, frees the top ring for DVP / USB3 / SDMMC fan-out), series-R arrays on the RP↔CH32 lines, bias networks, LM66100 ×3, load switch, test pads.
• Placement sketch: J1 + J2 on one short edge with the CH32 right behind J1 (SS pairs < 15 mm); J3 on the opposite short edge next to the RP2354B; microSD at a corner beside the CH32 (SDMMC on PC8–PC12/PD2 side); ADC10065 + filter + header along a long edge next to the DVP pins (PE0–PE6, PF3/PF4/PF14), away from J1; logic lines (PD10–15/PC6/PC7) and counter lines (RP GPIO20–30 → 2:1 switch) run RP → CH32, length-matched loosely (≤ 5 mm skew at 75 MHz).
• QFN88 at 0.4 mm pitch (D54, LCSC footprint QFN-88_L10.0-W10.0-P0.40-BL-EP7.7): standard JLC 6-layer rules are enough.