Pin map — RP2354B ↔ CH32H417MEU6
Generated by hw/gen/gen_site.py from the schematic netlist (hw/gen/build.py is the source of truth).
Pin numbers are package pins: CH32H417MEU6 QFN88 (U1), RP2354B QFN80 (U2). Design rationale: architecture; decisions are referenced as Dxx.
1. Direct RP2354B ↔ CH32 links
Every line between the two chips has a series resistor (back-feed limit when the CH32 domain is off, D29).
Not listed here: the DVP capture bus and PCLK (through the 2:1 switches U11–U13, D55) and the CH32 debug
pins PB8/PB9 (through the USB switch U4, D26) — see architecture.
| RP2354B pin |
RP net |
Series part |
CH32 pin |
CH32 function |
CH32 net |
| 3 GPIO6 |
QSPI_SCK_RP |
R54 33 |
26 |
PE10 |
QSPI_SCK |
| 4 GPIO7 |
QSPI_CS_RP |
R55 33 |
27 |
PE11 |
QSPI_CS |
| 6 GPIO8 |
QSPI_IO0_RP |
R56 33 |
28 |
PE12 |
QSPI_IO0 |
| 7 GPIO9 |
QSPI_IO1_RP |
R57 33 |
29 |
PE13 |
QSPI_IO1 |
| 8 GPIO10 |
QSPI_IO2_RP |
R58 33 |
30 |
PE14 |
QSPI_IO2 |
| 9 GPIO11 |
QSPI_IO3_RP |
R59 33 |
31 |
PE15 |
QSPI_IO3 |
| 11 GPIO12 |
LOGIC0_RP |
R60 33 |
41 |
PD12 |
LOGIC0 |
| 12 GPIO13 |
LOGIC1_RP |
R61 33 |
42 |
PD13 |
LOGIC1 |
| 13 GPIO14 |
LOGIC2_RP |
R62 33 |
43 |
PD14 |
LOGIC2 |
| 14 GPIO15 |
LOGIC3_RP |
R63 33 |
44 |
PD15 |
LOGIC3 |
| 16 GPIO16 |
LOGIC4_RP |
R64 33 |
39 |
PD10 |
LOGIC4 |
| 17 GPIO17 |
LOGIC5_RP |
R65 33 |
40 |
PD11 |
LOGIC5 |
| 18 GPIO18 |
LOGIC6_RP |
R66 33 |
50 |
PC6 |
LOGIC6 |
| 19 GPIO19 |
LOGIC7_RP |
R67 33 |
51 |
PC7 |
LOGIC7 |
| 39 GPIO31 |
HSYNC_RP |
R79 33 |
22 |
PA4/ADC4/DAC1 |
DVP_HSYNC |
| 40 GPIO32 |
VSYNC_RP |
R80 33 |
23 |
PA5/ADC5/OP1_O1/DAC2 |
DVP_VSYNC |
| 42 GPIO33 |
MARK_RP |
R81 33 |
38 |
PB14 |
CH_MARK |
| 43 GPIO34 |
MCO_RP |
R82 33 |
24 |
PB0/ADC8/OP1_P0/CMP_P0 |
CH_MCO |
| 46 GPIO37 |
CH_NRST_RP |
R83 1k |
14 |
NRST |
CH_NRST |
| 77 GPIO0 |
RP_UART_TX |
R50 220 |
55 |
PA10/OTG_ID |
CH_UART_RX |
| 78 GPIO1 |
RP_UART_RX |
R51 220 |
54 |
PA9/OTG_VBUS |
CH_UART_TX |
| 79 GPIO2 |
RP_SDA |
R52 100 |
33 |
PB11 |
CH_SDA |
| 80 GPIO3 |
RP_SCL |
R53 100 |
32 |
PB10 |
CH_SCL |
2. CH32H417MEU6 (U1, QFN88) — all pins
| Pin |
Function |
Net |
| 1 |
VDD33 |
+3V3_CH |
| 2 |
PE3 / SERDES_TXP |
CAP_D3 |
| 3 |
PE4 / SERDES_TXN |
CAP_D4 |
| 4 |
PE5 / SERDES_RXP |
CAP_D6 |
| 5 |
PE6 / SERDES_RXN |
CAP_D7 |
| 6 |
VDDK |
VDDK |
| 7 |
MDIRN |
— |
| 8 |
MDIRP |
— |
| 9 |
MDITN |
— |
| 10 |
MDITP |
— |
| 11 |
VDD33 |
+3V3_CH |
| 12 |
XI |
CH_XI |
| 13 |
XO |
CH_XO |
| 14 |
NRST |
CH_NRST |
| 15 |
PC0 / ADC10 / HSADC0 |
CH_AIN0 |
| 16 |
PC1 / ADC11 / HSADC1 |
CH_AIN1 |
| 17 |
PC2 / ADC12 / HSADC2 / OP3_P0 |
LED_CH_R |
| 18 |
PC3 / ADC13 / HSADC3 / OP3_N0 |
CH_AIN3 |
| 19 |
VDDIO |
+3V3_CH |
| 20 |
VDD33A |
+3V3A_CH |
| 21 |
PA0 / ADC0 / OP3_O0 |
— |
| 22 |
PA4 / ADC4 / DAC1 |
DVP_HSYNC |
| 23 |
PA5 / ADC5 / OP1_O1 / DAC2 |
DVP_VSYNC |
| 24 |
PB0 / ADC8 / OP1_P0 / CMP_P0 |
CH_MCO |
| 25 |
PB1 / ADC9 / CMP_N0 / OP1_N0 |
— |
| 26 |
PE10 |
QSPI_SCK |
| 27 |
PE11 |
QSPI_CS |
| 28 |
PE12 |
QSPI_IO0 |
| 29 |
PE13 |
QSPI_IO1 |
| 30 |
PE14 |
QSPI_IO2 |
| 31 |
PE15 |
QSPI_IO3 |
| 32 |
PB10 |
CH_SCL |
| 33 |
PB11 |
CH_SDA |
| 34 |
VIO18 |
+3V3_CH |
| 35 |
VDDIO |
+3V3_CH |
| 36 |
PB12 |
CAP_PCLK |
| 37 |
PB13 |
CAP_D2 |
| 38 |
PB14 |
CH_MARK |
| 39 |
PD10 |
LOGIC4 |
| 40 |
PD11 |
LOGIC5 |
| 41 |
PD12 |
LOGIC0 |
| 42 |
PD13 |
LOGIC1 |
| 43 |
PD14 |
LOGIC2 |
| 44 |
PD15 |
LOGIC3 |
| 45 |
PF0 |
LED_CH_G |
| 46 |
PF1 |
LED_CH_B |
| 47 |
PF2 |
CAP_PCLK |
| 48 |
VDDK |
VDDK |
| 49 |
VIO18 |
+3V3_CH |
| 50 |
PC6 |
LOGIC6 |
| 51 |
PC7 |
LOGIC7 |
| 52 |
PC8 |
SD_D0 |
| 53 |
PC9 |
SD_D1 |
| 54 |
PA9 / OTG_VBUS |
CH_UART_TX |
| 55 |
PA10 / OTG_ID |
CH_UART_RX |
| 56 |
PA11 / OTG_DM |
J2_DM |
| 57 |
PA12 / OTG_DP |
J2_DP |
| 58 |
PA13 |
— |
| 59 |
VDD33 |
+3V3_CH |
| 60 |
PA14 |
— |
| 61 |
PA15 |
— |
| 62 |
PC10 |
SD_D2 |
| 63 |
PC11 |
SD_D3 |
| 64 |
PC12 |
SD_CLK |
| 65 |
PD0 |
SD_CD |
| 66 |
PD1 |
— |
| 67 |
PD2 |
SD_CMD |
| 68 |
PD3 |
— |
| 69 |
PD4 |
— |
| 70 |
PD5 |
— |
| 71 |
PD6 |
— |
| 72 |
PD7 |
— |
| 73 |
PF3 |
CAP_D9 |
| 74 |
PF4 |
CAP_D8 |
| 75 |
PF5 |
— |
| 76 |
PE0 |
CAP_D0 |
| 77 |
PE1 |
CAP_D1 |
| 78 |
PF14 |
CAP_D5 |
| 79 |
VIO18 |
+3V3_CH |
| 80 |
PB3 / CC1 |
— |
| 81 |
PB4 / CC2 |
— |
| 82 |
PB8 / USB2DP / SWCLK |
CH_USBHS_DP |
| 83 |
PB9 / USB2DM / SWDIO |
CH_USBHS_DM |
| 84 |
SSTXB |
CH_SSTX_N |
| 85 |
SSTXA |
CH_SSTX_P |
| 86 |
VDD12A |
VDD12A |
| 87 |
SSRXB |
SS_RX_N |
| 88 |
SSRXA |
SS_RX_P |
| 89 |
EP |
GND |
3. RP2354B (U2, QFN80) — all pins
| Pin |
Function |
Net |
| 1 |
GPIO4 |
MGMT_SDA |
| 2 |
GPIO5 |
MGMT_SCL |
| 3 |
GPIO6 |
QSPI_SCK_RP |
| 4 |
GPIO7 |
QSPI_CS_RP |
| 5 |
IOVDD |
+3V3 |
| 6 |
GPIO8 |
QSPI_IO0_RP |
| 7 |
GPIO9 |
QSPI_IO1_RP |
| 8 |
GPIO10 |
QSPI_IO2_RP |
| 9 |
GPIO11 |
QSPI_IO3_RP |
| 10 |
DVDD |
+1V1 |
| 11 |
GPIO12 |
LOGIC0_RP |
| 12 |
GPIO13 |
LOGIC1_RP |
| 13 |
GPIO14 |
LOGIC2_RP |
| 14 |
GPIO15 |
LOGIC3_RP |
| 15 |
IOVDD |
+3V3 |
| 16 |
GPIO16 |
LOGIC4_RP |
| 17 |
GPIO17 |
LOGIC5_RP |
| 18 |
GPIO18 |
LOGIC6_RP |
| 19 |
GPIO19 |
LOGIC7_RP |
| 20 |
GPIO20 |
CNT_D0_RP |
| 21 |
GPIO21 |
CNT_D1_RP |
| 22 |
GPIO22 |
CNT_D2_RP |
| 23 |
GPIO23 |
CNT_D3_RP |
| 24 |
IOVDD |
+3V3 |
| 25 |
GPIO24 |
CNT_D4_RP |
| 26 |
GPIO25 |
CNT_D5_RP |
| 27 |
GPIO26 |
CNT_D6_RP |
| 28 |
GPIO27 |
CNT_D7_RP |
| 29 |
IOVDD |
+3V3 |
| 30 |
XIN |
RP_XIN |
| 31 |
XOUT |
RP_XOUT |
| 32 |
DVDD |
+1V1 |
| 33 |
SWCLK |
— |
| 34 |
SWDIO |
— |
| 35 |
RUN |
RP_RUN |
| 36 |
GPIO28 |
CNT_D8_RP |
| 37 |
GPIO29 |
CNT_D9_RP |
| 38 |
GPIO30 |
CNT_PCLK_RP |
| 39 |
GPIO31 |
HSYNC_RP |
| 40 |
GPIO32 |
VSYNC_RP |
| 41 |
IOVDD |
+3V3 |
| 42 |
GPIO33 |
MARK_RP |
| 43 |
GPIO34 |
MCO_RP |
| 44 |
GPIO35 |
SWIO_RP |
| 45 |
GPIO36 |
SWCLK_RP |
| 46 |
GPIO37 |
CH_NRST_RP |
| 47 |
GPIO38 |
CH_PWR_EN |
| 48 |
GPIO39 |
USB_SEL |
| 49 |
GPIO40_ADC0 |
ADC_V3V3CH |
| 50 |
IOVDD |
+3V3 |
| 51 |
DVDD |
+1V1 |
| 52 |
GPIO41_ADC1 |
ADC_VSYS |
| 53 |
GPIO42_ADC2 |
CAP_SEL |
| 54 |
GPIO43_ADC3 |
LED_RP_R |
| 55 |
GPIO44_ADC4 |
SAO_SDA |
| 56 |
GPIO45_ADC5 |
SAO_SCL |
| 57 |
GPIO46_ADC6 |
LED_RP_G |
| 58 |
GPIO47_ADC7 |
LED_RP_B |
| 59 |
ADC_AVDD |
+3V3 |
| 60 |
IOVDD |
+3V3 |
| 61 |
VREG_AVDD |
RP_VREG_AVDD |
| 62 |
VREG_PGND |
GND |
| 63 |
VREG_LX |
RP_VREG_LX |
| 64 |
VREG_VIN |
+3V3 |
| 65 |
VREG_FB |
+1V1 |
| 66 |
USB_DM |
RP_USB_DM |
| 67 |
USB_DP |
RP_USB_DP |
| 68 |
USB_OTP_VDD |
+3V3 |
| 69 |
QSPI_IOVDD |
+3V3 |
| 70 |
QSPI_SD3 |
— |
| 71 |
QSPI_SCLK |
— |
| 72 |
QSPI_SD0 |
— |
| 73 |
QSPI_SD2 |
— |
| 74 |
QSPI_SD1 |
— |
| 75 |
QSPI_SS |
RP_QSPI_SS |
| 76 |
IOVDD |
+3V3 |
| 77 |
GPIO0 |
RP_UART_TX |
| 78 |
GPIO1 |
RP_UART_RX |
| 79 |
GPIO2 |
RP_SDA |
| 80 |
GPIO3 |
RP_SCL |
| 81 |
GND |
GND |