2017-11-12 fpga go

Call for clarification
Open toolchain is Verilog / VHDL / Lattice tools
130 lines of 150us at 24Msps on 16 bits is 7488000 bits
Worked on two experiments: pulser tests and testing new probe, and again, once the probe is refilled
@done 20171111a and 20171112b Readmes

Written on November 12, 2017